^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* Driver for Realtek PCI-Express card reader
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Wei WANG <wei_wang@realsil.com.cn>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/rtsx_pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "rtsx_pcr.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) static u8 rts5249_get_ic_version(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) return val & 0x0F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) static void rts5249_fill_driving(struct rtsx_pcr *pcr, u8 voltage)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) u8 driving_3v3[4][3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) {0x11, 0x11, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) {0x55, 0x55, 0x5C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) {0xFF, 0xFF, 0xFF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) {0x96, 0x96, 0x96},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) u8 driving_1v8[4][3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) {0xC4, 0xC4, 0xC4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) {0x3C, 0x3C, 0x3C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) {0xFE, 0xFE, 0xFE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) {0xB3, 0xB3, 0xB3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) u8 (*driving)[3], drive_sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) if (voltage == OUTPUT_3V3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) driving = driving_3v3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) drive_sel = pcr->sd30_drive_sel_3v3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) driving = driving_1v8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) drive_sel = pcr->sd30_drive_sel_1v8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CLK_DRIVE_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 0xFF, driving[drive_sel][0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CMD_DRIVE_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 0xFF, driving[drive_sel][1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DAT_DRIVE_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 0xFF, driving[drive_sel][2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static void rtsx_base_fetch_vendor_settings(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct pci_dev *pdev = pcr->pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) pci_read_config_dword(pdev, PCR_SETTING_REG1, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) if (!rtsx_vendor_setting_valid(reg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) pcr_dbg(pcr, "skip fetch vendor setting\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) pcr->aspm_en = rtsx_reg_to_aspm(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) pcr->sd30_drive_sel_1v8 = rtsx_reg_to_sd30_drive_sel_1v8(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) pcr->card_drive_sel &= 0x3F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) pci_read_config_dword(pdev, PCR_SETTING_REG2, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) if (rtsx_check_mmc_support(reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) pcr->extra_caps |= EXTRA_CAPS_NO_MMC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) if (rtsx_reg_check_reverse_socket(reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) pcr->flags |= PCR_REVERSE_SOCKET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static void rts5249_init_from_cfg(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct pci_dev *pdev = pcr->pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) int l1ss;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct rtsx_cr_option *option = &(pcr->option);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) u32 lval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) l1ss = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) if (!l1ss)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) pci_read_config_dword(pdev, l1ss + PCI_L1SS_CTL1, &lval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) if (0 == (lval & 0x0F))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) rtsx_pci_enable_oobs_polling(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) rtsx_pci_disable_oobs_polling(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) if (lval & PCI_L1SS_CTL1_ASPM_L1_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) rtsx_set_dev_flag(pcr, ASPM_L1_1_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) if (lval & PCI_L1SS_CTL1_ASPM_L1_2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) rtsx_set_dev_flag(pcr, ASPM_L1_2_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) if (lval & PCI_L1SS_CTL1_PCIPM_L1_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) rtsx_set_dev_flag(pcr, PM_L1_1_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) if (lval & PCI_L1SS_CTL1_PCIPM_L1_2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) rtsx_set_dev_flag(pcr, PM_L1_2_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) if (option->ltr_en) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) if (val & PCI_EXP_DEVCTL2_LTR_EN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) option->ltr_enabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) option->ltr_active = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) rtsx_set_ltr_latency(pcr, option->ltr_active_latency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) option->ltr_enabled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static int rts5249_init_from_hw(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct rtsx_cr_option *option = &(pcr->option);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) | PM_L1_1_EN | PM_L1_2_EN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) option->force_clkreq_0 = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) option->force_clkreq_0 = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static void rts52xa_save_content_from_efuse(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) u8 cnt, sv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) u16 j = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) u8 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) REG_EFUSE_BYPASS | REG_EFUSE_POR, REG_EFUSE_POR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) pcr_dbg(pcr, "Enable efuse por!");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) pcr_dbg(pcr, "save efuse to autoload");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) rtsx_pci_write_register(pcr, RTS525A_EFUSE_ADD, REG_EFUSE_ADD_MASK, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) rtsx_pci_write_register(pcr, RTS525A_EFUSE_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) REG_EFUSE_ENABLE | REG_EFUSE_MODE, REG_EFUSE_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* Wait transfer end */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) for (j = 0; j < 1024; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) rtsx_pci_read_register(pcr, RTS525A_EFUSE_CTL, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) if ((tmp & 0x80) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) rtsx_pci_read_register(pcr, RTS525A_EFUSE_DATA, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) cnt = val & 0x0F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) sv = val & 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) if (sv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) for (i = 0; i < 4; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) rtsx_pci_write_register(pcr, RTS525A_EFUSE_ADD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) REG_EFUSE_ADD_MASK, 0x04 + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) rtsx_pci_write_register(pcr, RTS525A_EFUSE_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) REG_EFUSE_ENABLE | REG_EFUSE_MODE, REG_EFUSE_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* Wait transfer end */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) for (j = 0; j < 1024; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) rtsx_pci_read_register(pcr, RTS525A_EFUSE_CTL, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) if ((tmp & 0x80) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) rtsx_pci_read_register(pcr, RTS525A_EFUSE_DATA, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) rtsx_pci_write_register(pcr, 0xFF04 + i, 0xFF, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) rtsx_pci_write_register(pcr, 0xFF04, 0xFF, (u8)PCI_VID(pcr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) rtsx_pci_write_register(pcr, 0xFF05, 0xFF, (u8)(PCI_VID(pcr) >> 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) rtsx_pci_write_register(pcr, 0xFF06, 0xFF, (u8)PCI_PID(pcr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) rtsx_pci_write_register(pcr, 0xFF07, 0xFF, (u8)(PCI_PID(pcr) >> 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) for (i = 0; i < cnt * 4; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if (sv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) rtsx_pci_write_register(pcr, RTS525A_EFUSE_ADD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) REG_EFUSE_ADD_MASK, 0x08 + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) rtsx_pci_write_register(pcr, RTS525A_EFUSE_ADD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) REG_EFUSE_ADD_MASK, 0x04 + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) rtsx_pci_write_register(pcr, RTS525A_EFUSE_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) REG_EFUSE_ENABLE | REG_EFUSE_MODE, REG_EFUSE_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /* Wait transfer end */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) for (j = 0; j < 1024; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) rtsx_pci_read_register(pcr, RTS525A_EFUSE_CTL, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if ((tmp & 0x80) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) rtsx_pci_read_register(pcr, RTS525A_EFUSE_DATA, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) rtsx_pci_write_register(pcr, 0xFF08 + i, 0xFF, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) rtsx_pci_write_register(pcr, 0xFF00, 0xFF, (cnt & 0x7F) | 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) REG_EFUSE_BYPASS | REG_EFUSE_POR, REG_EFUSE_BYPASS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) pcr_dbg(pcr, "Disable efuse por!");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static void rts52xa_save_content_to_autoload_space(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) rtsx_pci_read_register(pcr, RESET_LOAD_REG, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (val & 0x02) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) rtsx_pci_read_register(pcr, RTS525A_BIOS_CFG, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (val & RTS525A_LOAD_BIOS_FLAG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) rtsx_pci_write_register(pcr, RTS525A_BIOS_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) RTS525A_LOAD_BIOS_FLAG, RTS525A_CLEAR_BIOS_FLAG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) REG_EFUSE_POWER_MASK, REG_EFUSE_POWERON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) pcr_dbg(pcr, "Power ON efuse!");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) rts52xa_save_content_from_efuse(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) rtsx_pci_read_register(pcr, RTS524A_PME_FORCE_CTL, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (!(val & 0x08))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) rts52xa_save_content_from_efuse(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) pcr_dbg(pcr, "Load from autoload");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) rtsx_pci_write_register(pcr, 0xFF00, 0xFF, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) rtsx_pci_write_register(pcr, 0xFF04, 0xFF, (u8)PCI_VID(pcr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) rtsx_pci_write_register(pcr, 0xFF05, 0xFF, (u8)(PCI_VID(pcr) >> 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) rtsx_pci_write_register(pcr, 0xFF06, 0xFF, (u8)PCI_PID(pcr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) rtsx_pci_write_register(pcr, 0xFF07, 0xFF, (u8)(PCI_PID(pcr) >> 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static int rts5249_extra_init_hw(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) struct rtsx_cr_option *option = &(pcr->option);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) rts5249_init_from_cfg(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) rts5249_init_from_hw(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) rtsx_pci_init_cmd(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) rts52xa_save_content_to_autoload_space(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /* Rest L1SUB Config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, L1SUB_CONFIG3, 0xFF, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /* Configure GPIO as output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, GPIO_CTL, 0x02, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /* Reset ASPM state to default value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, ASPM_FORCE_CTL, 0x3F, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /* Switch LDO3318 source from DV33 to card_3v3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /* LED shine disabled, set initial shine cycle period */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OLT_LED_CTL, 0x0F, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /* Configure driving */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) rts5249_fill_driving(pcr, OUTPUT_3V3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) if (pcr->flags & PCR_REVERSE_SOCKET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB0, 0xB0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB0, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) rtsx_pci_send_cmd(pcr, CMD_TIMEOUT_DEF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) rtsx_pci_write_register(pcr, REG_VREF, PWD_SUSPND_EN, PWD_SUSPND_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3, 0x01, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL, 0x30, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) rtsx_pci_write_register(pcr, PME_FORCE_CTL, 0xFF, 0x30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) rtsx_pci_write_register(pcr, PM_CTRL3, 0x01, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) * If u_force_clkreq_0 is enabled, CLKREQ# PIN will be forced
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) * to drive low, and we forcibly request clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (option->force_clkreq_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) rtsx_pci_write_register(pcr, PETXCFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) rtsx_pci_write_register(pcr, PETXCFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x10, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) REG_EFUSE_POWER_MASK, REG_EFUSE_POWEROFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) pcr_dbg(pcr, "Power OFF efuse!");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) static int rts5249_optimize_phy(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) err = rtsx_pci_write_register(pcr, PM_CTRL3, D3_DELINK_MODE_EN, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) err = rtsx_pci_write_phy_register(pcr, PHY_REV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) PHY_REV_RESV | PHY_REV_RXIDLE_LATCHED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) PHY_REV_P1_EN | PHY_REV_RXIDLE_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) PHY_REV_CLKREQ_TX_EN | PHY_REV_RX_PWST |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) PHY_REV_CLKREQ_DT_1_0 | PHY_REV_STOP_CLKRD |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) PHY_REV_STOP_CLKWR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) err = rtsx_pci_write_phy_register(pcr, PHY_BPCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) PHY_BPCR_IBRXSEL | PHY_BPCR_IBTXSEL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) PHY_BPCR_IB_FILTER | PHY_BPCR_CMIRROR_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) err = rtsx_pci_write_phy_register(pcr, PHY_PCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) PHY_PCR_FORCE_CODE | PHY_PCR_OOBS_CALI_50 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) PHY_PCR_OOBS_VCM_08 | PHY_PCR_OOBS_SEN_90 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) PHY_PCR_RSSI_EN | PHY_PCR_RX10K);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) err = rtsx_pci_write_phy_register(pcr, PHY_RCR2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) PHY_RCR2_EMPHASE_EN | PHY_RCR2_NADJR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) PHY_RCR2_CDR_SR_2 | PHY_RCR2_FREQSEL_12 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) PHY_RCR2_CDR_SC_12P | PHY_RCR2_CALIB_LATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) err = rtsx_pci_write_phy_register(pcr, PHY_FLD4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) PHY_FLD4_FLDEN_SEL | PHY_FLD4_REQ_REF |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) PHY_FLD4_RXAMP_OFF | PHY_FLD4_REQ_ADDA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) PHY_FLD4_BER_COUNT | PHY_FLD4_BER_TIMER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) PHY_FLD4_BER_CHK_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) err = rtsx_pci_write_phy_register(pcr, PHY_RDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) PHY_RDR_RXDSEL_1_9 | PHY_SSC_AUTO_PWD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) err = rtsx_pci_write_phy_register(pcr, PHY_RCR1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) PHY_RCR1_ADP_TIME_4 | PHY_RCR1_VCO_COARSE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) err = rtsx_pci_write_phy_register(pcr, PHY_FLD3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) PHY_FLD3_TIMER_4 | PHY_FLD3_TIMER_6 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) PHY_FLD3_RXDELINK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) return rtsx_pci_write_phy_register(pcr, PHY_TUNE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) PHY_TUNE_TUNEREF_1_0 | PHY_TUNE_VBGSEL_1252 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) PHY_TUNE_SDBUS_33 | PHY_TUNE_TUNED18 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) PHY_TUNE_TUNED12 | PHY_TUNE_TUNEA12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) static int rtsx_base_turn_on_led(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) static int rtsx_base_turn_off_led(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static int rtsx_base_enable_auto_blink(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) static int rtsx_base_disable_auto_blink(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) static int rtsx_base_card_power_on(struct rtsx_pcr *pcr, int card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) struct rtsx_cr_option *option = &pcr->option;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) if (option->ocp_en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) rtsx_pci_enable_ocp(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) rtsx_pci_init_cmd(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) SD_POWER_MASK, SD_VCC_PARTIAL_POWER_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) LDO3318_PWR_MASK, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) err = rtsx_pci_send_cmd(pcr, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) msleep(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) rtsx_pci_init_cmd(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) SD_POWER_MASK, SD_VCC_POWER_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) LDO3318_PWR_MASK, 0x06);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) return rtsx_pci_send_cmd(pcr, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) static int rtsx_base_card_power_off(struct rtsx_pcr *pcr, int card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) struct rtsx_cr_option *option = &pcr->option;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) if (option->ocp_en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) rtsx_pci_disable_ocp(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) rtsx_pci_write_register(pcr, CARD_PWR_CTL, SD_POWER_MASK, SD_POWER_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) rtsx_pci_write_register(pcr, PWR_GATE_CTRL, LDO3318_PWR_MASK, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) static int rtsx_base_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) u16 append;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) switch (voltage) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) case OUTPUT_3V3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) err = rtsx_pci_update_phy(pcr, PHY_TUNE, PHY_TUNE_VOLTAGE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) PHY_TUNE_VOLTAGE_3V3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) case OUTPUT_1V8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) append = PHY_TUNE_D18_1V8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) if (CHK_PCI_PID(pcr, 0x5249)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) err = rtsx_pci_update_phy(pcr, PHY_BACR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) PHY_BACR_BASIC_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) append = PHY_TUNE_D18_1V7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) err = rtsx_pci_update_phy(pcr, PHY_TUNE, PHY_TUNE_VOLTAGE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) append);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) pcr_dbg(pcr, "unknown output voltage %d\n", voltage);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) /* set pad drive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) rtsx_pci_init_cmd(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) rts5249_fill_driving(pcr, voltage);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) return rtsx_pci_send_cmd(pcr, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) static const struct pcr_ops rts5249_pcr_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) .fetch_vendor_settings = rtsx_base_fetch_vendor_settings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) .extra_init_hw = rts5249_extra_init_hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) .optimize_phy = rts5249_optimize_phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) .turn_on_led = rtsx_base_turn_on_led,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) .turn_off_led = rtsx_base_turn_off_led,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) .enable_auto_blink = rtsx_base_enable_auto_blink,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) .disable_auto_blink = rtsx_base_disable_auto_blink,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) .card_power_on = rtsx_base_card_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) .card_power_off = rtsx_base_card_power_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) .switch_output_voltage = rtsx_base_switch_output_voltage,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) /* SD Pull Control Enable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) * SD_DAT[3:0] ==> pull up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) * SD_CD ==> pull up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) * SD_WP ==> pull up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) * SD_CMD ==> pull up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) * SD_CLK ==> pull down
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) static const u32 rts5249_sd_pull_ctl_enable_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) RTSX_REG_PAIR(CARD_PULL_CTL1, 0x66),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) RTSX_REG_PAIR(CARD_PULL_CTL4, 0xAA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) /* SD Pull Control Disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) * SD_DAT[3:0] ==> pull down
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) * SD_CD ==> pull up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) * SD_WP ==> pull down
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) * SD_CMD ==> pull down
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) * SD_CLK ==> pull down
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) static const u32 rts5249_sd_pull_ctl_disable_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) RTSX_REG_PAIR(CARD_PULL_CTL1, 0x66),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) /* MS Pull Control Enable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) * MS CD ==> pull up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) * others ==> pull down
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) static const u32 rts5249_ms_pull_ctl_enable_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) /* MS Pull Control Disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) * MS CD ==> pull up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) * others ==> pull down
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) static const u32 rts5249_ms_pull_ctl_disable_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) void rts5249_init_params(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) struct rtsx_cr_option *option = &(pcr->option);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) pcr->num_slots = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) pcr->ops = &rts5249_pcr_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) pcr->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) pcr->aspm_en = ASPM_L1_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) pcr->tx_initial_phase = SET_CLOCK_PHASE(1, 29, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) pcr->ic_version = rts5249_get_ic_version(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) pcr->sd_pull_ctl_enable_tbl = rts5249_sd_pull_ctl_enable_tbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) pcr->sd_pull_ctl_disable_tbl = rts5249_sd_pull_ctl_disable_tbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) pcr->ms_pull_ctl_enable_tbl = rts5249_ms_pull_ctl_enable_tbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) pcr->ms_pull_ctl_disable_tbl = rts5249_ms_pull_ctl_disable_tbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) pcr->reg_pm_ctrl3 = PM_CTRL3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) option->dev_flags = (LTR_L1SS_PWR_GATE_CHECK_CARD_EN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) | LTR_L1SS_PWR_GATE_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) option->ltr_en = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) /* Init latency of active, idle, L1OFF to 60us, 300us, 3ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) option->ltr_active_latency = LTR_ACTIVE_LATENCY_DEF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) option->ltr_idle_latency = LTR_IDLE_LATENCY_DEF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) option->ltr_l1off_latency = LTR_L1OFF_LATENCY_DEF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) option->l1_snooze_delay = L1_SNOOZE_DELAY_DEF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) option->ltr_l1off_sspwrgate = LTR_L1OFF_SSPWRGATE_5249_DEF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) option->ltr_l1off_snooze_sspwrgate =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) LTR_L1OFF_SNOOZE_SSPWRGATE_5249_DEF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) static int rts524a_write_phy(struct rtsx_pcr *pcr, u8 addr, u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) addr = addr & 0x80 ? (addr & 0x7F) | 0x40 : addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) return __rtsx_pci_write_phy_register(pcr, addr, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) static int rts524a_read_phy(struct rtsx_pcr *pcr, u8 addr, u16 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) addr = addr & 0x80 ? (addr & 0x7F) | 0x40 : addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) return __rtsx_pci_read_phy_register(pcr, addr, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) static int rts524a_optimize_phy(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) err = rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) D3_DELINK_MODE_EN, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) rtsx_pci_write_phy_register(pcr, PHY_PCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) PHY_PCR_FORCE_CODE | PHY_PCR_OOBS_CALI_50 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) PHY_PCR_OOBS_VCM_08 | PHY_PCR_OOBS_SEN_90 | PHY_PCR_RSSI_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) rtsx_pci_write_phy_register(pcr, PHY_SSCCR3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) PHY_SSCCR3_STEP_IN | PHY_SSCCR3_CHECK_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) if (is_version(pcr, 0x524A, IC_VER_A)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) rtsx_pci_write_phy_register(pcr, PHY_SSCCR3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) PHY_SSCCR3_STEP_IN | PHY_SSCCR3_CHECK_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) rtsx_pci_write_phy_register(pcr, PHY_SSCCR2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) PHY_SSCCR2_PLL_NCODE | PHY_SSCCR2_TIME0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) PHY_SSCCR2_TIME2_WIDTH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) rtsx_pci_write_phy_register(pcr, PHY_ANA1A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) PHY_ANA1A_TXR_LOOPBACK | PHY_ANA1A_RXT_BIST |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) PHY_ANA1A_TXR_BIST | PHY_ANA1A_REV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) rtsx_pci_write_phy_register(pcr, PHY_ANA1D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) PHY_ANA1D_DEBUG_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) rtsx_pci_write_phy_register(pcr, PHY_DIG1E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) PHY_DIG1E_REV | PHY_DIG1E_D0_X_D1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) PHY_DIG1E_RX_ON_HOST | PHY_DIG1E_RCLK_REF_HOST |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) PHY_DIG1E_RCLK_TX_EN_KEEP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) PHY_DIG1E_RCLK_TX_TERM_KEEP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) PHY_DIG1E_RCLK_RX_EIDLE_ON | PHY_DIG1E_TX_TERM_KEEP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) PHY_DIG1E_RX_TERM_KEEP | PHY_DIG1E_TX_EN_KEEP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) PHY_DIG1E_RX_EN_KEEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) rtsx_pci_write_phy_register(pcr, PHY_ANA08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) PHY_ANA08_RX_EQ_DCGAIN | PHY_ANA08_SEL_RX_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) PHY_ANA08_RX_EQ_VAL | PHY_ANA08_SCP | PHY_ANA08_SEL_IPI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) static int rts524a_extra_init_hw(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) rts5249_extra_init_hw(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) rtsx_pci_write_register(pcr, FUNC_FORCE_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) FORCE_ASPM_L1_EN, FORCE_ASPM_L1_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) rtsx_pci_write_register(pcr, PM_EVENT_DEBUG, PME_DEBUG_0, PME_DEBUG_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) rtsx_pci_write_register(pcr, LDO_VCC_CFG1, LDO_VCC_LMT_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) LDO_VCC_LMT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) rtsx_pci_write_register(pcr, PCLK_CTL, PCLK_MODE_SEL, PCLK_MODE_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) if (is_version(pcr, 0x524A, IC_VER_A)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) rtsx_pci_write_register(pcr, LDO_DV18_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) LDO_DV18_SR_MASK, LDO_DV18_SR_DF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) rtsx_pci_write_register(pcr, LDO_VCC_CFG1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) LDO_VCC_REF_TUNE_MASK, LDO_VCC_REF_1V2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) rtsx_pci_write_register(pcr, LDO_VIO_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) LDO_VIO_REF_TUNE_MASK, LDO_VIO_REF_1V2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) rtsx_pci_write_register(pcr, LDO_VIO_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) LDO_VIO_SR_MASK, LDO_VIO_SR_DF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) rtsx_pci_write_register(pcr, LDO_DV12S_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) LDO_REF12_TUNE_MASK, LDO_REF12_TUNE_DF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) rtsx_pci_write_register(pcr, SD40_LDO_CTL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) SD40_VIO_TUNE_MASK, SD40_VIO_TUNE_1V7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) static void rts5250_set_l1off_cfg_sub_d0(struct rtsx_pcr *pcr, int active)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) struct rtsx_cr_option *option = &(pcr->option);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) u32 interrupt = rtsx_pci_readl(pcr, RTSX_BIPR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) int card_exist = (interrupt & SD_EXIST) | (interrupt & MS_EXIST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) int aspm_L1_1, aspm_L1_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) u8 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) aspm_L1_1 = rtsx_check_dev_flag(pcr, ASPM_L1_1_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) aspm_L1_2 = rtsx_check_dev_flag(pcr, ASPM_L1_2_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) if (active) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) /* Run, latency: 60us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) if (aspm_L1_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) val = option->ltr_l1off_snooze_sspwrgate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) /* L1off, latency: 300us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) if (aspm_L1_2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) val = option->ltr_l1off_sspwrgate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) if (aspm_L1_1 || aspm_L1_2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) if (rtsx_check_dev_flag(pcr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) LTR_L1SS_PWR_GATE_CHECK_CARD_EN)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) if (card_exist)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) val &= ~L1OFF_MBIAS2_EN_5250;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) val |= L1OFF_MBIAS2_EN_5250;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) rtsx_set_l1off_sub(pcr, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) static const struct pcr_ops rts524a_pcr_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) .write_phy = rts524a_write_phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) .read_phy = rts524a_read_phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) .fetch_vendor_settings = rtsx_base_fetch_vendor_settings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) .extra_init_hw = rts524a_extra_init_hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) .optimize_phy = rts524a_optimize_phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) .turn_on_led = rtsx_base_turn_on_led,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) .turn_off_led = rtsx_base_turn_off_led,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) .enable_auto_blink = rtsx_base_enable_auto_blink,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) .disable_auto_blink = rtsx_base_disable_auto_blink,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) .card_power_on = rtsx_base_card_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) .card_power_off = rtsx_base_card_power_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) .switch_output_voltage = rtsx_base_switch_output_voltage,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) .set_l1off_cfg_sub_d0 = rts5250_set_l1off_cfg_sub_d0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) void rts524a_init_params(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) rts5249_init_params(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 29, 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) pcr->option.ltr_l1off_sspwrgate = LTR_L1OFF_SSPWRGATE_5250_DEF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) pcr->option.ltr_l1off_snooze_sspwrgate =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) LTR_L1OFF_SNOOZE_SSPWRGATE_5250_DEF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) pcr->reg_pm_ctrl3 = RTS524A_PM_CTRL3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) pcr->ops = &rts524a_pcr_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) pcr->option.ocp_en = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) if (pcr->option.ocp_en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) pcr->hw_param.interrupt_en |= SD_OC_INT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) pcr->hw_param.ocp_glitch = SD_OCP_GLITCH_10M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) pcr->option.sd_800mA_ocp_thd = RTS524A_OCP_THD_800;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) static int rts525a_card_power_on(struct rtsx_pcr *pcr, int card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) rtsx_pci_write_register(pcr, LDO_VCC_CFG1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) LDO_VCC_TUNE_MASK, LDO_VCC_3V3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) return rtsx_base_card_power_on(pcr, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) static int rts525a_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) switch (voltage) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) case OUTPUT_3V3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) rtsx_pci_write_register(pcr, LDO_CONFIG2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) LDO_D3318_MASK, LDO_D3318_33V);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) rtsx_pci_write_register(pcr, SD_PAD_CTL, SD_IO_USING_1V8, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) case OUTPUT_1V8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) rtsx_pci_write_register(pcr, LDO_CONFIG2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) LDO_D3318_MASK, LDO_D3318_18V);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) rtsx_pci_write_register(pcr, SD_PAD_CTL, SD_IO_USING_1V8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) SD_IO_USING_1V8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) rtsx_pci_init_cmd(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) rts5249_fill_driving(pcr, voltage);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) return rtsx_pci_send_cmd(pcr, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) static int rts525a_optimize_phy(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) err = rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) D3_DELINK_MODE_EN, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) rtsx_pci_write_phy_register(pcr, _PHY_FLD0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) _PHY_FLD0_CLK_REQ_20C | _PHY_FLD0_RX_IDLE_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) _PHY_FLD0_BIT_ERR_RSTN | _PHY_FLD0_BER_COUNT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) _PHY_FLD0_BER_TIMER | _PHY_FLD0_CHECK_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) rtsx_pci_write_phy_register(pcr, _PHY_ANA03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) _PHY_ANA03_TIMER_MAX | _PHY_ANA03_OOBS_DEB_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) _PHY_CMU_DEBUG_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) if (is_version(pcr, 0x525A, IC_VER_A))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) rtsx_pci_write_phy_register(pcr, _PHY_REV0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) _PHY_REV0_FILTER_OUT | _PHY_REV0_CDR_BYPASS_PFD |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) _PHY_REV0_CDR_RX_IDLE_BYPASS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) static int rts525a_extra_init_hw(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) rts5249_extra_init_hw(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) rtsx_pci_write_register(pcr, RTS5250_CLK_CFG3, RTS525A_CFG_MEM_PD, RTS525A_CFG_MEM_PD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) rtsx_pci_write_register(pcr, PCLK_CTL, PCLK_MODE_SEL, PCLK_MODE_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) if (is_version(pcr, 0x525A, IC_VER_A)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) rtsx_pci_write_register(pcr, L1SUB_CONFIG2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) L1SUB_AUTO_CFG, L1SUB_AUTO_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) rtsx_pci_write_register(pcr, RREF_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) RREF_VBGSEL_MASK, RREF_VBGSEL_1V25);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) rtsx_pci_write_register(pcr, LDO_VIO_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) LDO_VIO_TUNE_MASK, LDO_VIO_1V7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) rtsx_pci_write_register(pcr, LDO_DV12S_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) LDO_D12_TUNE_MASK, LDO_D12_TUNE_DF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) rtsx_pci_write_register(pcr, LDO_AV12S_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) LDO_AV12S_TUNE_MASK, LDO_AV12S_TUNE_DF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) rtsx_pci_write_register(pcr, LDO_VCC_CFG0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) LDO_VCC_LMTVTH_MASK, LDO_VCC_LMTVTH_2A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) rtsx_pci_write_register(pcr, OOBS_CONFIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) OOBS_AUTOK_DIS | OOBS_VAL_MASK, 0x89);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) static const struct pcr_ops rts525a_pcr_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) .fetch_vendor_settings = rtsx_base_fetch_vendor_settings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) .extra_init_hw = rts525a_extra_init_hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) .optimize_phy = rts525a_optimize_phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) .turn_on_led = rtsx_base_turn_on_led,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) .turn_off_led = rtsx_base_turn_off_led,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) .enable_auto_blink = rtsx_base_enable_auto_blink,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) .disable_auto_blink = rtsx_base_disable_auto_blink,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) .card_power_on = rts525a_card_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) .card_power_off = rtsx_base_card_power_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) .switch_output_voltage = rts525a_switch_output_voltage,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) .set_l1off_cfg_sub_d0 = rts5250_set_l1off_cfg_sub_d0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) void rts525a_init_params(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) rts5249_init_params(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) pcr->tx_initial_phase = SET_CLOCK_PHASE(25, 29, 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) pcr->option.ltr_l1off_sspwrgate = LTR_L1OFF_SSPWRGATE_5250_DEF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) pcr->option.ltr_l1off_snooze_sspwrgate =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) LTR_L1OFF_SNOOZE_SSPWRGATE_5250_DEF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) pcr->reg_pm_ctrl3 = RTS524A_PM_CTRL3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) pcr->ops = &rts525a_pcr_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) pcr->option.ocp_en = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) if (pcr->option.ocp_en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) pcr->hw_param.interrupt_en |= SD_OC_INT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) pcr->hw_param.ocp_glitch = SD_OCP_GLITCH_10M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) pcr->option.sd_800mA_ocp_thd = RTS525A_OCP_THD_800;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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