^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* Driver for Realtek PCI-Express card reader
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright(c) 2018-2019 Realtek Semiconductor Corp. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Ricky WU <ricky_wu@realtek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Rui FENG <rui_feng@realsil.com.cn>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Wei WANG <wei_wang@realsil.com.cn>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #ifndef RTS5228_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define RTS5228_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define RTS5228_AUTOLOAD_CFG0 0xFF7B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define RTS5228_AUTOLOAD_CFG1 0xFF7C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define RTS5228_AUTOLOAD_CFG2 0xFF7D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define RTS5228_AUTOLOAD_CFG3 0xFF7E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define RTS5228_AUTOLOAD_CFG4 0xFF7F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define RTS5228_REG_VREF 0xFE97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define RTS5228_PWD_SUSPND_EN (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define RTS5228_PAD_H3L1 0xFF79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PAD_GPIO_H3L1 (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* SSC_CTL2 0xFC12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define RTS5228_SSC_DEPTH_MASK 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define RTS5228_SSC_DEPTH_DISALBE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define RTS5228_SSC_DEPTH_8M 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define RTS5228_SSC_DEPTH_4M 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define RTS5228_SSC_DEPTH_2M 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define RTS5228_SSC_DEPTH_1M 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define RTS5228_SSC_DEPTH_512K 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define RTS5228_SSC_DEPTH_256K 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define RTS5228_SSC_DEPTH_128K 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* DMACTL 0xFE2C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define RTS5228_DMA_PACK_SIZE_MASK 0xF0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define RTS5228_REG_LDO12_CFG 0xFF6E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define RTS5228_LDO12_VO_TUNE_MASK (0x07<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define RTS5228_LDO12_100 (0x00<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define RTS5228_LDO12_105 (0x01<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define RTS5228_LDO12_110 (0x02<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define RTS5228_LDO12_115 (0x03<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define RTS5228_LDO12_120 (0x04<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define RTS5228_LDO12_125 (0x05<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define RTS5228_LDO12_130 (0x06<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define RTS5228_LDO12_135 (0x07<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define RTS5228_REG_PWD_LDO12 (0x01<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define RTS5228_REG_LDO12_L12 0xFF6F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define RTS5228_LDO12_L12_MASK (0x07<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define RTS5228_LDO12_L12_120 (0x04<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* LDO control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define RTS5228_CARD_PWR_CTL 0xFD50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define RTS5228_PUPDC (0x01<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define RTS5228_LDO1233318_POW_CTL 0xFF70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define RTS5228_LDO3318_POWERON (0x01<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define RTS5228_LDO1_POWEROFF (0x00<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define RTS5228_LDO1_SOFTSTART (0x01<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define RTS5228_LDO1_FULLON (0x03<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define RTS5228_LDO1_POWERON_MASK (0x03<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define RTS5228_LDO_POWERON_MASK (0x0F<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define RTS5228_DV3318_CFG 0xFF71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define RTS5228_DV3318_TUNE_MASK (0x07<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define RTS5228_DV3318_17 (0x00<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define RTS5228_DV3318_1V75 (0x01<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define RTS5228_DV3318_18 (0x02<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define RTS5228_DV3318_1V85 (0x03<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define RTS5228_DV3318_19 (0x04<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define RTS5228_DV3318_33 (0x07<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define RTS5228_DV3318_SR_MASK (0x03<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define RTS5228_DV3318_SR_0 (0x00<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define RTS5228_DV3318_SR_250 (0x01<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define RTS5228_DV3318_SR_500 (0x02<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define RTS5228_DV3318_SR_1000 (0x03<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define RTS5228_LDO1_CFG0 0xFF72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define RTS5228_LDO1_OCP_THD_MASK (0x07<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define RTS5228_LDO1_OCP_EN (0x01<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define RTS5228_LDO1_OCP_LMT_THD_MASK (0x03<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define RTS5228_LDO1_OCP_LMT_EN (0x01<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define RTS5228_LDO1_OCP_THD_730 (0x00<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define RTS5228_LDO1_OCP_THD_780 (0x01<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define RTS5228_LDO1_OCP_THD_860 (0x02<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define RTS5228_LDO1_OCP_THD_930 (0x03<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define RTS5228_LDO1_OCP_THD_1000 (0x04<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define RTS5228_LDO1_OCP_THD_1070 (0x05<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define RTS5228_LDO1_OCP_THD_1140 (0x06<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define RTS5228_LDO1_OCP_THD_1220 (0x07<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define RTS5228_LDO1_LMT_THD_450 (0x00<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define RTS5228_LDO1_LMT_THD_1000 (0x01<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define RTS5228_LDO1_LMT_THD_1500 (0x02<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define RTS5228_LDO1_LMT_THD_2000 (0x03<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define RTS5228_LDO1_CFG1 0xFF73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define RTS5228_LDO1_SR_TIME_MASK (0x03<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define RTS5228_LDO1_SR_0_0 (0x00<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define RTS5228_LDO1_SR_0_25 (0x01<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define RTS5228_LDO1_SR_0_5 (0x02<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define RTS5228_LDO1_SR_1_0 (0x03<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define RTS5228_LDO1_TUNE_MASK (0x07<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define RTS5228_LDO1_18 (0x05<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define RTS5228_LDO1_33 (0x07<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define RTS5228_LDO1_PWD_MASK (0x01<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define RTS5228_AUXCLK_GAT_CTL 0xFF74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define RTS5228_REG_RREF_CTL_0 0xFF75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define RTS5228_FORCE_RREF_EXTL (0x01<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define RTS5228_REG_BG33_MASK (0x07<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define RTS5228_RREF_12_1V (0x04<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define RTS5228_RREF_12_3V (0x05<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define RTS5228_REG_RREF_CTL_1 0xFF76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define RTS5228_REG_RREF_CTL_2 0xFF77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define RTS5228_TEST_INTL_RREF (0x01<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define RTS5228_DGLCH_TIME_MASK (0x03<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define RTS5228_DGLCH_TIME_50 (0x00<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define RTS5228_DGLCH_TIME_75 (0x01<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define RTS5228_DGLCH_TIME_100 (0x02<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define RTS5228_DGLCH_TIME_125 (0x03<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define RTS5228_REG_REXT_TUNE_MASK (0x1F<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define RTS5228_REG_PME_FORCE_CTL 0xFF78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define FORCE_PM_CONTROL 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define FORCE_PM_VALUE 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* Single LUN, support SD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define DEFAULT_SINGLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define SD_LUN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* For Change_FPGA_SSCClock Function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define MULTIPLY_BY_1 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define MULTIPLY_BY_2 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define MULTIPLY_BY_3 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define MULTIPLY_BY_4 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define MULTIPLY_BY_5 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define MULTIPLY_BY_6 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define MULTIPLY_BY_7 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define MULTIPLY_BY_8 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define MULTIPLY_BY_9 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define MULTIPLY_BY_10 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define DIVIDE_BY_2 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define DIVIDE_BY_3 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define DIVIDE_BY_4 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define DIVIDE_BY_5 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define DIVIDE_BY_6 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define DIVIDE_BY_7 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define DIVIDE_BY_8 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define DIVIDE_BY_9 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define DIVIDE_BY_10 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) int rts5228_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #endif /* RTS5228_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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