Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /* Driver for Realtek PCI-Express card reader
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Author:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *   Wei WANG <wei_wang@realsil.com.cn>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *   Roger Tseng <rogerable@realtek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/rtsx_pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include "rtsx_pcr.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) static u8 rts5227_get_ic_version(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 	u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 	rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	return val & 0x0F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) static void rts5227_fill_driving(struct rtsx_pcr *pcr, u8 voltage)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	u8 driving_3v3[4][3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 		{0x13, 0x13, 0x13},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 		{0x96, 0x96, 0x96},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 		{0x7F, 0x7F, 0x7F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 		{0x96, 0x96, 0x96},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	u8 driving_1v8[4][3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 		{0x99, 0x99, 0x99},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 		{0xAA, 0xAA, 0xAA},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 		{0xFE, 0xFE, 0xFE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 		{0xB3, 0xB3, 0xB3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	u8 (*driving)[3], drive_sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	if (voltage == OUTPUT_3V3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 		driving = driving_3v3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 		drive_sel = pcr->sd30_drive_sel_3v3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 		driving = driving_1v8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 		drive_sel = pcr->sd30_drive_sel_1v8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CLK_DRIVE_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 			0xFF, driving[drive_sel][0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CMD_DRIVE_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 			0xFF, driving[drive_sel][1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DAT_DRIVE_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 			0xFF, driving[drive_sel][2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) static void rts5227_fetch_vendor_settings(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	struct pci_dev *pdev = pcr->pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	pci_read_config_dword(pdev, PCR_SETTING_REG1, &reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	if (!rtsx_vendor_setting_valid(reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	pcr->aspm_en = rtsx_reg_to_aspm(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	pcr->sd30_drive_sel_1v8 = rtsx_reg_to_sd30_drive_sel_1v8(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	pcr->card_drive_sel &= 0x3F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	pci_read_config_dword(pdev, PCR_SETTING_REG2, &reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	if (rtsx_check_mmc_support(reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 		pcr->extra_caps |= EXTRA_CAPS_NO_MMC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	if (rtsx_reg_check_reverse_socket(reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 		pcr->flags |= PCR_REVERSE_SOCKET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) static void rts5227_init_from_cfg(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	struct pci_dev *pdev = pcr->pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	int l1ss;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	u32 lval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	struct rtsx_cr_option *option = &pcr->option;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	l1ss = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	if (!l1ss)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	pci_read_config_dword(pdev, l1ss + PCI_L1SS_CTL1, &lval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	if (CHK_PCI_PID(pcr, 0x522A)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		if (0 == (lval & 0x0F))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 			rtsx_pci_enable_oobs_polling(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 			rtsx_pci_disable_oobs_polling(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	if (lval & PCI_L1SS_CTL1_ASPM_L1_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		rtsx_set_dev_flag(pcr, ASPM_L1_1_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		rtsx_clear_dev_flag(pcr, ASPM_L1_1_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	if (lval & PCI_L1SS_CTL1_ASPM_L1_2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		rtsx_set_dev_flag(pcr, ASPM_L1_2_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		rtsx_clear_dev_flag(pcr, ASPM_L1_2_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	if (lval & PCI_L1SS_CTL1_PCIPM_L1_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 		rtsx_set_dev_flag(pcr, PM_L1_1_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		rtsx_clear_dev_flag(pcr, PM_L1_1_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	if (lval & PCI_L1SS_CTL1_PCIPM_L1_2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		rtsx_set_dev_flag(pcr, PM_L1_2_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		rtsx_clear_dev_flag(pcr, PM_L1_2_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	if (option->ltr_en) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		pcie_capability_read_word(pcr->pci, PCI_EXP_DEVCTL2, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		if (val & PCI_EXP_DEVCTL2_LTR_EN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 			option->ltr_enabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 			option->ltr_active = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 			rtsx_set_ltr_latency(pcr, option->ltr_active_latency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 			option->ltr_enabled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 				| PM_L1_1_EN | PM_L1_2_EN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		option->force_clkreq_0 = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		option->force_clkreq_0 = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static int rts5227_extra_init_hw(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	u16 cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	struct rtsx_cr_option *option = &pcr->option;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	rts5227_init_from_cfg(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	rtsx_pci_init_cmd(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	/* Configure GPIO as output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, GPIO_CTL, 0x02, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	/* Reset ASPM state to default value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, ASPM_FORCE_CTL, 0x3F, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	/* Switch LDO3318 source from DV33 to card_3v3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	/* LED shine disabled, set initial shine cycle period */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OLT_LED_CTL, 0x0F, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	/* Configure LTR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	pcie_capability_read_word(pcr->pci, PCI_EXP_DEVCTL2, &cap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	if (cap & PCI_EXP_DEVCTL2_LTR_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LTR_CTL, 0xFF, 0xA3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	/* Configure OBFF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OBFF_CFG, 0x03, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	/* Configure driving */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	rts5227_fill_driving(pcr, OUTPUT_3V3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	/* Configure force_clock_req */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	if (pcr->flags & PCR_REVERSE_SOCKET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0x30, 0x30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0x30, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	if (option->force_clkreq_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 				FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 				FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, pcr->reg_pm_ctrl3, 0x10, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	return rtsx_pci_send_cmd(pcr, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static int rts5227_optimize_phy(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	err = rtsx_pci_write_register(pcr, PM_CTRL3, D3_DELINK_MODE_EN, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	/* Optimize RX sensitivity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	return rtsx_pci_write_phy_register(pcr, 0x00, 0xBA42);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static int rts5227_turn_on_led(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static int rts5227_turn_off_led(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static int rts5227_enable_auto_blink(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static int rts5227_disable_auto_blink(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static int rts5227_card_power_on(struct rtsx_pcr *pcr, int card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	if (pcr->option.ocp_en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		rtsx_pci_enable_ocp(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	rtsx_pci_init_cmd(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 			SD_POWER_MASK, SD_PARTIAL_POWER_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 			LDO3318_PWR_MASK, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	err = rtsx_pci_send_cmd(pcr, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	/* To avoid too large in-rush current */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	rtsx_pci_init_cmd(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 			SD_POWER_MASK, SD_POWER_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 			LDO3318_PWR_MASK, 0x06);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_OE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 			SD_OUTPUT_EN, SD_OUTPUT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_OE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 			MS_OUTPUT_EN, MS_OUTPUT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	return rtsx_pci_send_cmd(pcr, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static int rts5227_card_power_off(struct rtsx_pcr *pcr, int card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	if (pcr->option.ocp_en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		rtsx_pci_disable_ocp(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	rtsx_pci_write_register(pcr, CARD_PWR_CTL, SD_POWER_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 			PMOS_STRG_MASK, SD_POWER_OFF | PMOS_STRG_400mA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	rtsx_pci_write_register(pcr, PWR_GATE_CTRL, LDO3318_PWR_MASK, 0X00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static int rts5227_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	if (voltage == OUTPUT_3V3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		err = rtsx_pci_write_phy_register(pcr, 0x08, 0x4FC0 | 0x24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 		if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 			return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	} else if (voltage == OUTPUT_1V8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		err = rtsx_pci_write_phy_register(pcr, 0x11, 0x3C02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 			return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		err = rtsx_pci_write_phy_register(pcr, 0x08, 0x4C80 | 0x24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 		if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 			return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	/* set pad drive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	rtsx_pci_init_cmd(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	rts5227_fill_driving(pcr, voltage);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	return rtsx_pci_send_cmd(pcr, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static const struct pcr_ops rts5227_pcr_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	.fetch_vendor_settings = rts5227_fetch_vendor_settings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	.extra_init_hw = rts5227_extra_init_hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	.optimize_phy = rts5227_optimize_phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	.turn_on_led = rts5227_turn_on_led,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	.turn_off_led = rts5227_turn_off_led,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	.enable_auto_blink = rts5227_enable_auto_blink,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	.disable_auto_blink = rts5227_disable_auto_blink,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	.card_power_on = rts5227_card_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	.card_power_off = rts5227_card_power_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	.switch_output_voltage = rts5227_switch_output_voltage,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	.cd_deglitch = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	.conv_clk_and_div_n = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) /* SD Pull Control Enable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)  *     SD_DAT[3:0] ==> pull up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)  *     SD_CD       ==> pull up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)  *     SD_WP       ==> pull up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)  *     SD_CMD      ==> pull up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)  *     SD_CLK      ==> pull down
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) static const u32 rts5227_sd_pull_ctl_enable_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /* SD Pull Control Disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)  *     SD_DAT[3:0] ==> pull down
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)  *     SD_CD       ==> pull up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)  *     SD_WP       ==> pull down
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)  *     SD_CMD      ==> pull down
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)  *     SD_CLK      ==> pull down
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) static const u32 rts5227_sd_pull_ctl_disable_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) /* MS Pull Control Enable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)  *     MS CD       ==> pull up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)  *     others      ==> pull down
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static const u32 rts5227_ms_pull_ctl_enable_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) /* MS Pull Control Disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)  *     MS CD       ==> pull up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)  *     others      ==> pull down
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static const u32 rts5227_ms_pull_ctl_disable_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) void rts5227_init_params(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	pcr->num_slots = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	pcr->ops = &rts5227_pcr_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	pcr->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	pcr->aspm_en = ASPM_L1_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 27, 15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	pcr->rx_initial_phase = SET_CLOCK_PHASE(30, 7, 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	pcr->ic_version = rts5227_get_ic_version(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	pcr->sd_pull_ctl_enable_tbl = rts5227_sd_pull_ctl_enable_tbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	pcr->sd_pull_ctl_disable_tbl = rts5227_sd_pull_ctl_disable_tbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	pcr->ms_pull_ctl_enable_tbl = rts5227_ms_pull_ctl_enable_tbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	pcr->ms_pull_ctl_disable_tbl = rts5227_ms_pull_ctl_disable_tbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	pcr->reg_pm_ctrl3 = PM_CTRL3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static int rts522a_optimize_phy(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	err = rtsx_pci_write_register(pcr, RTS522A_PM_CTRL3, D3_DELINK_MODE_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 		0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	if (is_version(pcr, 0x522A, IC_VER_A)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 		err = rtsx_pci_write_phy_register(pcr, PHY_RCR2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 			PHY_RCR2_INIT_27S);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 		if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 			return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 		rtsx_pci_write_phy_register(pcr, PHY_RCR1, PHY_RCR1_INIT_27S);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 		rtsx_pci_write_phy_register(pcr, PHY_FLD0, PHY_FLD0_INIT_27S);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 		rtsx_pci_write_phy_register(pcr, PHY_FLD3, PHY_FLD3_INIT_27S);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 		rtsx_pci_write_phy_register(pcr, PHY_FLD4, PHY_FLD4_INIT_27S);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) static int rts522a_extra_init_hw(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	rts5227_extra_init_hw(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	/* Power down OCP for power consumption */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 	if (!pcr->card_exist)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 		rtsx_pci_write_register(pcr, FPDCTL, OC_POWER_DOWN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 				OC_POWER_DOWN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	rtsx_pci_write_register(pcr, FUNC_FORCE_CTL, FUNC_FORCE_UPME_XMT_DBG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 		FUNC_FORCE_UPME_XMT_DBG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	rtsx_pci_write_register(pcr, PCLK_CTL, 0x04, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	rtsx_pci_write_register(pcr, PM_EVENT_DEBUG, PME_DEBUG_0, PME_DEBUG_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	rtsx_pci_write_register(pcr, PM_CLK_FORCE_CTL, 0xFF, 0x11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) static int rts522a_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 	if (voltage == OUTPUT_3V3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 		err = rtsx_pci_write_phy_register(pcr, 0x08, 0x57E4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 		if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 			return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 	} else if (voltage == OUTPUT_1V8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 		err = rtsx_pci_write_phy_register(pcr, 0x11, 0x3C02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 		if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 			return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 		err = rtsx_pci_write_phy_register(pcr, 0x08, 0x54A4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 		if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 			return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 	/* set pad drive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 	rtsx_pci_init_cmd(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 	rts5227_fill_driving(pcr, voltage);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 	return rtsx_pci_send_cmd(pcr, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) static void rts522a_set_l1off_cfg_sub_d0(struct rtsx_pcr *pcr, int active)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 	struct rtsx_cr_option *option = &pcr->option;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 	int aspm_L1_1, aspm_L1_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 	u8 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 	aspm_L1_1 = rtsx_check_dev_flag(pcr, ASPM_L1_1_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 	aspm_L1_2 = rtsx_check_dev_flag(pcr, ASPM_L1_2_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 	if (active) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 		/* run, latency: 60us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 		if (aspm_L1_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 			val = option->ltr_l1off_snooze_sspwrgate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 		/* l1off, latency: 300us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 		if (aspm_L1_2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 			val = option->ltr_l1off_sspwrgate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 	rtsx_set_l1off_sub(pcr, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) /* rts522a operations mainly derived from rts5227, except phy/hw init setting.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) static const struct pcr_ops rts522a_pcr_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 	.fetch_vendor_settings = rts5227_fetch_vendor_settings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 	.extra_init_hw = rts522a_extra_init_hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 	.optimize_phy = rts522a_optimize_phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 	.turn_on_led = rts5227_turn_on_led,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 	.turn_off_led = rts5227_turn_off_led,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 	.enable_auto_blink = rts5227_enable_auto_blink,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 	.disable_auto_blink = rts5227_disable_auto_blink,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 	.card_power_on = rts5227_card_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 	.card_power_off = rts5227_card_power_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 	.switch_output_voltage = rts522a_switch_output_voltage,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 	.cd_deglitch = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 	.conv_clk_and_div_n = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 	.set_l1off_cfg_sub_d0 = rts522a_set_l1off_cfg_sub_d0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) void rts522a_init_params(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 	struct rtsx_cr_option *option = &pcr->option;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 	rts5227_init_params(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 	pcr->ops = &rts522a_pcr_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 	pcr->tx_initial_phase = SET_CLOCK_PHASE(20, 20, 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 	pcr->reg_pm_ctrl3 = RTS522A_PM_CTRL3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) 	option->dev_flags = LTR_L1SS_PWR_GATE_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) 	option->ltr_en = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 	/* init latency of active, idle, L1OFF to 60us, 300us, 3ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 	option->ltr_active_latency = LTR_ACTIVE_LATENCY_DEF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) 	option->ltr_idle_latency = LTR_IDLE_LATENCY_DEF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) 	option->ltr_l1off_latency = LTR_L1OFF_LATENCY_DEF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) 	option->l1_snooze_delay = L1_SNOOZE_DELAY_DEF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) 	option->ltr_l1off_sspwrgate = 0x7F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) 	option->ltr_l1off_snooze_sspwrgate = 0x78;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) 	pcr->option.ocp_en = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) 	if (pcr->option.ocp_en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) 		pcr->hw_param.interrupt_en |= SD_OC_INT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) 	pcr->hw_param.ocp_glitch = SD_OCP_GLITCH_10M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 	pcr->option.sd_800mA_ocp_thd = RTS522A_OCP_THD_800;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) }