Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /* Driver for Realtek PCI-Express card reader
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Author:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *   Wei WANG <wei_wang@realsil.com.cn>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/rtsx_pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include "rtsx_pcr.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) static u8 rts5209_get_ic_version(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 	u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 	val = rtsx_pci_readb(pcr, 0x1C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 	return val & 0x0F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) static void rts5209_fetch_vendor_settings(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	struct pci_dev *pdev = pcr->pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	pci_read_config_dword(pdev, PCR_SETTING_REG1, &reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	if (rts5209_vendor_setting1_valid(reg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 		if (rts5209_reg_check_ms_pmos(reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 			pcr->flags |= PCR_MS_PMOS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 		pcr->aspm_en = rts5209_reg_to_aspm(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	pci_read_config_dword(pdev, PCR_SETTING_REG2, &reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	if (rts5209_vendor_setting2_valid(reg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 		pcr->sd30_drive_sel_1v8 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 			rts5209_reg_to_sd30_drive_sel_1v8(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 		pcr->sd30_drive_sel_3v3 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 			rts5209_reg_to_sd30_drive_sel_3v3(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 		pcr->card_drive_sel = rts5209_reg_to_card_drive_sel(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) static void rts5209_force_power_down(struct rtsx_pcr *pcr, u8 pm_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	rtsx_pci_write_register(pcr, FPDCTL, 0x07, 0x07);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) static int rts5209_extra_init_hw(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	rtsx_pci_init_cmd(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	/* Turn off LED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_GPIO, 0xFF, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	/* Reset ASPM state to default value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, ASPM_FORCE_CTL, 0x3F, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	/* Force CLKREQ# PIN to drive 0 to request clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0x08, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	/* Configure GPIO as output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_GPIO_DIR, 0xFF, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	/* Configure driving */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DRIVE_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 			0xFF, pcr->sd30_drive_sel_3v3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	return rtsx_pci_send_cmd(pcr, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) static int rts5209_optimize_phy(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	return rtsx_pci_write_phy_register(pcr, 0x00, 0xB966);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) static int rts5209_turn_on_led(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	return rtsx_pci_write_register(pcr, CARD_GPIO, 0x01, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) static int rts5209_turn_off_led(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	return rtsx_pci_write_register(pcr, CARD_GPIO, 0x01, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) static int rts5209_enable_auto_blink(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	return rtsx_pci_write_register(pcr, CARD_AUTO_BLINK, 0xFF, 0x0D);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) static int rts5209_disable_auto_blink(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	return rtsx_pci_write_register(pcr, CARD_AUTO_BLINK, 0x08, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) static int rts5209_card_power_on(struct rtsx_pcr *pcr, int card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	u8 pwr_mask, partial_pwr_on, pwr_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	pwr_mask = SD_POWER_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	partial_pwr_on = SD_PARTIAL_POWER_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	pwr_on = SD_POWER_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	if ((pcr->flags & PCR_MS_PMOS) && (card == RTSX_MS_CARD)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		pwr_mask = MS_POWER_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		partial_pwr_on = MS_PARTIAL_POWER_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		pwr_on = MS_POWER_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	rtsx_pci_init_cmd(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 			pwr_mask, partial_pwr_on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 			LDO3318_PWR_MASK, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	err = rtsx_pci_send_cmd(pcr, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	/* To avoid too large in-rush current */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	udelay(150);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	rtsx_pci_init_cmd(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL, pwr_mask, pwr_on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 			LDO3318_PWR_MASK, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	return rtsx_pci_send_cmd(pcr, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static int rts5209_card_power_off(struct rtsx_pcr *pcr, int card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	u8 pwr_mask, pwr_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	pwr_mask = SD_POWER_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	pwr_off = SD_POWER_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	if ((pcr->flags & PCR_MS_PMOS) && (card == RTSX_MS_CARD)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		pwr_mask = MS_POWER_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		pwr_off = MS_POWER_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	rtsx_pci_init_cmd(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 			pwr_mask | PMOS_STRG_MASK, pwr_off | PMOS_STRG_400mA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 			LDO3318_PWR_MASK, 0x06);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	return rtsx_pci_send_cmd(pcr, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static int rts5209_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	if (voltage == OUTPUT_3V3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		err = rtsx_pci_write_register(pcr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 				SD30_DRIVE_SEL, 0x07, pcr->sd30_drive_sel_3v3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 			return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		err = rtsx_pci_write_phy_register(pcr, 0x08, 0x4FC0 | 0x24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 			return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	} else if (voltage == OUTPUT_1V8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		err = rtsx_pci_write_register(pcr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 				SD30_DRIVE_SEL, 0x07, pcr->sd30_drive_sel_1v8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 			return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		err = rtsx_pci_write_phy_register(pcr, 0x08, 0x4C40 | 0x24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 			return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static const struct pcr_ops rts5209_pcr_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	.fetch_vendor_settings = rts5209_fetch_vendor_settings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	.extra_init_hw = rts5209_extra_init_hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	.optimize_phy = rts5209_optimize_phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	.turn_on_led = rts5209_turn_on_led,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	.turn_off_led = rts5209_turn_off_led,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	.enable_auto_blink = rts5209_enable_auto_blink,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	.disable_auto_blink = rts5209_disable_auto_blink,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	.card_power_on = rts5209_card_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	.card_power_off = rts5209_card_power_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	.switch_output_voltage = rts5209_switch_output_voltage,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	.cd_deglitch = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	.conv_clk_and_div_n = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	.force_power_down = rts5209_force_power_down,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /* SD Pull Control Enable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)  *     SD_DAT[3:0] ==> pull up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)  *     SD_CD       ==> pull up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)  *     SD_WP       ==> pull up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)  *     SD_CMD      ==> pull up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)  *     SD_CLK      ==> pull down
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static const u32 rts5209_sd_pull_ctl_enable_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	RTSX_REG_PAIR(CARD_PULL_CTL1, 0xAA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /* SD Pull Control Disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)  *     SD_DAT[3:0] ==> pull down
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)  *     SD_CD       ==> pull up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)  *     SD_WP       ==> pull down
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)  *     SD_CMD      ==> pull down
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)  *     SD_CLK      ==> pull down
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static const u32 rts5209_sd_pull_ctl_disable_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	RTSX_REG_PAIR(CARD_PULL_CTL1, 0x55),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /* MS Pull Control Enable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)  *     MS CD       ==> pull up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)  *     others      ==> pull down
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static const u32 rts5209_ms_pull_ctl_enable_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /* MS Pull Control Disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)  *     MS CD       ==> pull up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)  *     others      ==> pull down
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static const u32 rts5209_ms_pull_ctl_disable_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) void rts5209_init_params(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	pcr->extra_caps = EXTRA_CAPS_SD_SDR50 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		EXTRA_CAPS_SD_SDR104 | EXTRA_CAPS_MMC_8BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	pcr->num_slots = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	pcr->ops = &rts5209_pcr_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	pcr->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	pcr->card_drive_sel = RTS5209_CARD_DRIVE_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	pcr->sd30_drive_sel_1v8 = DRIVER_TYPE_B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	pcr->sd30_drive_sel_3v3 = DRIVER_TYPE_D;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	pcr->aspm_en = ASPM_L1_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 27, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	pcr->ic_version = rts5209_get_ic_version(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	pcr->sd_pull_ctl_enable_tbl = rts5209_sd_pull_ctl_enable_tbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	pcr->sd_pull_ctl_disable_tbl = rts5209_sd_pull_ctl_disable_tbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	pcr->ms_pull_ctl_enable_tbl = rts5209_ms_pull_ctl_enable_tbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	pcr->ms_pull_ctl_disable_tbl = rts5209_ms_pull_ctl_disable_tbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }