^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* Driver for Realtek PCI-Express card reader
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Wei WANG <wei_wang@realsil.com.cn>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Roger Tseng <rogerable@realtek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/rtsx_pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "rtsx_pcr.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) static u8 rtl8411_get_ic_version(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) rtsx_pci_read_register(pcr, SYS_VER, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) return val & 0x0F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) static int rtl8411b_is_qfn48(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) u8 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) rtsx_pci_read_register(pcr, RTL8411B_PACKAGE_MODE, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) if (val & 0x2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static void rtl8411_fetch_vendor_settings(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct pci_dev *pdev = pcr->pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) u32 reg1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) u8 reg3 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) pci_read_config_dword(pdev, PCR_SETTING_REG1, ®1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) if (!rtsx_vendor_setting_valid(reg1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) pcr->aspm_en = rtsx_reg_to_aspm(reg1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) pcr->sd30_drive_sel_1v8 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) map_sd_drive(rtsx_reg_to_sd30_drive_sel_1v8(reg1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) pcr->card_drive_sel &= 0x3F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) pci_read_config_byte(pdev, PCR_SETTING_REG3, ®3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG3, reg3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) pcr->sd30_drive_sel_3v3 = rtl8411_reg_to_sd30_drive_sel_3v3(reg3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static void rtl8411b_fetch_vendor_settings(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct pci_dev *pdev = pcr->pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) u32 reg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) pci_read_config_dword(pdev, PCR_SETTING_REG1, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) if (!rtsx_vendor_setting_valid(reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) pcr->aspm_en = rtsx_reg_to_aspm(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) pcr->sd30_drive_sel_1v8 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) map_sd_drive(rtsx_reg_to_sd30_drive_sel_1v8(reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) pcr->sd30_drive_sel_3v3 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) map_sd_drive(rtl8411b_reg_to_sd30_drive_sel_3v3(reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static void rtl8411_force_power_down(struct rtsx_pcr *pcr, u8 pm_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) rtsx_pci_write_register(pcr, FPDCTL, 0x07, 0x07);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static int rtl8411_extra_init_hw(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) rtsx_pci_init_cmd(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DRIVE_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) 0xFF, pcr->sd30_drive_sel_3v3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CD_PAD_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) CD_DISABLE_MASK | CD_AUTO_DISABLE, CD_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) return rtsx_pci_send_cmd(pcr, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static int rtl8411b_extra_init_hw(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) rtsx_pci_init_cmd(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) if (rtl8411b_is_qfn48(pcr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) CARD_PULL_CTL3, 0xFF, 0xF5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DRIVE_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 0xFF, pcr->sd30_drive_sel_3v3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CD_PAD_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) CD_DISABLE_MASK | CD_AUTO_DISABLE, CD_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, FUNC_FORCE_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 0x06, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) return rtsx_pci_send_cmd(pcr, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static int rtl8411_turn_on_led(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) return rtsx_pci_write_register(pcr, CARD_GPIO, 0x01, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static int rtl8411_turn_off_led(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) return rtsx_pci_write_register(pcr, CARD_GPIO, 0x01, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static int rtl8411_enable_auto_blink(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) return rtsx_pci_write_register(pcr, CARD_AUTO_BLINK, 0xFF, 0x0D);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static int rtl8411_disable_auto_blink(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) return rtsx_pci_write_register(pcr, CARD_AUTO_BLINK, 0x08, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static int rtl8411_card_power_on(struct rtsx_pcr *pcr, int card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) rtsx_pci_init_cmd(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) BPP_POWER_MASK, BPP_POWER_5_PERCENT_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) BPP_LDO_POWB, BPP_LDO_SUSPEND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) err = rtsx_pci_send_cmd(pcr, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* To avoid too large in-rush current */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) udelay(150);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) err = rtsx_pci_write_register(pcr, CARD_PWR_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) BPP_POWER_MASK, BPP_POWER_10_PERCENT_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) udelay(150);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) err = rtsx_pci_write_register(pcr, CARD_PWR_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) BPP_POWER_MASK, BPP_POWER_15_PERCENT_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) udelay(150);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) err = rtsx_pci_write_register(pcr, CARD_PWR_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) BPP_POWER_MASK, BPP_POWER_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) return rtsx_pci_write_register(pcr, LDO_CTL, BPP_LDO_POWB, BPP_LDO_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static int rtl8411_card_power_off(struct rtsx_pcr *pcr, int card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) err = rtsx_pci_write_register(pcr, CARD_PWR_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) BPP_POWER_MASK, BPP_POWER_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) return rtsx_pci_write_register(pcr, LDO_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) BPP_LDO_POWB, BPP_LDO_SUSPEND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static int rtl8411_do_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) int bpp_tuned18_shift, int bpp_asic_1v8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) u8 mask, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) mask = (BPP_REG_TUNED18 << bpp_tuned18_shift) | BPP_PAD_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) if (voltage == OUTPUT_3V3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) err = rtsx_pci_write_register(pcr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) SD30_DRIVE_SEL, 0x07, pcr->sd30_drive_sel_3v3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) val = (BPP_ASIC_3V3 << bpp_tuned18_shift) | BPP_PAD_3V3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) } else if (voltage == OUTPUT_1V8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) err = rtsx_pci_write_register(pcr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) SD30_DRIVE_SEL, 0x07, pcr->sd30_drive_sel_1v8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) val = (bpp_asic_1v8 << bpp_tuned18_shift) | BPP_PAD_1V8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) return rtsx_pci_write_register(pcr, LDO_CTL, mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static int rtl8411_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) return rtl8411_do_switch_output_voltage(pcr, voltage,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) BPP_TUNED18_SHIFT_8411, BPP_ASIC_1V8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static int rtl8402_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) return rtl8411_do_switch_output_voltage(pcr, voltage,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) BPP_TUNED18_SHIFT_8402, BPP_ASIC_2V0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static unsigned int rtl8411_cd_deglitch(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) unsigned int card_exist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) card_exist = rtsx_pci_readl(pcr, RTSX_BIPR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) card_exist &= CARD_EXIST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if (!card_exist) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /* Enable card CD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) rtsx_pci_write_register(pcr, CD_PAD_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) CD_DISABLE_MASK, CD_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /* Enable card interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) rtsx_pci_write_register(pcr, EFUSE_CONTENT, 0xe0, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (hweight32(card_exist) > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) rtsx_pci_write_register(pcr, CARD_PWR_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) BPP_POWER_MASK, BPP_POWER_5_PERCENT_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) msleep(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) card_exist = rtsx_pci_readl(pcr, RTSX_BIPR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) if (card_exist & MS_EXIST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) card_exist = MS_EXIST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) else if (card_exist & SD_EXIST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) card_exist = SD_EXIST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) card_exist = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) rtsx_pci_write_register(pcr, CARD_PWR_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) BPP_POWER_MASK, BPP_POWER_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) pcr_dbg(pcr, "After CD deglitch, card_exist = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) card_exist);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) if (card_exist & MS_EXIST) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /* Disable SD interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) rtsx_pci_write_register(pcr, EFUSE_CONTENT, 0xe0, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) rtsx_pci_write_register(pcr, CD_PAD_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) CD_DISABLE_MASK, MS_CD_EN_ONLY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) } else if (card_exist & SD_EXIST) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /* Disable MS interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) rtsx_pci_write_register(pcr, EFUSE_CONTENT, 0xe0, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) rtsx_pci_write_register(pcr, CD_PAD_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) CD_DISABLE_MASK, SD_CD_EN_ONLY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) return card_exist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static int rtl8411_conv_clk_and_div_n(int input, int dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) int output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) if (dir == CLK_TO_DIV_N)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) output = input * 4 / 5 - 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) output = (input + 2) * 5 / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) return output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static const struct pcr_ops rtl8411_pcr_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .fetch_vendor_settings = rtl8411_fetch_vendor_settings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .extra_init_hw = rtl8411_extra_init_hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .optimize_phy = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .turn_on_led = rtl8411_turn_on_led,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .turn_off_led = rtl8411_turn_off_led,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .enable_auto_blink = rtl8411_enable_auto_blink,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .disable_auto_blink = rtl8411_disable_auto_blink,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .card_power_on = rtl8411_card_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .card_power_off = rtl8411_card_power_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .switch_output_voltage = rtl8411_switch_output_voltage,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .cd_deglitch = rtl8411_cd_deglitch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .conv_clk_and_div_n = rtl8411_conv_clk_and_div_n,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .force_power_down = rtl8411_force_power_down,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static const struct pcr_ops rtl8402_pcr_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .fetch_vendor_settings = rtl8411_fetch_vendor_settings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .extra_init_hw = rtl8411_extra_init_hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .optimize_phy = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .turn_on_led = rtl8411_turn_on_led,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .turn_off_led = rtl8411_turn_off_led,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .enable_auto_blink = rtl8411_enable_auto_blink,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .disable_auto_blink = rtl8411_disable_auto_blink,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .card_power_on = rtl8411_card_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .card_power_off = rtl8411_card_power_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .switch_output_voltage = rtl8402_switch_output_voltage,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .cd_deglitch = rtl8411_cd_deglitch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) .conv_clk_and_div_n = rtl8411_conv_clk_and_div_n,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .force_power_down = rtl8411_force_power_down,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static const struct pcr_ops rtl8411b_pcr_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) .fetch_vendor_settings = rtl8411b_fetch_vendor_settings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .extra_init_hw = rtl8411b_extra_init_hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) .optimize_phy = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .turn_on_led = rtl8411_turn_on_led,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .turn_off_led = rtl8411_turn_off_led,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .enable_auto_blink = rtl8411_enable_auto_blink,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .disable_auto_blink = rtl8411_disable_auto_blink,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .card_power_on = rtl8411_card_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .card_power_off = rtl8411_card_power_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .switch_output_voltage = rtl8411_switch_output_voltage,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .cd_deglitch = rtl8411_cd_deglitch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .conv_clk_and_div_n = rtl8411_conv_clk_and_div_n,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .force_power_down = rtl8411_force_power_down,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) /* SD Pull Control Enable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) * SD_DAT[3:0] ==> pull up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) * SD_CD ==> pull up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) * SD_WP ==> pull up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) * SD_CMD ==> pull up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) * SD_CLK ==> pull down
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) static const u32 rtl8411_sd_pull_ctl_enable_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) RTSX_REG_PAIR(CARD_PULL_CTL1, 0xAA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) RTSX_REG_PAIR(CARD_PULL_CTL3, 0xA9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) RTSX_REG_PAIR(CARD_PULL_CTL4, 0x09),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) RTSX_REG_PAIR(CARD_PULL_CTL5, 0x09),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) RTSX_REG_PAIR(CARD_PULL_CTL6, 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) /* SD Pull Control Disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) * SD_DAT[3:0] ==> pull down
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) * SD_CD ==> pull up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) * SD_WP ==> pull down
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) * SD_CMD ==> pull down
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) * SD_CLK ==> pull down
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static const u32 rtl8411_sd_pull_ctl_disable_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) RTSX_REG_PAIR(CARD_PULL_CTL1, 0x65),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) RTSX_REG_PAIR(CARD_PULL_CTL3, 0x95),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) RTSX_REG_PAIR(CARD_PULL_CTL4, 0x09),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) RTSX_REG_PAIR(CARD_PULL_CTL5, 0x05),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) RTSX_REG_PAIR(CARD_PULL_CTL6, 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) /* MS Pull Control Enable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) * MS CD ==> pull up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) * others ==> pull down
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) static const u32 rtl8411_ms_pull_ctl_enable_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) RTSX_REG_PAIR(CARD_PULL_CTL1, 0x65),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) RTSX_REG_PAIR(CARD_PULL_CTL3, 0x95),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) RTSX_REG_PAIR(CARD_PULL_CTL4, 0x05),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) RTSX_REG_PAIR(CARD_PULL_CTL5, 0x05),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) RTSX_REG_PAIR(CARD_PULL_CTL6, 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) /* MS Pull Control Disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) * MS CD ==> pull up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) * others ==> pull down
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static const u32 rtl8411_ms_pull_ctl_disable_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) RTSX_REG_PAIR(CARD_PULL_CTL1, 0x65),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) RTSX_REG_PAIR(CARD_PULL_CTL3, 0x95),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) RTSX_REG_PAIR(CARD_PULL_CTL4, 0x09),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) RTSX_REG_PAIR(CARD_PULL_CTL5, 0x05),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) RTSX_REG_PAIR(CARD_PULL_CTL6, 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) static const u32 rtl8411b_qfn64_sd_pull_ctl_enable_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) RTSX_REG_PAIR(CARD_PULL_CTL1, 0xAA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) RTSX_REG_PAIR(CARD_PULL_CTL3, 0x09 | 0xD0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) RTSX_REG_PAIR(CARD_PULL_CTL4, 0x09 | 0x50),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) RTSX_REG_PAIR(CARD_PULL_CTL5, 0x05 | 0x50),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) RTSX_REG_PAIR(CARD_PULL_CTL6, 0x04 | 0x11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) static const u32 rtl8411b_qfn48_sd_pull_ctl_enable_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) RTSX_REG_PAIR(CARD_PULL_CTL3, 0x69 | 0x90),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) RTSX_REG_PAIR(CARD_PULL_CTL6, 0x08 | 0x11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) static const u32 rtl8411b_qfn64_sd_pull_ctl_disable_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) RTSX_REG_PAIR(CARD_PULL_CTL1, 0x65),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) RTSX_REG_PAIR(CARD_PULL_CTL3, 0x05 | 0xD0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) RTSX_REG_PAIR(CARD_PULL_CTL4, 0x09 | 0x50),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) RTSX_REG_PAIR(CARD_PULL_CTL5, 0x05 | 0x50),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) RTSX_REG_PAIR(CARD_PULL_CTL6, 0x04 | 0x11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) static const u32 rtl8411b_qfn48_sd_pull_ctl_disable_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) RTSX_REG_PAIR(CARD_PULL_CTL3, 0x65 | 0x90),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) RTSX_REG_PAIR(CARD_PULL_CTL6, 0x04 | 0x11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) static const u32 rtl8411b_qfn64_ms_pull_ctl_enable_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) RTSX_REG_PAIR(CARD_PULL_CTL1, 0x65),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) RTSX_REG_PAIR(CARD_PULL_CTL3, 0x05 | 0xD0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) RTSX_REG_PAIR(CARD_PULL_CTL4, 0x05 | 0x50),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) RTSX_REG_PAIR(CARD_PULL_CTL5, 0x05 | 0x50),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) RTSX_REG_PAIR(CARD_PULL_CTL6, 0x04 | 0x11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) static const u32 rtl8411b_qfn48_ms_pull_ctl_enable_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) RTSX_REG_PAIR(CARD_PULL_CTL3, 0x65 | 0x90),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) RTSX_REG_PAIR(CARD_PULL_CTL6, 0x04 | 0x11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) static const u32 rtl8411b_qfn64_ms_pull_ctl_disable_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) RTSX_REG_PAIR(CARD_PULL_CTL1, 0x65),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) RTSX_REG_PAIR(CARD_PULL_CTL3, 0x05 | 0xD0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) RTSX_REG_PAIR(CARD_PULL_CTL4, 0x09 | 0x50),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) RTSX_REG_PAIR(CARD_PULL_CTL5, 0x05 | 0x50),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) RTSX_REG_PAIR(CARD_PULL_CTL6, 0x04 | 0x11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) static const u32 rtl8411b_qfn48_ms_pull_ctl_disable_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) RTSX_REG_PAIR(CARD_PULL_CTL3, 0x65 | 0x90),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) RTSX_REG_PAIR(CARD_PULL_CTL6, 0x04 | 0x11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) static void rtl8411_init_common_params(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) pcr->num_slots = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) pcr->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) pcr->card_drive_sel = RTL8411_CARD_DRIVE_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) pcr->sd30_drive_sel_1v8 = DRIVER_TYPE_B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) pcr->sd30_drive_sel_3v3 = DRIVER_TYPE_D;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) pcr->aspm_en = ASPM_L1_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) pcr->tx_initial_phase = SET_CLOCK_PHASE(23, 7, 14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) pcr->rx_initial_phase = SET_CLOCK_PHASE(4, 3, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) pcr->ic_version = rtl8411_get_ic_version(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) void rtl8411_init_params(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) rtl8411_init_common_params(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) pcr->ops = &rtl8411_pcr_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) set_pull_ctrl_tables(pcr, rtl8411);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) void rtl8411b_init_params(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) rtl8411_init_common_params(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) pcr->ops = &rtl8411b_pcr_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) if (rtl8411b_is_qfn48(pcr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) set_pull_ctrl_tables(pcr, rtl8411b_qfn48);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) set_pull_ctrl_tables(pcr, rtl8411b_qfn64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) void rtl8402_init_params(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) rtl8411_init_common_params(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) pcr->ops = &rtl8402_pcr_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) set_pull_ctrl_tables(pcr, rtl8411);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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