Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * wm8994-irq.c  --  Interrupt controller support for Wolfson WM8994
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright 2010 Wolfson Microelectronics PLC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/mfd/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/mfd/wm8994/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/mfd/wm8994/pdata.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/mfd/wm8994/registers.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) static const struct regmap_irq wm8994_irqs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	[WM8994_IRQ_TEMP_SHUT] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 		.reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 		.mask = WM8994_TEMP_SHUT_EINT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	[WM8994_IRQ_MIC1_DET] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 		.reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 		.mask = WM8994_MIC1_DET_EINT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	[WM8994_IRQ_MIC1_SHRT] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 		.reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 		.mask = WM8994_MIC1_SHRT_EINT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	[WM8994_IRQ_MIC2_DET] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 		.reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 		.mask = WM8994_MIC2_DET_EINT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	[WM8994_IRQ_MIC2_SHRT] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 		.reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 		.mask = WM8994_MIC2_SHRT_EINT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	[WM8994_IRQ_FLL1_LOCK] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 		.reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 		.mask = WM8994_FLL1_LOCK_EINT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	[WM8994_IRQ_FLL2_LOCK] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 		.reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 		.mask = WM8994_FLL2_LOCK_EINT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	[WM8994_IRQ_SRC1_LOCK] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 		.reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 		.mask = WM8994_SRC1_LOCK_EINT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	[WM8994_IRQ_SRC2_LOCK] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 		.reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 		.mask = WM8994_SRC2_LOCK_EINT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	[WM8994_IRQ_AIF1DRC1_SIG_DET] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 		.reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 		.mask = WM8994_AIF1DRC1_SIG_DET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	[WM8994_IRQ_AIF1DRC2_SIG_DET] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 		.reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 		.mask = WM8994_AIF1DRC2_SIG_DET_EINT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	[WM8994_IRQ_AIF2DRC_SIG_DET] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 		.reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 		.mask = WM8994_AIF2DRC_SIG_DET_EINT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	[WM8994_IRQ_FIFOS_ERR] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 		.reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		.mask = WM8994_FIFOS_ERR_EINT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	[WM8994_IRQ_WSEQ_DONE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 		.reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		.mask = WM8994_WSEQ_DONE_EINT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	[WM8994_IRQ_DCS_DONE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		.reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		.mask = WM8994_DCS_DONE_EINT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	[WM8994_IRQ_TEMP_WARN] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		.reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		.mask = WM8994_TEMP_WARN_EINT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	[WM8994_IRQ_GPIO(1)] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		.mask = WM8994_GP1_EINT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	[WM8994_IRQ_GPIO(2)] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		.mask = WM8994_GP2_EINT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	[WM8994_IRQ_GPIO(3)] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		.mask = WM8994_GP3_EINT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	[WM8994_IRQ_GPIO(4)] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		.mask = WM8994_GP4_EINT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	[WM8994_IRQ_GPIO(5)] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		.mask = WM8994_GP5_EINT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	[WM8994_IRQ_GPIO(6)] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		.mask = WM8994_GP6_EINT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	[WM8994_IRQ_GPIO(7)] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		.mask = WM8994_GP7_EINT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	[WM8994_IRQ_GPIO(8)] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 		.mask = WM8994_GP8_EINT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	[WM8994_IRQ_GPIO(9)] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		.mask = WM8994_GP8_EINT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	[WM8994_IRQ_GPIO(10)] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		.mask = WM8994_GP10_EINT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	[WM8994_IRQ_GPIO(11)] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		.mask = WM8994_GP11_EINT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static const struct regmap_irq_chip wm8994_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	.name = "wm8994",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	.irqs = wm8994_irqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	.num_irqs = ARRAY_SIZE(wm8994_irqs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	.num_regs = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	.status_base = WM8994_INTERRUPT_STATUS_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	.mask_base = WM8994_INTERRUPT_STATUS_1_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	.ack_base = WM8994_INTERRUPT_STATUS_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	.runtime_pm = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static void wm8994_edge_irq_enable(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static void wm8994_edge_irq_disable(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static struct irq_chip wm8994_edge_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	.name			= "wm8994_edge",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	.irq_disable		= wm8994_edge_irq_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	.irq_enable		= wm8994_edge_irq_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static irqreturn_t wm8994_edge_irq(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	struct wm8994 *wm8994 = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	while (gpio_get_value_cansleep(wm8994->pdata.irq_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		handle_nested_irq(irq_find_mapping(wm8994->edge_irq, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static int wm8994_edge_irq_map(struct irq_domain *h, unsigned int virq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 			       irq_hw_number_t hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	struct wm8994 *wm8994 = h->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	irq_set_chip_data(virq, wm8994);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	irq_set_chip_and_handler(virq, &wm8994_edge_irq_chip, handle_edge_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	irq_set_nested_thread(virq, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	irq_set_noprobe(virq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static const struct irq_domain_ops wm8994_edge_irq_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	.map	= wm8994_edge_irq_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	.xlate	= irq_domain_xlate_twocell,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) int wm8994_irq_init(struct wm8994 *wm8994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	unsigned long irqflags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	struct wm8994_pdata *pdata = &wm8994->pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	if (!wm8994->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		dev_warn(wm8994->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 			 "No interrupt specified, no interrupts\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		wm8994->irq_base = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	/* select user or default irq flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	irqflags = IRQF_TRIGGER_HIGH | IRQF_ONESHOT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	if (pdata->irq_flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		irqflags = pdata->irq_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	/* use a GPIO for edge triggered controllers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	if (irqflags & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		if (gpio_to_irq(pdata->irq_gpio) != wm8994->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 			dev_warn(wm8994->dev, "IRQ %d is not GPIO %d (%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 				 wm8994->irq, pdata->irq_gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 				 gpio_to_irq(pdata->irq_gpio));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 			wm8994->irq = gpio_to_irq(pdata->irq_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		ret = devm_gpio_request_one(wm8994->dev, pdata->irq_gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 					    GPIOF_IN, "WM8994 IRQ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 			dev_err(wm8994->dev, "Failed to get IRQ GPIO: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 				ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		wm8994->edge_irq = irq_domain_add_linear(NULL, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 							 &wm8994_edge_irq_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 							 wm8994);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		ret = regmap_add_irq_chip(wm8994->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 					  irq_create_mapping(wm8994->edge_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 							     0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 					  IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 					  wm8994->irq_base, &wm8994_irq_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 					  &wm8994->irq_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 			dev_err(wm8994->dev, "Failed to get IRQ: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 				ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		ret = request_threaded_irq(wm8994->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 					   NULL, wm8994_edge_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 					   irqflags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 					   "WM8994 edge", wm8994);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		ret = regmap_add_irq_chip(wm8994->regmap, wm8994->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 					  irqflags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 					  wm8994->irq_base, &wm8994_irq_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 					  &wm8994->irq_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		dev_err(wm8994->dev, "Failed to register IRQ chip: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	/* Enable top level interrupt if it was masked */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	wm8994_reg_write(wm8994, WM8994_INTERRUPT_CONTROL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) EXPORT_SYMBOL(wm8994_irq_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) void wm8994_irq_exit(struct wm8994 *wm8994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	regmap_del_irq_chip(wm8994->irq, wm8994->irq_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) EXPORT_SYMBOL(wm8994_irq_exit);