^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * wm831x-auxadc.c -- AUXADC for Wolfson WM831x PMICs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2009-2011 Wolfson Microelectronics PLC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/mfd/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/mfd/wm831x/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/mfd/wm831x/pdata.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/mfd/wm831x/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/mfd/wm831x/auxadc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/mfd/wm831x/otp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/mfd/wm831x/regulator.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) struct wm831x_auxadc_req {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) enum wm831x_auxadc input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) struct completion done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static int wm831x_auxadc_read_irq(struct wm831x *wm831x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) enum wm831x_auxadc input)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct wm831x_auxadc_req *req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) bool ena = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) req = kzalloc(sizeof(*req), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) if (!req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) init_completion(&req->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) req->input = input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) req->val = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) mutex_lock(&wm831x->auxadc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* Enqueue the request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) list_add(&req->list, &wm831x->auxadc_pending);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) ena = !wm831x->auxadc_active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) if (ena) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) ret = wm831x_set_bits(wm831x, WM831X_AUXADC_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) WM831X_AUX_ENA, WM831X_AUX_ENA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) dev_err(wm831x->dev, "Failed to enable AUXADC: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* Enable the conversion if not already running */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) if (!(wm831x->auxadc_active & (1 << input))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) ret = wm831x_set_bits(wm831x, WM831X_AUXADC_SOURCE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 1 << input, 1 << input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) dev_err(wm831x->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) "Failed to set AUXADC source: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) wm831x->auxadc_active |= 1 << input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* We convert at the fastest rate possible */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) if (ena) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) ret = wm831x_set_bits(wm831x, WM831X_AUXADC_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) WM831X_AUX_CVT_ENA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) WM831X_AUX_RATE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) WM831X_AUX_CVT_ENA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) WM831X_AUX_RATE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) dev_err(wm831x->dev, "Failed to start AUXADC: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) mutex_unlock(&wm831x->auxadc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* Wait for an interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) wait_for_completion_timeout(&req->done, msecs_to_jiffies(500));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) mutex_lock(&wm831x->auxadc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) ret = req->val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) list_del(&req->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) mutex_unlock(&wm831x->auxadc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) kfree(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static irqreturn_t wm831x_auxadc_irq(int irq, void *irq_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct wm831x *wm831x = irq_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct wm831x_auxadc_req *req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) int ret, input, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) ret = wm831x_reg_read(wm831x, WM831X_AUXADC_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) dev_err(wm831x->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) "Failed to read AUXADC data: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) input = ((ret & WM831X_AUX_DATA_SRC_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) >> WM831X_AUX_DATA_SRC_SHIFT) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) if (input == 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) input = WM831X_AUX_CAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) val = ret & WM831X_AUX_DATA_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) mutex_lock(&wm831x->auxadc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* Disable this conversion, we're about to complete all users */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) wm831x_set_bits(wm831x, WM831X_AUXADC_SOURCE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 1 << input, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) wm831x->auxadc_active &= ~(1 << input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* Turn off the entire convertor if idle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) if (!wm831x->auxadc_active)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) wm831x_reg_write(wm831x, WM831X_AUXADC_CONTROL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /* Wake up any threads waiting for this request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) list_for_each_entry(req, &wm831x->auxadc_pending, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) if (req->input == input) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) req->val = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) complete(&req->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) mutex_unlock(&wm831x->auxadc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static int wm831x_auxadc_read_polled(struct wm831x *wm831x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) enum wm831x_auxadc input)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) int ret, src, timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) mutex_lock(&wm831x->auxadc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) ret = wm831x_set_bits(wm831x, WM831X_AUXADC_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) WM831X_AUX_ENA, WM831X_AUX_ENA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) dev_err(wm831x->dev, "Failed to enable AUXADC: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /* We force a single source at present */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) src = input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) ret = wm831x_reg_write(wm831x, WM831X_AUXADC_SOURCE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 1 << src);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) dev_err(wm831x->dev, "Failed to set AUXADC source: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) ret = wm831x_set_bits(wm831x, WM831X_AUXADC_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) WM831X_AUX_CVT_ENA, WM831X_AUX_CVT_ENA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) dev_err(wm831x->dev, "Failed to start AUXADC: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) goto disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* If we're not using interrupts then poll the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * interrupt status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) timeout = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) while (timeout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) ret = wm831x_reg_read(wm831x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) WM831X_INTERRUPT_STATUS_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) dev_err(wm831x->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) "ISR 1 read failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) goto disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /* Did it complete? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) if (ret & WM831X_AUXADC_DATA_EINT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) wm831x_reg_write(wm831x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) WM831X_INTERRUPT_STATUS_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) WM831X_AUXADC_DATA_EINT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) dev_err(wm831x->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) "AUXADC conversion timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) ret = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) goto disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) ret = wm831x_reg_read(wm831x, WM831X_AUXADC_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) dev_err(wm831x->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) "Failed to read AUXADC data: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) goto disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) src = ((ret & WM831X_AUX_DATA_SRC_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) >> WM831X_AUX_DATA_SRC_SHIFT) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) if (src == 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) src = WM831X_AUX_CAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if (src != input) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) dev_err(wm831x->dev, "Data from source %d not %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) src, input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) ret &= WM831X_AUX_DATA_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) wm831x_set_bits(wm831x, WM831X_AUXADC_CONTROL, WM831X_AUX_ENA, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) mutex_unlock(&wm831x->auxadc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * wm831x_auxadc_read: Read a value from the WM831x AUXADC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) * @wm831x: Device to read from.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * @input: AUXADC input to read.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) int wm831x_auxadc_read(struct wm831x *wm831x, enum wm831x_auxadc input)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) return wm831x->auxadc_read(wm831x, input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) EXPORT_SYMBOL_GPL(wm831x_auxadc_read);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) * wm831x_auxadc_read_uv: Read a voltage from the WM831x AUXADC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * @wm831x: Device to read from.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) * @input: AUXADC input to read.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) int wm831x_auxadc_read_uv(struct wm831x *wm831x, enum wm831x_auxadc input)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) ret = wm831x_auxadc_read(wm831x, input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) ret *= 1465;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) EXPORT_SYMBOL_GPL(wm831x_auxadc_read_uv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) void wm831x_auxadc_init(struct wm831x *wm831x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) mutex_init(&wm831x->auxadc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) INIT_LIST_HEAD(&wm831x->auxadc_pending);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) if (wm831x->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) wm831x->auxadc_read = wm831x_auxadc_read_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) ret = request_threaded_irq(wm831x_irq(wm831x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) WM831X_IRQ_AUXADC_DATA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) NULL, wm831x_auxadc_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) "auxadc", wm831x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) dev_err(wm831x->dev, "AUXADC IRQ request failed: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) wm831x->auxadc_read = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) if (!wm831x->auxadc_read)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) wm831x->auxadc_read = wm831x_auxadc_read_polled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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