Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * MFD driver for TWL6040 audio device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Authors:	Misael Lopez Cruz <misael.lopez@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *		Jorge Eduardo Candelaria <jorge.candelaria@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *		Peter Ujfalusi <peter.ujfalusi@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * Copyright:	(C) 2011 Texas Instruments, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/of_gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include <linux/mfd/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #include <linux/mfd/twl6040.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define VIBRACTRL_MEMBER(reg) ((reg == TWL6040_REG_VIBCTLL) ? 0 : 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define TWL6040_NUM_SUPPLIES	(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) static const struct reg_default twl6040_defaults[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	{ 0x01, 0x4B }, /* REG_ASICID	(ro) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	{ 0x02, 0x00 }, /* REG_ASICREV	(ro) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	{ 0x03, 0x00 }, /* REG_INTID	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	{ 0x04, 0x00 }, /* REG_INTMR	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	{ 0x05, 0x00 }, /* REG_NCPCTRL	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	{ 0x06, 0x00 }, /* REG_LDOCTL	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	{ 0x07, 0x60 }, /* REG_HPPLLCTL	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	{ 0x08, 0x00 }, /* REG_LPPLLCTL	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	{ 0x09, 0x4A }, /* REG_LPPLLDIV	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	{ 0x0A, 0x00 }, /* REG_AMICBCTL	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	{ 0x0B, 0x00 }, /* REG_DMICBCTL	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	{ 0x0C, 0x00 }, /* REG_MICLCTL	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	{ 0x0D, 0x00 }, /* REG_MICRCTL	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	{ 0x0E, 0x00 }, /* REG_MICGAIN	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	{ 0x0F, 0x1B }, /* REG_LINEGAIN	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	{ 0x10, 0x00 }, /* REG_HSLCTL	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	{ 0x11, 0x00 }, /* REG_HSRCTL	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	{ 0x12, 0x00 }, /* REG_HSGAIN	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	{ 0x13, 0x00 }, /* REG_EARCTL	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	{ 0x14, 0x00 }, /* REG_HFLCTL	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	{ 0x15, 0x00 }, /* REG_HFLGAIN	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	{ 0x16, 0x00 }, /* REG_HFRCTL	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	{ 0x17, 0x00 }, /* REG_HFRGAIN	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	{ 0x18, 0x00 }, /* REG_VIBCTLL	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	{ 0x19, 0x00 }, /* REG_VIBDATL	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	{ 0x1A, 0x00 }, /* REG_VIBCTLR	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	{ 0x1B, 0x00 }, /* REG_VIBDATR	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	{ 0x1C, 0x00 }, /* REG_HKCTL1	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	{ 0x1D, 0x00 }, /* REG_HKCTL2	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	{ 0x1E, 0x00 }, /* REG_GPOCTL	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	{ 0x1F, 0x00 }, /* REG_ALB	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	{ 0x20, 0x00 }, /* REG_DLB	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	/* 0x28, REG_TRIM1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	/* 0x29, REG_TRIM2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	/* 0x2A, REG_TRIM3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	/* 0x2B, REG_HSOTRIM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	/* 0x2C, REG_HFOTRIM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	{ 0x2D, 0x08 }, /* REG_ACCCTL	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	{ 0x2E, 0x00 }, /* REG_STATUS	(ro) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) static struct reg_sequence twl6040_patch[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	 * Select I2C bus access to dual access registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	 * Interrupt register is cleared on read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	 * Select fast mode for i2c (400KHz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	{ TWL6040_REG_ACCCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		TWL6040_I2CSEL | TWL6040_INTCLRMODE | TWL6040_I2CMODE(1) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) static bool twl6040_has_vibra(struct device_node *parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	struct device_node *node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	node = of_get_child_by_name(parent, "vibra");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	if (node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		of_node_put(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) int twl6040_reg_read(struct twl6040 *twl6040, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	ret = regmap_read(twl6040->regmap, reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) EXPORT_SYMBOL(twl6040_reg_read);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) int twl6040_reg_write(struct twl6040 *twl6040, unsigned int reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	ret = regmap_write(twl6040->regmap, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) EXPORT_SYMBOL(twl6040_reg_write);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) int twl6040_set_bits(struct twl6040 *twl6040, unsigned int reg, u8 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	return regmap_update_bits(twl6040->regmap, reg, mask, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) EXPORT_SYMBOL(twl6040_set_bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) int twl6040_clear_bits(struct twl6040 *twl6040, unsigned int reg, u8 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	return regmap_update_bits(twl6040->regmap, reg, mask, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) EXPORT_SYMBOL(twl6040_clear_bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* twl6040 codec manual power-up sequence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static int twl6040_power_up_manual(struct twl6040 *twl6040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	u8 ldoctl, ncpctl, lppllctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	/* enable high-side LDO, reference system and internal oscillator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	ldoctl = TWL6040_HSLDOENA | TWL6040_REFENA | TWL6040_OSCENA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	ret = twl6040_reg_write(twl6040, TWL6040_REG_LDOCTL, ldoctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	usleep_range(10000, 10500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	/* enable negative charge pump */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	ncpctl = TWL6040_NCPENA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	ret = twl6040_reg_write(twl6040, TWL6040_REG_NCPCTL, ncpctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		goto ncp_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	usleep_range(1000, 1500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	/* enable low-side LDO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	ldoctl |= TWL6040_LSLDOENA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	ret = twl6040_reg_write(twl6040, TWL6040_REG_LDOCTL, ldoctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		goto lsldo_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	usleep_range(1000, 1500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	/* enable low-power PLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	lppllctl = TWL6040_LPLLENA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	ret = twl6040_reg_write(twl6040, TWL6040_REG_LPPLLCTL, lppllctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		goto lppll_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	usleep_range(5000, 5500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	/* disable internal oscillator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	ldoctl &= ~TWL6040_OSCENA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	ret = twl6040_reg_write(twl6040, TWL6040_REG_LDOCTL, ldoctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		goto osc_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) osc_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	lppllctl &= ~TWL6040_LPLLENA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	twl6040_reg_write(twl6040, TWL6040_REG_LPPLLCTL, lppllctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) lppll_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	ldoctl &= ~TWL6040_LSLDOENA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	twl6040_reg_write(twl6040, TWL6040_REG_LDOCTL, ldoctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) lsldo_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	ncpctl &= ~TWL6040_NCPENA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	twl6040_reg_write(twl6040, TWL6040_REG_NCPCTL, ncpctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) ncp_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	ldoctl &= ~(TWL6040_HSLDOENA | TWL6040_REFENA | TWL6040_OSCENA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	twl6040_reg_write(twl6040, TWL6040_REG_LDOCTL, ldoctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	dev_err(twl6040->dev, "manual power-up failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /* twl6040 manual power-down sequence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static void twl6040_power_down_manual(struct twl6040 *twl6040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	u8 ncpctl, ldoctl, lppllctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	ncpctl = twl6040_reg_read(twl6040, TWL6040_REG_NCPCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	ldoctl = twl6040_reg_read(twl6040, TWL6040_REG_LDOCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	lppllctl = twl6040_reg_read(twl6040, TWL6040_REG_LPPLLCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	/* enable internal oscillator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	ldoctl |= TWL6040_OSCENA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	twl6040_reg_write(twl6040, TWL6040_REG_LDOCTL, ldoctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	usleep_range(1000, 1500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	/* disable low-power PLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	lppllctl &= ~TWL6040_LPLLENA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	twl6040_reg_write(twl6040, TWL6040_REG_LPPLLCTL, lppllctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	/* disable low-side LDO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	ldoctl &= ~TWL6040_LSLDOENA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	twl6040_reg_write(twl6040, TWL6040_REG_LDOCTL, ldoctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	/* disable negative charge pump */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	ncpctl &= ~TWL6040_NCPENA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	twl6040_reg_write(twl6040, TWL6040_REG_NCPCTL, ncpctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	/* disable high-side LDO, reference system and internal oscillator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	ldoctl &= ~(TWL6040_HSLDOENA | TWL6040_REFENA | TWL6040_OSCENA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	twl6040_reg_write(twl6040, TWL6040_REG_LDOCTL, ldoctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static irqreturn_t twl6040_readyint_handler(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	struct twl6040 *twl6040 = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	complete(&twl6040->ready);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static irqreturn_t twl6040_thint_handler(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	struct twl6040 *twl6040 = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	u8 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	status = twl6040_reg_read(twl6040, TWL6040_REG_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	if (status & TWL6040_TSHUTDET) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		dev_warn(twl6040->dev, "Thermal shutdown, powering-off");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		twl6040_power(twl6040, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 		dev_warn(twl6040->dev, "Leaving thermal shutdown, powering-on");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		twl6040_power(twl6040, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) static int twl6040_power_up_automatic(struct twl6040 *twl6040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	int time_left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	gpio_set_value(twl6040->audpwron, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	time_left = wait_for_completion_timeout(&twl6040->ready,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 						msecs_to_jiffies(144));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	if (!time_left) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		u8 intid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		dev_warn(twl6040->dev, "timeout waiting for READYINT\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		intid = twl6040_reg_read(twl6040, TWL6040_REG_INTID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		if (!(intid & TWL6040_READYINT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 			dev_err(twl6040->dev, "automatic power-up failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 			gpio_set_value(twl6040->audpwron, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 			return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) int twl6040_power(struct twl6040 *twl6040, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	mutex_lock(&twl6040->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 		/* already powered-up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 		if (twl6040->power_count++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 			goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		ret = clk_prepare_enable(twl6040->clk32k);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 		if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 			twl6040->power_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 			goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		/* Allow writes to the chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 		regcache_cache_only(twl6040->regmap, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 		if (gpio_is_valid(twl6040->audpwron)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 			/* use automatic power-up sequence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 			ret = twl6040_power_up_automatic(twl6040);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 			if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 				clk_disable_unprepare(twl6040->clk32k);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 				twl6040->power_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 				goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 			/* use manual power-up sequence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 			ret = twl6040_power_up_manual(twl6040);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 			if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 				clk_disable_unprepare(twl6040->clk32k);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 				twl6040->power_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 				goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 		 * Register access can produce errors after power-up unless we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 		 * wait at least 8ms based on measurements on duovero.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 		usleep_range(10000, 12000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 		/* Sync with the HW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 		ret = regcache_sync(twl6040->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 		if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 			dev_err(twl6040->dev, "Failed to sync with the HW: %i\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 				ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 			goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 		/* Default PLL configuration after power up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 		twl6040->pll = TWL6040_SYSCLK_SEL_LPPLL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 		twl6040->sysclk_rate = 19200000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 		/* already powered-down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 		if (!twl6040->power_count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 			dev_err(twl6040->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 				"device is already powered-off\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 			ret = -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 			goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 		if (--twl6040->power_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 			goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 		if (gpio_is_valid(twl6040->audpwron)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 			/* use AUDPWRON line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 			gpio_set_value(twl6040->audpwron, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 			/* power-down sequence latency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 			usleep_range(500, 700);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 			/* use manual power-down sequence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 			twl6040_power_down_manual(twl6040);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 		/* Set regmap to cache only and mark it as dirty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 		regcache_cache_only(twl6040->regmap, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 		regcache_mark_dirty(twl6040->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 		twl6040->sysclk_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 		if (twl6040->pll == TWL6040_SYSCLK_SEL_HPPLL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 			clk_disable_unprepare(twl6040->mclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 			twl6040->mclk_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 		clk_disable_unprepare(twl6040->clk32k);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	mutex_unlock(&twl6040->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) EXPORT_SYMBOL(twl6040_power);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) int twl6040_set_pll(struct twl6040 *twl6040, int pll_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 		    unsigned int freq_in, unsigned int freq_out)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	u8 hppllctl, lppllctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	mutex_lock(&twl6040->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	hppllctl = twl6040_reg_read(twl6040, TWL6040_REG_HPPLLCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	lppllctl = twl6040_reg_read(twl6040, TWL6040_REG_LPPLLCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	/* Force full reconfiguration when switching between PLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	if (pll_id != twl6040->pll) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 		twl6040->sysclk_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 		twl6040->mclk_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	switch (pll_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	case TWL6040_SYSCLK_SEL_LPPLL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 		/* low-power PLL divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 		/* Change the sysclk configuration only if it has been canged */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 		if (twl6040->sysclk_rate != freq_out) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 			switch (freq_out) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 			case 17640000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 				lppllctl |= TWL6040_LPLLFIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 				break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 			case 19200000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 				lppllctl &= ~TWL6040_LPLLFIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 				break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 			default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 				dev_err(twl6040->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 					"freq_out %d not supported\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 					freq_out);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 				ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 				goto pll_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 			twl6040_reg_write(twl6040, TWL6040_REG_LPPLLCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 					  lppllctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 		/* The PLL in use has not been change, we can exit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 		if (twl6040->pll == pll_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 		switch (freq_in) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 		case 32768:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 			lppllctl |= TWL6040_LPLLENA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 			twl6040_reg_write(twl6040, TWL6040_REG_LPPLLCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 					  lppllctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 			mdelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 			lppllctl &= ~TWL6040_HPLLSEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 			twl6040_reg_write(twl6040, TWL6040_REG_LPPLLCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 					  lppllctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 			hppllctl &= ~TWL6040_HPLLENA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 			twl6040_reg_write(twl6040, TWL6040_REG_HPPLLCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 					  hppllctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 		default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 			dev_err(twl6040->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 				"freq_in %d not supported\n", freq_in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 			ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 			goto pll_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 		clk_disable_unprepare(twl6040->mclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 	case TWL6040_SYSCLK_SEL_HPPLL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 		/* high-performance PLL can provide only 19.2 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 		if (freq_out != 19200000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 			dev_err(twl6040->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 				"freq_out %d not supported\n", freq_out);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 			ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 			goto pll_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 		if (twl6040->mclk_rate != freq_in) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 			hppllctl &= ~TWL6040_MCLK_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 			switch (freq_in) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 			case 12000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 				/* PLL enabled, active mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 				hppllctl |= TWL6040_MCLK_12000KHZ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 					    TWL6040_HPLLENA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 				break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 			case 19200000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 				/* PLL enabled, bypass mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 				hppllctl |= TWL6040_MCLK_19200KHZ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 					    TWL6040_HPLLBP | TWL6040_HPLLENA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 				break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 			case 26000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 				/* PLL enabled, active mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 				hppllctl |= TWL6040_MCLK_26000KHZ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 					    TWL6040_HPLLENA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 				break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 			case 38400000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 				/* PLL enabled, bypass mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 				hppllctl |= TWL6040_MCLK_38400KHZ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 					    TWL6040_HPLLBP | TWL6040_HPLLENA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 				break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 			default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 				dev_err(twl6040->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 					"freq_in %d not supported\n", freq_in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 				ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 				goto pll_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 			/* When switching to HPPLL, enable the mclk first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 			if (pll_id != twl6040->pll)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 				clk_prepare_enable(twl6040->mclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 			/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 			 * enable clock slicer to ensure input waveform is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 			 * square
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 			 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 			hppllctl |= TWL6040_HPLLSQRENA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 			twl6040_reg_write(twl6040, TWL6040_REG_HPPLLCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 					  hppllctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 			usleep_range(500, 700);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) 			lppllctl |= TWL6040_HPLLSEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) 			twl6040_reg_write(twl6040, TWL6040_REG_LPPLLCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 					  lppllctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 			lppllctl &= ~TWL6040_LPLLENA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 			twl6040_reg_write(twl6040, TWL6040_REG_LPPLLCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) 					  lppllctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) 			twl6040->mclk_rate = freq_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) 		dev_err(twl6040->dev, "unknown pll id %d\n", pll_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) 		ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) 		goto pll_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) 	twl6040->sysclk_rate = freq_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) 	twl6040->pll = pll_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) pll_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) 	mutex_unlock(&twl6040->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) EXPORT_SYMBOL(twl6040_set_pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) int twl6040_get_pll(struct twl6040 *twl6040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) 	if (twl6040->power_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) 		return twl6040->pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) EXPORT_SYMBOL(twl6040_get_pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) unsigned int twl6040_get_sysclk(struct twl6040 *twl6040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) 	return twl6040->sysclk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) EXPORT_SYMBOL(twl6040_get_sysclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) /* Get the combined status of the vibra control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) int twl6040_get_vibralr_status(struct twl6040 *twl6040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) 	unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) 	u8 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) 	ret = regmap_read(twl6040->regmap, TWL6040_REG_VIBCTLL, &reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) 	if (ret != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) 	status = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) 	ret = regmap_read(twl6040->regmap, TWL6040_REG_VIBCTLR, &reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) 	if (ret != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) 	status |= reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) 	status &= (TWL6040_VIBENA | TWL6040_VIBSEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) 	return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) EXPORT_SYMBOL(twl6040_get_vibralr_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) static struct resource twl6040_vibra_rsrc[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) 		.flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) static struct resource twl6040_codec_rsrc[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) 		.flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) static bool twl6040_readable_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) 	/* Register 0 is not readable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) 	if (!reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) 		return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) 	return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) static bool twl6040_volatile_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) 	switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) 	case TWL6040_REG_ASICID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) 	case TWL6040_REG_ASICREV:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) 	case TWL6040_REG_INTID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) 	case TWL6040_REG_LPPLLCTL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) 	case TWL6040_REG_HPPLLCTL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) 	case TWL6040_REG_STATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) 		return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) 		return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) static bool twl6040_writeable_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) 	switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) 	case TWL6040_REG_ASICID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) 	case TWL6040_REG_ASICREV:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) 	case TWL6040_REG_STATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) 		return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) 		return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) static const struct regmap_config twl6040_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) 	.reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) 	.val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) 	.reg_defaults = twl6040_defaults,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) 	.num_reg_defaults = ARRAY_SIZE(twl6040_defaults),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) 	.max_register = TWL6040_REG_STATUS, /* 0x2e */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) 	.readable_reg = twl6040_readable_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) 	.volatile_reg = twl6040_volatile_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) 	.writeable_reg = twl6040_writeable_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) 	.cache_type = REGCACHE_RBTREE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) 	.use_single_read = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) 	.use_single_write = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) static const struct regmap_irq twl6040_irqs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) 	{ .reg_offset = 0, .mask = TWL6040_THINT, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) 	{ .reg_offset = 0, .mask = TWL6040_PLUGINT | TWL6040_UNPLUGINT, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) 	{ .reg_offset = 0, .mask = TWL6040_HOOKINT, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) 	{ .reg_offset = 0, .mask = TWL6040_HFINT, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) 	{ .reg_offset = 0, .mask = TWL6040_VIBINT, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) 	{ .reg_offset = 0, .mask = TWL6040_READYINT, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) static struct regmap_irq_chip twl6040_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) 	.name = "twl6040",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) 	.irqs = twl6040_irqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) 	.num_irqs = ARRAY_SIZE(twl6040_irqs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) 	.num_regs = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) 	.status_base = TWL6040_REG_INTID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) 	.mask_base = TWL6040_REG_INTMR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) static int twl6040_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) 			 const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) 	struct device_node *node = client->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) 	struct twl6040 *twl6040;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) 	struct mfd_cell *cell = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) 	int irq, ret, children = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) 	if (!node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) 		dev_err(&client->dev, "of node is missing\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) 	/* In order to operate correctly we need valid interrupt config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) 	if (!client->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) 		dev_err(&client->dev, "Invalid IRQ configuration\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) 	twl6040 = devm_kzalloc(&client->dev, sizeof(struct twl6040),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) 			       GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) 	if (!twl6040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) 	twl6040->regmap = devm_regmap_init_i2c(client, &twl6040_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) 	if (IS_ERR(twl6040->regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) 		return PTR_ERR(twl6040->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) 	i2c_set_clientdata(client, twl6040);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) 	twl6040->clk32k = devm_clk_get(&client->dev, "clk32k");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) 	if (IS_ERR(twl6040->clk32k)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) 		if (PTR_ERR(twl6040->clk32k) == -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) 			return -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) 		dev_dbg(&client->dev, "clk32k is not handled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) 		twl6040->clk32k = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) 	twl6040->mclk = devm_clk_get(&client->dev, "mclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) 	if (IS_ERR(twl6040->mclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) 		if (PTR_ERR(twl6040->mclk) == -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) 			return -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) 		dev_dbg(&client->dev, "mclk is not handled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) 		twl6040->mclk = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) 	twl6040->supplies[0].supply = "vio";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) 	twl6040->supplies[1].supply = "v2v1";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) 	ret = devm_regulator_bulk_get(&client->dev, TWL6040_NUM_SUPPLIES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) 				      twl6040->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) 	if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) 		dev_err(&client->dev, "Failed to get supplies: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) 	ret = regulator_bulk_enable(TWL6040_NUM_SUPPLIES, twl6040->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) 	if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) 		dev_err(&client->dev, "Failed to enable supplies: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) 	twl6040->dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) 	twl6040->irq = client->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) 	mutex_init(&twl6040->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) 	init_completion(&twl6040->ready);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) 	regmap_register_patch(twl6040->regmap, twl6040_patch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) 			      ARRAY_SIZE(twl6040_patch));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) 	twl6040->rev = twl6040_reg_read(twl6040, TWL6040_REG_ASICREV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) 	if (twl6040->rev < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) 		dev_err(&client->dev, "Failed to read revision register: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) 			twl6040->rev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) 		ret = twl6040->rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) 		goto gpio_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) 	/* ERRATA: Automatic power-up is not possible in ES1.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) 	if (twl6040_get_revid(twl6040) > TWL6040_REV_ES1_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) 		twl6040->audpwron = of_get_named_gpio(node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) 						      "ti,audpwron-gpio", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) 		twl6040->audpwron = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) 	if (gpio_is_valid(twl6040->audpwron)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) 		ret = devm_gpio_request_one(&client->dev, twl6040->audpwron,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) 					    GPIOF_OUT_INIT_LOW, "audpwron");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) 			goto gpio_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) 		/* Clear any pending interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) 		twl6040_reg_read(twl6040, TWL6040_REG_INTID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) 	ret = regmap_add_irq_chip(twl6040->regmap, twl6040->irq, IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) 				  0, &twl6040_irq_chip, &twl6040->irq_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) 		goto gpio_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) 	twl6040->irq_ready = regmap_irq_get_virq(twl6040->irq_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) 						 TWL6040_IRQ_READY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) 	twl6040->irq_th = regmap_irq_get_virq(twl6040->irq_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) 					      TWL6040_IRQ_TH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) 	ret = devm_request_threaded_irq(twl6040->dev, twl6040->irq_ready, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) 					twl6040_readyint_handler, IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) 					"twl6040_irq_ready", twl6040);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) 		dev_err(twl6040->dev, "READY IRQ request failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) 		goto readyirq_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) 	ret = devm_request_threaded_irq(twl6040->dev, twl6040->irq_th, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) 					twl6040_thint_handler, IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) 					"twl6040_irq_th", twl6040);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) 		dev_err(twl6040->dev, "Thermal IRQ request failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) 		goto readyirq_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) 	 * The main functionality of twl6040 to provide audio on OMAP4+ systems.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) 	 * We can add the ASoC codec child whenever this driver has been loaded.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) 	irq = regmap_irq_get_virq(twl6040->irq_data, TWL6040_IRQ_PLUG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) 	cell = &twl6040->cells[children];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) 	cell->name = "twl6040-codec";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) 	twl6040_codec_rsrc[0].start = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) 	twl6040_codec_rsrc[0].end = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) 	cell->resources = twl6040_codec_rsrc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) 	cell->num_resources = ARRAY_SIZE(twl6040_codec_rsrc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) 	children++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) 	/* Vibra input driver support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) 	if (twl6040_has_vibra(node)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) 		irq = regmap_irq_get_virq(twl6040->irq_data, TWL6040_IRQ_VIB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) 		cell = &twl6040->cells[children];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) 		cell->name = "twl6040-vibra";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) 		twl6040_vibra_rsrc[0].start = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) 		twl6040_vibra_rsrc[0].end = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) 		cell->resources = twl6040_vibra_rsrc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) 		cell->num_resources = ARRAY_SIZE(twl6040_vibra_rsrc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) 		children++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) 	/* GPO support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) 	cell = &twl6040->cells[children];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) 	cell->name = "twl6040-gpo";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) 	children++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) 	/* PDM clock support  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) 	cell = &twl6040->cells[children];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) 	cell->name = "twl6040-pdmclk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) 	children++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) 	/* The chip is powered down so mark regmap to cache only and dirty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) 	regcache_cache_only(twl6040->regmap, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) 	regcache_mark_dirty(twl6040->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) 	ret = mfd_add_devices(&client->dev, -1, twl6040->cells, children,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) 			      NULL, 0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) 		goto readyirq_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) readyirq_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) 	regmap_del_irq_chip(twl6040->irq, twl6040->irq_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) gpio_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) 	regulator_bulk_disable(TWL6040_NUM_SUPPLIES, twl6040->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) static int twl6040_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) 	struct twl6040 *twl6040 = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) 	if (twl6040->power_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) 		twl6040_power(twl6040, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) 	regmap_del_irq_chip(twl6040->irq, twl6040->irq_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) 	mfd_remove_devices(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) 	regulator_bulk_disable(TWL6040_NUM_SUPPLIES, twl6040->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) static const struct i2c_device_id twl6040_i2c_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) 	{ "twl6040", 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) 	{ "twl6041", 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) 	{ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) MODULE_DEVICE_TABLE(i2c, twl6040_i2c_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) static struct i2c_driver twl6040_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) 		.name = "twl6040",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) 	.probe		= twl6040_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) 	.remove		= twl6040_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) 	.id_table	= twl6040_i2c_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) module_i2c_driver(twl6040_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) MODULE_DESCRIPTION("TWL6040 MFD");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) MODULE_AUTHOR("Misael Lopez Cruz <misael.lopez@ti.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) MODULE_AUTHOR("Jorge Eduardo Candelaria <jorge.candelaria@ti.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) MODULE_LICENSE("GPL");