^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * twl6030-irq.c - TWL6030 irq support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2005-2009 Texas Instruments, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Modifications to defer interrupt handling to a kernel thread:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 2006 MontaVista Software, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Based on tlv320aic23.c:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Copyright (c) by Kai Svahn <kai.svahn@nokia.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Code cleanup and modifications to IRQ handler.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * by syed khasim <x0khasim@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * TWL6030 specific code and IRQ handling changes by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * Jagadeesh Bhaskar Pakaravoor <j-pakaravoor@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * Balaji T K <balajitk@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/kthread.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/mfd/twl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/suspend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include "twl-core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * TWL6030 (unlike its predecessors, which had two level interrupt handling)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * three interrupt registers INT_STS_A, INT_STS_B and INT_STS_C.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * It exposes status bits saying who has raised an interrupt. There are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * three mask registers that corresponds to these status registers, that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * enables/disables these interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * We set up IRQs starting at a platform-specified base. An interrupt map table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * specifies mapping between interrupt number and the associated module.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define TWL6030_NR_IRQS 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static int twl6030_interrupt_mapping[24] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) PWR_INTR_OFFSET, /* Bit 0 PWRON */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) PWR_INTR_OFFSET, /* Bit 1 RPWRON */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) PWR_INTR_OFFSET, /* Bit 2 BAT_VLOW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) RTC_INTR_OFFSET, /* Bit 3 RTC_ALARM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) RTC_INTR_OFFSET, /* Bit 4 RTC_PERIOD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) HOTDIE_INTR_OFFSET, /* Bit 5 HOT_DIE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) SMPSLDO_INTR_OFFSET, /* Bit 6 VXXX_SHORT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) SMPSLDO_INTR_OFFSET, /* Bit 7 VMMC_SHORT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) SMPSLDO_INTR_OFFSET, /* Bit 8 VUSIM_SHORT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) BATDETECT_INTR_OFFSET, /* Bit 9 BAT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) SIMDETECT_INTR_OFFSET, /* Bit 10 SIM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) MMCDETECT_INTR_OFFSET, /* Bit 11 MMC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) RSV_INTR_OFFSET, /* Bit 12 Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) MADC_INTR_OFFSET, /* Bit 13 GPADC_RT_EOC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) MADC_INTR_OFFSET, /* Bit 14 GPADC_SW_EOC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) GASGAUGE_INTR_OFFSET, /* Bit 15 CC_AUTOCAL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) USBOTG_INTR_OFFSET, /* Bit 16 ID_WKUP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) USBOTG_INTR_OFFSET, /* Bit 17 VBUS_WKUP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) USBOTG_INTR_OFFSET, /* Bit 18 ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) USB_PRES_INTR_OFFSET, /* Bit 19 VBUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) CHARGER_INTR_OFFSET, /* Bit 20 CHRG_CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) CHARGERFAULT_INTR_OFFSET, /* Bit 21 EXT_CHRG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) CHARGERFAULT_INTR_OFFSET, /* Bit 22 INT_CHRG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) RSV_INTR_OFFSET, /* Bit 23 Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static int twl6032_interrupt_mapping[24] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) PWR_INTR_OFFSET, /* Bit 0 PWRON */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) PWR_INTR_OFFSET, /* Bit 1 RPWRON */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) PWR_INTR_OFFSET, /* Bit 2 SYS_VLOW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) RTC_INTR_OFFSET, /* Bit 3 RTC_ALARM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) RTC_INTR_OFFSET, /* Bit 4 RTC_PERIOD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) HOTDIE_INTR_OFFSET, /* Bit 5 HOT_DIE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) SMPSLDO_INTR_OFFSET, /* Bit 6 VXXX_SHORT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) PWR_INTR_OFFSET, /* Bit 7 SPDURATION */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) PWR_INTR_OFFSET, /* Bit 8 WATCHDOG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) BATDETECT_INTR_OFFSET, /* Bit 9 BAT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) SIMDETECT_INTR_OFFSET, /* Bit 10 SIM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) MMCDETECT_INTR_OFFSET, /* Bit 11 MMC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) MADC_INTR_OFFSET, /* Bit 12 GPADC_RT_EOC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) MADC_INTR_OFFSET, /* Bit 13 GPADC_SW_EOC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) GASGAUGE_INTR_OFFSET, /* Bit 14 CC_EOC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) GASGAUGE_INTR_OFFSET, /* Bit 15 CC_AUTOCAL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) USBOTG_INTR_OFFSET, /* Bit 16 ID_WKUP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) USBOTG_INTR_OFFSET, /* Bit 17 VBUS_WKUP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) USBOTG_INTR_OFFSET, /* Bit 18 ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) USB_PRES_INTR_OFFSET, /* Bit 19 VBUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) CHARGER_INTR_OFFSET, /* Bit 20 CHRG_CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) CHARGERFAULT_INTR_OFFSET, /* Bit 21 EXT_CHRG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) CHARGERFAULT_INTR_OFFSET, /* Bit 22 INT_CHRG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) RSV_INTR_OFFSET, /* Bit 23 Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /*----------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct twl6030_irq {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) unsigned int irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) int twl_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) bool irq_wake_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) atomic_t wakeirqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct notifier_block pm_nb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct irq_chip irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct irq_domain *irq_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) const int *irq_mapping_tbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static struct twl6030_irq *twl6030_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static int twl6030_irq_pm_notifier(struct notifier_block *notifier,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) unsigned long pm_event, void *unused)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) int chained_wakeups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct twl6030_irq *pdata = container_of(notifier, struct twl6030_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) pm_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) switch (pm_event) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) case PM_SUSPEND_PREPARE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) chained_wakeups = atomic_read(&pdata->wakeirqs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) if (chained_wakeups && !pdata->irq_wake_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) if (enable_irq_wake(pdata->twl_irq))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) pr_err("twl6030 IRQ wake enable failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) pdata->irq_wake_enabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) } else if (!chained_wakeups && pdata->irq_wake_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) disable_irq_wake(pdata->twl_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) pdata->irq_wake_enabled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) disable_irq(pdata->twl_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) case PM_POST_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) enable_irq(pdata->twl_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return NOTIFY_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * Threaded irq handler for the twl6030 interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * We query the interrupt controller in the twl6030 to determine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * which module is generating the interrupt request and call
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * handle_nested_irq for that module.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static irqreturn_t twl6030_irq_thread(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) u8 bytes[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) __le32 int_sts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) } sts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) u32 int_sts; /* sts.int_sts converted to CPU endianness */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct twl6030_irq *pdata = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /* read INT_STS_A, B and C in one shot using a burst read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) ret = twl_i2c_read(TWL_MODULE_PIH, sts.bytes, REG_INT_STS_A, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) pr_warn("twl6030_irq: I2C error %d reading PIH ISR\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) sts.bytes[3] = 0; /* Only 24 bits are valid*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * Since VBUS status bit is not reliable for VBUS disconnect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * use CHARGER VBUS detection status bit instead.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) if (sts.bytes[2] & 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) sts.bytes[2] |= 0x08;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) int_sts = le32_to_cpu(sts.int_sts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) for (i = 0; int_sts; int_sts >>= 1, i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if (int_sts & 0x1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) int module_irq =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) irq_find_mapping(pdata->irq_domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) pdata->irq_mapping_tbl[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) if (module_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) handle_nested_irq(module_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) pr_err("twl6030_irq: Unmapped PIH ISR %u detected\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) pr_debug("twl6030_irq: PIH ISR %u, virq%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) i, module_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * NOTE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * Simulation confirms that documentation is wrong w.r.t the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * interrupt status clear operation. A single *byte* write to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * any one of STS_A to STS_C register results in all three
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * STS registers being reset. Since it does not matter which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * value is written, all three registers are cleared on a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * single byte write, so we just use 0x0 to clear.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) ret = twl_i2c_write_u8(TWL_MODULE_PIH, 0x00, REG_INT_STS_A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) pr_warn("twl6030_irq: I2C error in clearing PIH ISR\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /*----------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static int twl6030_irq_set_wake(struct irq_data *d, unsigned int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) struct twl6030_irq *pdata = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if (on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) atomic_inc(&pdata->wakeirqs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) atomic_dec(&pdata->wakeirqs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) int twl6030_interrupt_unmask(u8 bit_mask, u8 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) u8 unmask_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) ret = twl_i2c_read_u8(TWL_MODULE_PIH, &unmask_value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) REG_INT_STS_A + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) unmask_value &= (~(bit_mask));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) ret |= twl_i2c_write_u8(TWL_MODULE_PIH, unmask_value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) REG_INT_STS_A + offset); /* unmask INT_MSK_A/B/C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) EXPORT_SYMBOL(twl6030_interrupt_unmask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) int twl6030_interrupt_mask(u8 bit_mask, u8 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) u8 mask_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) ret = twl_i2c_read_u8(TWL_MODULE_PIH, &mask_value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) REG_INT_STS_A + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) mask_value |= (bit_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) ret |= twl_i2c_write_u8(TWL_MODULE_PIH, mask_value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) REG_INT_STS_A + offset); /* mask INT_MSK_A/B/C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) EXPORT_SYMBOL(twl6030_interrupt_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) int twl6030_mmc_card_detect_config(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) u8 reg_val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /* Unmasking the Card detect Interrupt line for MMC1 from Phoenix */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) twl6030_interrupt_unmask(TWL6030_MMCDETECT_INT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) REG_INT_MSK_LINE_B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) twl6030_interrupt_unmask(TWL6030_MMCDETECT_INT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) REG_INT_MSK_STS_B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) * Initially Configuring MMC_CTRL for receiving interrupts &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) * Card status on TWL6030 for MMC1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) ret = twl_i2c_read_u8(TWL6030_MODULE_ID0, ®_val, TWL6030_MMCCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) pr_err("twl6030: Failed to read MMCCTRL, error %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) reg_val &= ~VMMC_AUTO_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) reg_val |= SW_FC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) ret = twl_i2c_write_u8(TWL6030_MODULE_ID0, reg_val, TWL6030_MMCCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) pr_err("twl6030: Failed to write MMCCTRL, error %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /* Configuring PullUp-PullDown register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) ret = twl_i2c_read_u8(TWL6030_MODULE_ID0, ®_val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) TWL6030_CFG_INPUT_PUPD3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) pr_err("twl6030: Failed to read CFG_INPUT_PUPD3, error %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) reg_val &= ~(MMC_PU | MMC_PD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) ret = twl_i2c_write_u8(TWL6030_MODULE_ID0, reg_val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) TWL6030_CFG_INPUT_PUPD3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) pr_err("twl6030: Failed to write CFG_INPUT_PUPD3, error %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) return irq_find_mapping(twl6030_irq->irq_domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) MMCDETECT_INTR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) EXPORT_SYMBOL(twl6030_mmc_card_detect_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) int twl6030_mmc_card_detect(struct device *dev, int slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) int ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) u8 read_reg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) struct platform_device *pdev = to_platform_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) if (pdev->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /* TWL6030 provide's Card detect support for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * only MMC1 controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) pr_err("Unknown MMC controller %d in %s\n", pdev->id, __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) * BIT0 of MMC_CTRL on TWL6030 provides card status for MMC1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) * 0 - Card not present ,1 - Card present
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) ret = twl_i2c_read_u8(TWL6030_MODULE_ID0, &read_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) TWL6030_MMCCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) if (ret >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) ret = read_reg & STS_MMC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) EXPORT_SYMBOL(twl6030_mmc_card_detect);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static int twl6030_irq_map(struct irq_domain *d, unsigned int virq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) irq_hw_number_t hwirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) struct twl6030_irq *pdata = d->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) irq_set_chip_data(virq, pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) irq_set_chip_and_handler(virq, &pdata->irq_chip, handle_simple_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) irq_set_nested_thread(virq, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) irq_set_parent(virq, pdata->twl_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) irq_set_noprobe(virq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static void twl6030_irq_unmap(struct irq_domain *d, unsigned int virq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) irq_set_chip_and_handler(virq, NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) irq_set_chip_data(virq, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) static const struct irq_domain_ops twl6030_irq_domain_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) .map = twl6030_irq_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) .unmap = twl6030_irq_unmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .xlate = irq_domain_xlate_onetwocell,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static const struct of_device_id twl6030_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {.compatible = "ti,twl6030", &twl6030_interrupt_mapping},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {.compatible = "ti,twl6032", &twl6032_interrupt_mapping},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) int twl6030_init_irq(struct device *dev, int irq_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) int nr_irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) u8 mask[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) const struct of_device_id *of_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) of_id = of_match_device(twl6030_of_match, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) if (!of_id || !of_id->data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) dev_err(dev, "Unknown TWL device model\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) nr_irqs = TWL6030_NR_IRQS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) twl6030_irq = devm_kzalloc(dev, sizeof(*twl6030_irq), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) if (!twl6030_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) mask[0] = 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) mask[1] = 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) mask[2] = 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) /* mask all int lines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) status = twl_i2c_write(TWL_MODULE_PIH, &mask[0], REG_INT_MSK_LINE_A, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) /* mask all int sts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) status |= twl_i2c_write(TWL_MODULE_PIH, &mask[0], REG_INT_MSK_STS_A, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) /* clear INT_STS_A,B,C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) status |= twl_i2c_write(TWL_MODULE_PIH, &mask[0], REG_INT_STS_A, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) if (status < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) dev_err(dev, "I2C err writing TWL_MODULE_PIH: %d\n", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) * install an irq handler for each of the modules;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) * clone dummy irq_chip since PIH can't *do* anything
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) twl6030_irq->irq_chip = dummy_irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) twl6030_irq->irq_chip.name = "twl6030";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) twl6030_irq->irq_chip.irq_set_type = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) twl6030_irq->irq_chip.irq_set_wake = twl6030_irq_set_wake;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) twl6030_irq->pm_nb.notifier_call = twl6030_irq_pm_notifier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) atomic_set(&twl6030_irq->wakeirqs, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) twl6030_irq->irq_mapping_tbl = of_id->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) twl6030_irq->irq_domain =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) irq_domain_add_linear(node, nr_irqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) &twl6030_irq_domain_ops, twl6030_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if (!twl6030_irq->irq_domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) dev_err(dev, "Can't add irq_domain\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) dev_info(dev, "PIH (irq %d) nested IRQs\n", irq_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) /* install an irq handler to demultiplex the TWL6030 interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) status = request_threaded_irq(irq_num, NULL, twl6030_irq_thread,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) IRQF_ONESHOT, "TWL6030-PIH", twl6030_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) if (status < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) dev_err(dev, "could not claim irq %d: %d\n", irq_num, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) goto fail_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) twl6030_irq->twl_irq = irq_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) register_pm_notifier(&twl6030_irq->pm_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) fail_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) irq_domain_remove(twl6030_irq->irq_domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) int twl6030_exit_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) if (twl6030_irq && twl6030_irq->twl_irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) unregister_pm_notifier(&twl6030_irq->pm_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) free_irq(twl6030_irq->twl_irq, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) * TODO: IRQ domain and allocated nested IRQ descriptors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) * should be freed somehow here. Now It can't be done, because
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) * child devices will not be deleted during removing of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) * TWL Core driver and they will still contain allocated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) * virt IRQs in their Resources tables.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) * The same prevents us from using devm_request_threaded_irq()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) * in this module.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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