^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Handle TWL4030 Power initialization
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2008 Nokia Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2006 Texas Instruments, Inc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Written by Kalle Jokiniemi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Peter De Schrijver <peter.de-schrijver@nokia.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Several fixes by Amit Kucheria <amit.kucheria@verdurent.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * This file is subject to the terms and conditions of the GNU General
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Public License. See the file "COPYING" in the main directory of this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * archive for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * This program is distributed in the hope that it will be useful,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * but WITHOUT ANY WARRANTY; without even the implied warranty of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * You should have received a copy of the GNU General Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * along with this program; if not, write to the Free Software
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/mfd/twl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <asm/mach-types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static u8 twl4030_start_script_address = 0x2b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* Register bits for P1, P2 and P3_SW_EVENTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define PWR_STOPON_PRWON BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PWR_STOPON_SYSEN BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define PWR_ENABLE_WARMRESET BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PWR_LVL_WAKEUP BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PWR_DEVACT BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PWR_DEVSLP BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PWR_DEVOFF BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* Register bits for CFG_P1_TRANSITION (also for P2 and P3) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define STARTON_SWBUG BIT(7) /* Start on watchdog */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define STARTON_VBUS BIT(5) /* Start on VBUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define STARTON_VBAT BIT(4) /* Start on battery insert */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define STARTON_RTC BIT(3) /* Start on RTC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define STARTON_USB BIT(2) /* Start on USB host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define STARTON_CHG BIT(1) /* Start on charger */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define STARTON_PWON BIT(0) /* Start on PWRON button */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SEQ_OFFSYNC (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define PHY_TO_OFF_PM_MASTER(p) (p - 0x36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define PHY_TO_OFF_PM_RECEIVER(p) (p - 0x5b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* resource - hfclk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define R_HFCLKOUT_DEV_GRP PHY_TO_OFF_PM_RECEIVER(0xe6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* PM events */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define R_P1_SW_EVENTS PHY_TO_OFF_PM_MASTER(0x46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define R_P2_SW_EVENTS PHY_TO_OFF_PM_MASTER(0x47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define R_P3_SW_EVENTS PHY_TO_OFF_PM_MASTER(0x48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define R_CFG_P1_TRANSITION PHY_TO_OFF_PM_MASTER(0x36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define R_CFG_P2_TRANSITION PHY_TO_OFF_PM_MASTER(0x37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define R_CFG_P3_TRANSITION PHY_TO_OFF_PM_MASTER(0x38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define END_OF_SCRIPT 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define R_SEQ_ADD_A2S PHY_TO_OFF_PM_MASTER(0x55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define R_SEQ_ADD_S2A12 PHY_TO_OFF_PM_MASTER(0x56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define R_SEQ_ADD_S2A3 PHY_TO_OFF_PM_MASTER(0x57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define R_SEQ_ADD_WARM PHY_TO_OFF_PM_MASTER(0x58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define R_MEMORY_ADDRESS PHY_TO_OFF_PM_MASTER(0x59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define R_MEMORY_DATA PHY_TO_OFF_PM_MASTER(0x5a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* resource configuration registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) <RESOURCE>_DEV_GRP at address 'n+0'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) <RESOURCE>_TYPE at address 'n+1'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) <RESOURCE>_REMAP at address 'n+2'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) <RESOURCE>_DEDICATED at address 'n+3'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define DEV_GRP_OFFSET 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define TYPE_OFFSET 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define REMAP_OFFSET 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define DEDICATED_OFFSET 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* Bit positions in the registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* <RESOURCE>_DEV_GRP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define DEV_GRP_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define DEV_GRP_MASK (7 << DEV_GRP_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* <RESOURCE>_TYPE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define TYPE_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define TYPE_MASK (7 << TYPE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define TYPE2_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define TYPE2_MASK (3 << TYPE2_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* <RESOURCE>_REMAP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define SLEEP_STATE_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define SLEEP_STATE_MASK (0xf << SLEEP_STATE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define OFF_STATE_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define OFF_STATE_MASK (0xf << OFF_STATE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static u8 res_config_addrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) [RES_VAUX1] = 0x17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) [RES_VAUX2] = 0x1b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) [RES_VAUX3] = 0x1f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) [RES_VAUX4] = 0x23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) [RES_VMMC1] = 0x27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) [RES_VMMC2] = 0x2b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) [RES_VPLL1] = 0x2f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) [RES_VPLL2] = 0x33,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) [RES_VSIM] = 0x37,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) [RES_VDAC] = 0x3b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) [RES_VINTANA1] = 0x3f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) [RES_VINTANA2] = 0x43,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) [RES_VINTDIG] = 0x47,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) [RES_VIO] = 0x4b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) [RES_VDD1] = 0x55,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) [RES_VDD2] = 0x63,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) [RES_VUSB_1V5] = 0x71,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) [RES_VUSB_1V8] = 0x74,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) [RES_VUSB_3V1] = 0x77,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) [RES_VUSBCP] = 0x7a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) [RES_REGEN] = 0x7f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) [RES_NRES_PWRON] = 0x82,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) [RES_CLKEN] = 0x85,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) [RES_SYSEN] = 0x88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) [RES_HFCLKOUT] = 0x8b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) [RES_32KCLKOUT] = 0x8e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) [RES_RESET] = 0x91,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) [RES_MAIN_REF] = 0x94,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * Usable values for .remap_sleep and .remap_off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * Based on table "5.3.3 Resource Operating modes"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) TWL_REMAP_OFF = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) TWL_REMAP_SLEEP = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) TWL_REMAP_ACTIVE = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * Macros to configure the PM register states for various resources.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * Note that we can make MSG_SINGULAR etc private to this driver once
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * omap3 has been made DT only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define TWL_DFLT_DELAY 2 /* typically 2 32 KiHz cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define TWL_DEV_GRP_P123 (DEV_GRP_P1 | DEV_GRP_P2 | DEV_GRP_P3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define TWL_RESOURCE_SET(res, state) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) { MSG_SINGULAR(DEV_GRP_NULL, (res), (state)), TWL_DFLT_DELAY }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define TWL_RESOURCE_ON(res) TWL_RESOURCE_SET(res, RES_STATE_ACTIVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define TWL_RESOURCE_OFF(res) TWL_RESOURCE_SET(res, RES_STATE_OFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define TWL_RESOURCE_RESET(res) TWL_RESOURCE_SET(res, RES_STATE_WRST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * It seems that type1 and type2 is just the resource init order
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * number for the type1 and type2 group.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define TWL_RESOURCE_SET_ACTIVE(res, state) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) { MSG_SINGULAR(DEV_GRP_NULL, (res), RES_STATE_ACTIVE), (state) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define TWL_RESOURCE_GROUP_RESET(group, type1, type2) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) { MSG_BROADCAST(DEV_GRP_NULL, (group), (type1), (type2), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) RES_STATE_WRST), TWL_DFLT_DELAY }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define TWL_RESOURCE_GROUP_SLEEP(group, type, type2) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) { MSG_BROADCAST(DEV_GRP_NULL, (group), (type), (type2), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) RES_STATE_SLEEP), TWL_DFLT_DELAY }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define TWL_RESOURCE_GROUP_ACTIVE(group, type, type2) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) { MSG_BROADCAST(DEV_GRP_NULL, (group), (type), (type2), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) RES_STATE_ACTIVE), TWL_DFLT_DELAY }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define TWL_REMAP_SLEEP(res, devgrp, typ, typ2) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) { .resource = (res), .devgroup = (devgrp), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .type = (typ), .type2 = (typ2), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .remap_off = TWL_REMAP_OFF, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .remap_sleep = TWL_REMAP_SLEEP, }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define TWL_REMAP_OFF(res, devgrp, typ, typ2) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) { .resource = (res), .devgroup = (devgrp), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .type = (typ), .type2 = (typ2), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .remap_off = TWL_REMAP_OFF, .remap_sleep = TWL_REMAP_OFF, }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static int twl4030_write_script_byte(u8 address, u8 byte)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, address, R_MEMORY_ADDRESS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, byte, R_MEMORY_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static int twl4030_write_script_ins(u8 address, u16 pmb_message,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) u8 delay, u8 next)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) address *= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) err = twl4030_write_script_byte(address++, pmb_message >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) err = twl4030_write_script_byte(address++, pmb_message & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) err = twl4030_write_script_byte(address++, delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) err = twl4030_write_script_byte(address++, next);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static int twl4030_write_script(u8 address, struct twl4030_ins *script,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) int err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) for (; len; len--, address++, script++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (len == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) err = twl4030_write_script_ins(address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) script->pmb_message,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) script->delay,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) END_OF_SCRIPT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) err = twl4030_write_script_ins(address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) script->pmb_message,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) script->delay,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) address + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static int twl4030_config_wakeup3_sequence(u8 address)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) u8 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /* Set SLEEP to ACTIVE SEQ address for P3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, address, R_SEQ_ADD_S2A3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /* P3 LVL_WAKEUP should be on LEVEL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) err = twl_i2c_read_u8(TWL_MODULE_PM_MASTER, &data, R_P3_SW_EVENTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) data |= PWR_LVL_WAKEUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, data, R_P3_SW_EVENTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) pr_err("TWL4030 wakeup sequence for P3 config error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) twl4030_config_wakeup12_sequence(const struct twl4030_power_data *pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) u8 address)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) u8 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /* Set SLEEP to ACTIVE SEQ address for P1 and P2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, address, R_SEQ_ADD_S2A12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /* P1/P2 LVL_WAKEUP should be on LEVEL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) err = twl_i2c_read_u8(TWL_MODULE_PM_MASTER, &data, R_P1_SW_EVENTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) data |= PWR_LVL_WAKEUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, data, R_P1_SW_EVENTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) err = twl_i2c_read_u8(TWL_MODULE_PM_MASTER, &data, R_P2_SW_EVENTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) data |= PWR_LVL_WAKEUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, data, R_P2_SW_EVENTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) if (pdata->ac_charger_quirk || machine_is_omap_3430sdp() ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) machine_is_omap_ldp()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /* Disabling AC charger effect on sleep-active transitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) err = twl_i2c_read_u8(TWL_MODULE_PM_MASTER, &data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) R_CFG_P1_TRANSITION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) data &= ~STARTON_CHG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) R_CFG_P1_TRANSITION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) pr_err("TWL4030 wakeup sequence for P1 and P2" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) "config error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static int twl4030_config_sleep_sequence(u8 address)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) /* Set ACTIVE to SLEEP SEQ address in T2 memory*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, address, R_SEQ_ADD_A2S);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) pr_err("TWL4030 sleep sequence config error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) static int twl4030_config_warmreset_sequence(u8 address)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) u8 rd_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) /* Set WARM RESET SEQ address for P1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, address, R_SEQ_ADD_WARM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) /* P1/P2/P3 enable WARMRESET */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) err = twl_i2c_read_u8(TWL_MODULE_PM_MASTER, &rd_data, R_P1_SW_EVENTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) rd_data |= PWR_ENABLE_WARMRESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, rd_data, R_P1_SW_EVENTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) err = twl_i2c_read_u8(TWL_MODULE_PM_MASTER, &rd_data, R_P2_SW_EVENTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) rd_data |= PWR_ENABLE_WARMRESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, rd_data, R_P2_SW_EVENTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) err = twl_i2c_read_u8(TWL_MODULE_PM_MASTER, &rd_data, R_P3_SW_EVENTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) rd_data |= PWR_ENABLE_WARMRESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, rd_data, R_P3_SW_EVENTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) pr_err("TWL4030 warmreset seq config error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) static int twl4030_configure_resource(struct twl4030_resconfig *rconfig)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) int rconfig_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) u8 type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) u8 grp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) u8 remap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) if (rconfig->resource > TOTAL_RESOURCES) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) pr_err("TWL4030 Resource %d does not exist\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) rconfig->resource);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) rconfig_addr = res_config_addrs[rconfig->resource];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) /* Set resource group */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) err = twl_i2c_read_u8(TWL_MODULE_PM_RECEIVER, &grp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) rconfig_addr + DEV_GRP_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) pr_err("TWL4030 Resource %d group could not be read\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) rconfig->resource);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) if (rconfig->devgroup != TWL4030_RESCONFIG_UNDEF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) grp &= ~DEV_GRP_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) grp |= rconfig->devgroup << DEV_GRP_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) err = twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) grp, rconfig_addr + DEV_GRP_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) pr_err("TWL4030 failed to program devgroup\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) /* Set resource types */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) err = twl_i2c_read_u8(TWL_MODULE_PM_RECEIVER, &type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) rconfig_addr + TYPE_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) pr_err("TWL4030 Resource %d type could not be read\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) rconfig->resource);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if (rconfig->type != TWL4030_RESCONFIG_UNDEF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) type &= ~TYPE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) type |= rconfig->type << TYPE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) if (rconfig->type2 != TWL4030_RESCONFIG_UNDEF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) type &= ~TYPE2_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) type |= rconfig->type2 << TYPE2_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) err = twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) type, rconfig_addr + TYPE_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) pr_err("TWL4030 failed to program resource type\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) /* Set remap states */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) err = twl_i2c_read_u8(TWL_MODULE_PM_RECEIVER, &remap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) rconfig_addr + REMAP_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) pr_err("TWL4030 Resource %d remap could not be read\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) rconfig->resource);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) if (rconfig->remap_off != TWL4030_RESCONFIG_UNDEF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) remap &= ~OFF_STATE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) remap |= rconfig->remap_off << OFF_STATE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) if (rconfig->remap_sleep != TWL4030_RESCONFIG_UNDEF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) remap &= ~SLEEP_STATE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) remap |= rconfig->remap_sleep << SLEEP_STATE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) err = twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) remap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) rconfig_addr + REMAP_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) pr_err("TWL4030 failed to program remap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) static int load_twl4030_script(const struct twl4030_power_data *pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) struct twl4030_script *tscript,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) u8 address)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) static int order;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) /* Make sure the script isn't going beyond last valid address (0x3f) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) if ((address + tscript->size) > END_OF_SCRIPT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) pr_err("TWL4030 scripts too big error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) err = twl4030_write_script(address, tscript->script, tscript->size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) if (tscript->flags & TWL4030_WRST_SCRIPT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) err = twl4030_config_warmreset_sequence(address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) if (tscript->flags & TWL4030_WAKEUP12_SCRIPT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) /* Reset any existing sleep script to avoid hangs on reboot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, END_OF_SCRIPT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) R_SEQ_ADD_A2S);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) err = twl4030_config_wakeup12_sequence(pdata, address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) order = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) if (tscript->flags & TWL4030_WAKEUP3_SCRIPT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) err = twl4030_config_wakeup3_sequence(address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) if (tscript->flags & TWL4030_SLEEP_SCRIPT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) if (!order)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) pr_warn("TWL4030: Bad order of scripts (sleep script before wakeup) Leads to boot failure on some boards\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) err = twl4030_config_sleep_sequence(address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) int twl4030_remove_script(u8 flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, TWL4030_PM_MASTER_KEY_CFG1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) TWL4030_PM_MASTER_PROTECT_KEY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) pr_err("twl4030: unable to unlock PROTECT_KEY\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, TWL4030_PM_MASTER_KEY_CFG2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) TWL4030_PM_MASTER_PROTECT_KEY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) pr_err("twl4030: unable to unlock PROTECT_KEY\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) if (flags & TWL4030_WRST_SCRIPT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, END_OF_SCRIPT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) R_SEQ_ADD_WARM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) if (flags & TWL4030_WAKEUP12_SCRIPT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, END_OF_SCRIPT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) R_SEQ_ADD_S2A12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) if (flags & TWL4030_WAKEUP3_SCRIPT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, END_OF_SCRIPT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) R_SEQ_ADD_S2A3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) if (flags & TWL4030_SLEEP_SCRIPT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, END_OF_SCRIPT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) R_SEQ_ADD_A2S);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) TWL4030_PM_MASTER_PROTECT_KEY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) pr_err("TWL4030 Unable to relock registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) twl4030_power_configure_scripts(const struct twl4030_power_data *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) u8 address = twl4030_start_script_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) for (i = 0; i < pdata->num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) err = load_twl4030_script(pdata, pdata->scripts[i], address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) address += pdata->scripts[i]->size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) static void twl4030_patch_rconfig(struct twl4030_resconfig *common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) struct twl4030_resconfig *board)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) while (common->resource) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) struct twl4030_resconfig *b = board;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) while (b->resource) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) if (b->resource == common->resource) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) *common = *b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) b++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) common++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) twl4030_power_configure_resources(const struct twl4030_power_data *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) struct twl4030_resconfig *resconfig = pdata->resource_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) struct twl4030_resconfig *boardconf = pdata->board_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) if (resconfig) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) if (boardconf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) twl4030_patch_rconfig(resconfig, boardconf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) while (resconfig->resource) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) err = twl4030_configure_resource(resconfig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) resconfig++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) static int twl4030_starton_mask_and_set(u8 bitmask, u8 bitvalues)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) u8 regs[3] = { TWL4030_PM_MASTER_CFG_P1_TRANSITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) TWL4030_PM_MASTER_CFG_P2_TRANSITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) TWL4030_PM_MASTER_CFG_P3_TRANSITION, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) int i, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, TWL4030_PM_MASTER_KEY_CFG1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) TWL4030_PM_MASTER_PROTECT_KEY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) goto relock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) TWL4030_PM_MASTER_KEY_CFG2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) TWL4030_PM_MASTER_PROTECT_KEY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) goto relock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) for (i = 0; i < sizeof(regs); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) err = twl_i2c_read_u8(TWL_MODULE_PM_MASTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) &val, regs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) val = (~bitmask & val) | (bitmask & bitvalues);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) val, regs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) pr_err("TWL4030 Register access failed: %i\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) relock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) return twl_i2c_write_u8(TWL_MODULE_PM_MASTER, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) TWL4030_PM_MASTER_PROTECT_KEY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) * In master mode, start the power off sequence.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) * After a successful execution, TWL shuts down the power to the SoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) * and all peripherals connected to it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) void twl4030_power_off(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) /* Disable start on charger or VBUS as it can break poweroff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) err = twl4030_starton_mask_and_set(STARTON_VBUS | STARTON_CHG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) pr_err("TWL4030 Unable to configure start-up\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, PWR_DEVOFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) TWL4030_PM_MASTER_P1_SW_EVENTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) pr_err("TWL4030 Unable to power off\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) static bool twl4030_power_use_poweroff(const struct twl4030_power_data *pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) if (pdata && pdata->use_poweroff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) if (of_property_read_bool(node, "ti,system-power-controller"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) if (of_property_read_bool(node, "ti,use_poweroff"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) /* Generic warm reset configuration for omap3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) static struct twl4030_ins omap3_wrst_seq[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) TWL_RESOURCE_OFF(RES_NRES_PWRON),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) TWL_RESOURCE_OFF(RES_RESET),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) TWL_RESOURCE_RESET(RES_MAIN_REF),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) TWL_RESOURCE_GROUP_RESET(RES_GRP_ALL, RES_TYPE_R0, RES_TYPE2_R2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) TWL_RESOURCE_RESET(RES_VUSB_3V1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) TWL_RESOURCE_RESET(RES_VMMC1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) TWL_RESOURCE_GROUP_RESET(RES_GRP_ALL, RES_TYPE_R0, RES_TYPE2_R1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) TWL_RESOURCE_GROUP_RESET(RES_GRP_RC, RES_TYPE_ALL, RES_TYPE2_R0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) TWL_RESOURCE_ON(RES_RESET),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) TWL_RESOURCE_ON(RES_NRES_PWRON),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) static struct twl4030_script omap3_wrst_script = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) .script = omap3_wrst_seq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) .size = ARRAY_SIZE(omap3_wrst_seq),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) .flags = TWL4030_WRST_SCRIPT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) static struct twl4030_script *omap3_reset_scripts[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) &omap3_wrst_script,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) static struct twl4030_resconfig omap3_rconfig[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) TWL_REMAP_SLEEP(RES_HFCLKOUT, DEV_GRP_P3, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) TWL_REMAP_SLEEP(RES_VDD1, DEV_GRP_P1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) TWL_REMAP_SLEEP(RES_VDD2, DEV_GRP_P1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) { 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) static struct twl4030_power_data omap3_reset = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) .scripts = omap3_reset_scripts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) .num = ARRAY_SIZE(omap3_reset_scripts),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) .resource_config = omap3_rconfig,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) /* Recommended generic default idle configuration for off-idle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) /* Broadcast message to put res to sleep */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) static struct twl4030_ins omap3_idle_sleep_on_seq[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) TWL_RESOURCE_GROUP_SLEEP(RES_GRP_ALL, RES_TYPE_ALL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) static struct twl4030_script omap3_idle_sleep_on_script = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) .script = omap3_idle_sleep_on_seq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) .size = ARRAY_SIZE(omap3_idle_sleep_on_seq),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) .flags = TWL4030_SLEEP_SCRIPT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) /* Broadcast message to put res to active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) static struct twl4030_ins omap3_idle_wakeup_p12_seq[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) TWL_RESOURCE_GROUP_ACTIVE(RES_GRP_ALL, RES_TYPE_ALL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) static struct twl4030_script omap3_idle_wakeup_p12_script = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) .script = omap3_idle_wakeup_p12_seq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) .size = ARRAY_SIZE(omap3_idle_wakeup_p12_seq),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) .flags = TWL4030_WAKEUP12_SCRIPT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) /* Broadcast message to put res to active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) static struct twl4030_ins omap3_idle_wakeup_p3_seq[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) TWL_RESOURCE_SET_ACTIVE(RES_CLKEN, 0x37),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) TWL_RESOURCE_GROUP_ACTIVE(RES_GRP_ALL, RES_TYPE_ALL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) static struct twl4030_script omap3_idle_wakeup_p3_script = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) .script = omap3_idle_wakeup_p3_seq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) .size = ARRAY_SIZE(omap3_idle_wakeup_p3_seq),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) .flags = TWL4030_WAKEUP3_SCRIPT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) static struct twl4030_script *omap3_idle_scripts[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) &omap3_idle_wakeup_p12_script,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) &omap3_idle_wakeup_p3_script,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) &omap3_wrst_script,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) &omap3_idle_sleep_on_script,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) * Recommended configuration based on "Recommended Sleep
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) * Sequences for the Zoom Platform":
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) * http://omappedia.com/wiki/File:Recommended_Sleep_Sequences_Zoom.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) * Note that the type1 and type2 seem to be just the init order number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) * for type1 and type2 groups as specified in the document mentioned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) * above.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) static struct twl4030_resconfig omap3_idle_rconfig[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) TWL_REMAP_SLEEP(RES_VAUX1, TWL4030_RESCONFIG_UNDEF, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) TWL_REMAP_SLEEP(RES_VAUX2, TWL4030_RESCONFIG_UNDEF, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) TWL_REMAP_SLEEP(RES_VAUX3, TWL4030_RESCONFIG_UNDEF, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) TWL_REMAP_SLEEP(RES_VAUX4, TWL4030_RESCONFIG_UNDEF, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) TWL_REMAP_SLEEP(RES_VMMC1, TWL4030_RESCONFIG_UNDEF, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) TWL_REMAP_SLEEP(RES_VMMC2, TWL4030_RESCONFIG_UNDEF, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) TWL_REMAP_OFF(RES_VPLL1, DEV_GRP_P1, 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) TWL_REMAP_SLEEP(RES_VPLL2, DEV_GRP_P1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) TWL_REMAP_SLEEP(RES_VSIM, TWL4030_RESCONFIG_UNDEF, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) TWL_REMAP_SLEEP(RES_VDAC, TWL4030_RESCONFIG_UNDEF, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) TWL_REMAP_SLEEP(RES_VINTANA1, TWL_DEV_GRP_P123, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) TWL_REMAP_SLEEP(RES_VINTANA2, TWL_DEV_GRP_P123, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) TWL_REMAP_SLEEP(RES_VINTDIG, TWL_DEV_GRP_P123, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) TWL_REMAP_SLEEP(RES_VIO, TWL_DEV_GRP_P123, 2, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) TWL_REMAP_OFF(RES_VDD1, DEV_GRP_P1, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) TWL_REMAP_OFF(RES_VDD2, DEV_GRP_P1, 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) TWL_REMAP_SLEEP(RES_VUSB_1V5, TWL4030_RESCONFIG_UNDEF, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) TWL_REMAP_SLEEP(RES_VUSB_1V8, TWL4030_RESCONFIG_UNDEF, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) TWL_REMAP_SLEEP(RES_VUSB_3V1, TWL_DEV_GRP_P123, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) /* Resource #20 USB charge pump skipped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) TWL_REMAP_SLEEP(RES_REGEN, TWL_DEV_GRP_P123, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) TWL_REMAP_SLEEP(RES_NRES_PWRON, TWL_DEV_GRP_P123, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) TWL_REMAP_SLEEP(RES_CLKEN, TWL_DEV_GRP_P123, 3, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) TWL_REMAP_SLEEP(RES_SYSEN, TWL_DEV_GRP_P123, 6, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) TWL_REMAP_SLEEP(RES_HFCLKOUT, DEV_GRP_P3, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) TWL_REMAP_SLEEP(RES_32KCLKOUT, TWL_DEV_GRP_P123, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) TWL_REMAP_SLEEP(RES_RESET, TWL_DEV_GRP_P123, 6, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) TWL_REMAP_SLEEP(RES_MAIN_REF, TWL_DEV_GRP_P123, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) { /* Terminator */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) static struct twl4030_power_data omap3_idle = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) .scripts = omap3_idle_scripts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) .num = ARRAY_SIZE(omap3_idle_scripts),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) .resource_config = omap3_idle_rconfig,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) /* Disable 32 KiHz oscillator during idle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) static struct twl4030_resconfig osc_off_rconfig[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) TWL_REMAP_OFF(RES_CLKEN, DEV_GRP_P1 | DEV_GRP_P3, 3, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) { /* Terminator */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) static struct twl4030_power_data osc_off_idle = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) .scripts = omap3_idle_scripts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) .num = ARRAY_SIZE(omap3_idle_scripts),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) .resource_config = omap3_idle_rconfig,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) .board_config = osc_off_rconfig,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) static struct twl4030_power_data omap3_idle_ac_quirk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) .scripts = omap3_idle_scripts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) .num = ARRAY_SIZE(omap3_idle_scripts),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) .resource_config = omap3_idle_rconfig,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) .ac_charger_quirk = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) static struct twl4030_power_data omap3_idle_ac_quirk_osc_off = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) .scripts = omap3_idle_scripts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) .num = ARRAY_SIZE(omap3_idle_scripts),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) .resource_config = omap3_idle_rconfig,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) .board_config = osc_off_rconfig,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) .ac_charger_quirk = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) static const struct of_device_id twl4030_power_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) .compatible = "ti,twl4030-power",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) .compatible = "ti,twl4030-power-reset",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) .data = &omap3_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) .compatible = "ti,twl4030-power-idle",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) .data = &omap3_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) .compatible = "ti,twl4030-power-idle-osc-off",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) .data = &osc_off_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) .compatible = "ti,twl4030-power-omap3-sdp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) .data = &omap3_idle_ac_quirk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) .compatible = "ti,twl4030-power-omap3-ldp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) .data = &omap3_idle_ac_quirk_osc_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) .compatible = "ti,twl4030-power-omap3-evm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) .data = &omap3_idle_ac_quirk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) MODULE_DEVICE_TABLE(of, twl4030_power_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) #endif /* CONFIG_OF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) static int twl4030_power_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) const struct twl4030_power_data *pdata = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) struct device_node *node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) int err2 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) if (!pdata && !node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) dev_err(&pdev->dev, "Platform data is missing\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, TWL4030_PM_MASTER_KEY_CFG1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) TWL4030_PM_MASTER_PROTECT_KEY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) err |= twl_i2c_write_u8(TWL_MODULE_PM_MASTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) TWL4030_PM_MASTER_KEY_CFG2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) TWL4030_PM_MASTER_PROTECT_KEY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) pr_err("TWL4030 Unable to unlock registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) match = of_match_device(of_match_ptr(twl4030_power_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) if (match && match->data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) pdata = match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) if (pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) err = twl4030_power_configure_scripts(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) pr_err("TWL4030 failed to load scripts\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) goto relock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) err = twl4030_power_configure_resources(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) pr_err("TWL4030 failed to configure resource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) goto relock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) /* Board has to be wired properly to use this feature */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) if (twl4030_power_use_poweroff(pdata, node) && !pm_power_off) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) /* Default for SEQ_OFFSYNC is set, lets ensure this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) err = twl_i2c_read_u8(TWL_MODULE_PM_MASTER, &val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) TWL4030_PM_MASTER_CFG_P123_TRANSITION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) pr_warn("TWL4030 Unable to read registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) } else if (!(val & SEQ_OFFSYNC)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) val |= SEQ_OFFSYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) TWL4030_PM_MASTER_CFG_P123_TRANSITION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) pr_err("TWL4030 Unable to setup SEQ_OFFSYNC\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) goto relock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) pm_power_off = twl4030_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) relock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) err2 = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) TWL4030_PM_MASTER_PROTECT_KEY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) if (err2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) pr_err("TWL4030 Unable to relock registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) return err2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) static int twl4030_power_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) static struct platform_driver twl4030_power_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) .name = "twl4030_power",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) .of_match_table = of_match_ptr(twl4030_power_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) .probe = twl4030_power_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) .remove = twl4030_power_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) module_platform_driver(twl4030_power_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) MODULE_AUTHOR("Nokia Corporation");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) MODULE_AUTHOR("Texas Instruments, Inc.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) MODULE_DESCRIPTION("Power management for TWL4030");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) MODULE_ALIAS("platform:twl4030_power");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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