^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * twl4030-irq.c - TWL4030/TPS659x0 irq support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2005-2006 Texas Instruments, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Modifications to defer interrupt handling to a kernel thread:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 2006 MontaVista Software, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Based on tlv320aic23.c:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Copyright (c) by Kai Svahn <kai.svahn@nokia.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Code cleanup and modifications to IRQ handler.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * by syed khasim <x0khasim@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/mfd/twl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "twl-core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * TWL4030 IRQ handling has two stages in hardware, and thus in software.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * The Primary Interrupt Handler (PIH) stage exposes status bits saying
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * which Secondary Interrupt Handler (SIH) stage is raising an interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * SIH modules are more traditional IRQ components, which support per-IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * enable/disable and trigger controls; they do most of the work.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * These chips are designed to support IRQ handling from two different
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * I2C masters. Each has a dedicated IRQ line, and dedicated IRQ status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * and mask registers in the PIH and SIH modules.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * We set up IRQs starting at a platform-specified base, always starting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * with PIH and the SIH for PWR_INT and then usually adding GPIO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * base + 0 .. base + 7 PIH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * base + 8 .. base + 15 SIH for PWR_INT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * base + 16 .. base + 33 SIH for GPIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define TWL4030_CORE_NR_IRQS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define TWL4030_PWR_NR_IRQS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* PIH register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define REG_PIH_ISR_P1 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define REG_PIH_ISR_P2 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define REG_PIH_SIR 0x03 /* for testing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* Linux could (eventually) use either IRQ line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static int irq_line;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct sih {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) char name[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) u8 module; /* module id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) u8 control_offset; /* for SIH_CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) bool set_cor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) u8 bits; /* valid in isr/imr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) u8 bytes_ixr; /* bytelen of ISR/IMR/SIR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) u8 edr_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) u8 bytes_edr; /* bytelen of EDR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) u8 irq_lines; /* number of supported irq lines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* SIR ignored -- set interrupt, for testing only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct sih_irq_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) u8 isr_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) u8 imr_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) } mask[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* + 2 bytes padding */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static const struct sih *sih_modules;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static int nr_sih_modules;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define SIH_INITIALIZER(modname, nbits) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .module = TWL4030_MODULE_ ## modname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .control_offset = TWL4030_ ## modname ## _SIH_CTRL, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .bits = nbits, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .bytes_ixr = DIV_ROUND_UP(nbits, 8), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .edr_offset = TWL4030_ ## modname ## _EDR, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .bytes_edr = DIV_ROUND_UP((2*(nbits)), 8), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .irq_lines = 2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .mask = { { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .isr_offset = TWL4030_ ## modname ## _ISR1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .imr_offset = TWL4030_ ## modname ## _IMR1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .isr_offset = TWL4030_ ## modname ## _ISR2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .imr_offset = TWL4030_ ## modname ## _IMR2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* register naming policies are inconsistent ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define TWL4030_INT_PWR_EDR TWL4030_INT_PWR_EDR1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define TWL4030_MODULE_KEYPAD_KEYP TWL4030_MODULE_KEYPAD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define TWL4030_MODULE_INT_PWR TWL4030_MODULE_INT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * Order in this table matches order in PIH_ISR. That is,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * BIT(n) in PIH_ISR is sih_modules[n].
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* sih_modules_twl4030 is used both in twl4030 and twl5030 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static const struct sih sih_modules_twl4030[6] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .name = "gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .module = TWL4030_MODULE_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .control_offset = REG_GPIO_SIH_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .set_cor = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .bits = TWL4030_GPIO_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .bytes_ixr = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* Note: *all* of these IRQs default to no-trigger */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .edr_offset = REG_GPIO_EDR1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .bytes_edr = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .irq_lines = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .mask = { {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .isr_offset = REG_GPIO_ISR1A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .imr_offset = REG_GPIO_IMR1A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .isr_offset = REG_GPIO_ISR1B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .imr_offset = REG_GPIO_IMR1B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) [1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .name = "keypad",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .set_cor = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) SIH_INITIALIZER(KEYPAD_KEYP, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) [2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .name = "bci",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .module = TWL4030_MODULE_INTERRUPTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .control_offset = TWL4030_INTERRUPTS_BCISIHCTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .set_cor = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .bits = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .bytes_ixr = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .edr_offset = TWL4030_INTERRUPTS_BCIEDR1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* Note: most of these IRQs default to no-trigger */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .bytes_edr = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .irq_lines = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .mask = { {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .isr_offset = TWL4030_INTERRUPTS_BCIISR1A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .imr_offset = TWL4030_INTERRUPTS_BCIIMR1A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .isr_offset = TWL4030_INTERRUPTS_BCIISR1B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .imr_offset = TWL4030_INTERRUPTS_BCIIMR1B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) [3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .name = "madc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) SIH_INITIALIZER(MADC, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) [4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* USB doesn't use the same SIH organization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .name = "usb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) [5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .name = "power",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .set_cor = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) SIH_INITIALIZER(INT_PWR, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* there are no SIH modules #6 or #7 ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static const struct sih sih_modules_twl5031[8] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .name = "gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .module = TWL4030_MODULE_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .control_offset = REG_GPIO_SIH_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .set_cor = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .bits = TWL4030_GPIO_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .bytes_ixr = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /* Note: *all* of these IRQs default to no-trigger */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .edr_offset = REG_GPIO_EDR1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .bytes_edr = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .irq_lines = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .mask = { {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .isr_offset = REG_GPIO_ISR1A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .imr_offset = REG_GPIO_IMR1A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .isr_offset = REG_GPIO_ISR1B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .imr_offset = REG_GPIO_IMR1B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) [1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .name = "keypad",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .set_cor = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) SIH_INITIALIZER(KEYPAD_KEYP, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) [2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .name = "bci",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .module = TWL5031_MODULE_INTERRUPTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .control_offset = TWL5031_INTERRUPTS_BCISIHCTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .bits = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .bytes_ixr = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .edr_offset = TWL5031_INTERRUPTS_BCIEDR1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /* Note: most of these IRQs default to no-trigger */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .bytes_edr = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .irq_lines = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .mask = { {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .isr_offset = TWL5031_INTERRUPTS_BCIISR1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .imr_offset = TWL5031_INTERRUPTS_BCIIMR1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .isr_offset = TWL5031_INTERRUPTS_BCIISR2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .imr_offset = TWL5031_INTERRUPTS_BCIIMR2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) [3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .name = "madc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) SIH_INITIALIZER(MADC, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) [4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /* USB doesn't use the same SIH organization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .name = "usb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) [5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .name = "power",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .set_cor = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) SIH_INITIALIZER(INT_PWR, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) [6] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * ECI/DBI doesn't use the same SIH organization.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * For example, it supports only one interrupt output line.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * That is, the interrupts are seen on both INT1 and INT2 lines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .name = "eci_dbi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .module = TWL5031_MODULE_ACCESSORY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .bits = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .bytes_ixr = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .irq_lines = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .mask = { {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .isr_offset = TWL5031_ACIIDR_LSB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .imr_offset = TWL5031_ACIIMR_LSB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) [7] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /* Audio accessory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .name = "audio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .module = TWL5031_MODULE_ACCESSORY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .control_offset = TWL5031_ACCSIHCTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) .bits = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .bytes_ixr = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .edr_offset = TWL5031_ACCEDR1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /* Note: most of these IRQs default to no-trigger */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .bytes_edr = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .irq_lines = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .mask = { {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .isr_offset = TWL5031_ACCISR1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .imr_offset = TWL5031_ACCIMR1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .isr_offset = TWL5031_ACCISR2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .imr_offset = TWL5031_ACCIMR2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #undef TWL4030_MODULE_KEYPAD_KEYP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #undef TWL4030_MODULE_INT_PWR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #undef TWL4030_INT_PWR_EDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /*----------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static unsigned twl4030_irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) * handle_twl4030_pih() is the desc->handle method for the twl4030 interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * This is a chained interrupt, so there is no desc->action method for it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) * Now we need to query the interrupt controller in the twl4030 to determine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) * which module is generating the interrupt request. However, we can't do i2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) * transactions in interrupt context, so we must defer that work to a kernel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) * thread. All we do here is acknowledge and mask the interrupt and wakeup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) * the kernel thread.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static irqreturn_t handle_twl4030_pih(int irq, void *devid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) irqreturn_t ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) u8 pih_isr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) ret = twl_i2c_read_u8(TWL_MODULE_PIH, &pih_isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) REG_PIH_ISR_P1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) pr_warn("twl4030: I2C error %d reading PIH ISR\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) while (pih_isr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) unsigned long pending = __ffs(pih_isr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) unsigned int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) pih_isr &= ~BIT(pending);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) irq = pending + twl4030_irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) handle_nested_irq(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /*----------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) * twl4030_init_sih_modules() ... start from a known state where no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) * IRQs will be coming in, and where we can quickly enable them then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) * handle them as they arrive. Mask all IRQs: maybe init SIH_CTRL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) * NOTE: we don't touch EDR registers here; they stay with hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) * defaults or whatever the last value was. Note that when both EDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) * bits for an IRQ are clear, that's as if its IMR bit is set...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static int twl4030_init_sih_modules(unsigned line)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) const struct sih *sih;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) u8 buf[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) /* line 0 == int1_n signal; line 1 == int2_n signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) if (line > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) irq_line = line;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) /* disable all interrupts on our line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) memset(buf, 0xff, sizeof(buf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) sih = sih_modules;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) for (i = 0; i < nr_sih_modules; i++, sih++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) /* skip USB -- it's funky */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) if (!sih->bytes_ixr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /* Not all the SIH modules support multiple interrupt lines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) if (sih->irq_lines <= line)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) status = twl_i2c_write(sih->module, buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) sih->mask[line].imr_offset, sih->bytes_ixr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) pr_err("twl4030: err %d initializing %s %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) status, sih->name, "IMR");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) * Maybe disable "exclusive" mode; buffer second pending irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) * set Clear-On-Read (COR) bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) * NOTE that sometimes COR polarity is documented as being
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) * inverted: for MADC, COR=1 means "clear on write".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) * And for PWR_INT it's not documented...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) if (sih->set_cor) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) status = twl_i2c_write_u8(sih->module,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) TWL4030_SIH_CTRL_COR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) sih->control_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) pr_err("twl4030: err %d initializing %s %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) status, sih->name, "SIH_CTRL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) sih = sih_modules;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) for (i = 0; i < nr_sih_modules; i++, sih++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) u8 rxbuf[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) int j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) /* skip USB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) if (!sih->bytes_ixr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) /* Not all the SIH modules support multiple interrupt lines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) if (sih->irq_lines <= line)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) * Clear pending interrupt status. Either the read was
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) * enough, or we need to write those bits. Repeat, in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) * case an IRQ is pending (PENDDIS=0) ... that's not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) * uncommon with PWR_INT.PWRON.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) for (j = 0; j < 2; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) status = twl_i2c_read(sih->module, rxbuf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) sih->mask[line].isr_offset, sih->bytes_ixr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) pr_warn("twl4030: err %d initializing %s %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) status, sih->name, "ISR");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (!sih->set_cor) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) status = twl_i2c_write(sih->module, buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) sih->mask[line].isr_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) sih->bytes_ixr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) pr_warn("twl4030: write failed: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) * else COR=1 means read sufficed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) * (for most SIH modules...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) static inline void activate_irq(int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) /*----------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) struct sih_agent {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) int irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) const struct sih *sih;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) u32 imr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) bool imr_change_pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) u32 edge_change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) struct mutex irq_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) char *irq_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) /*----------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) * All irq_chip methods get issued from code holding irq_desc[irq].lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) * which can't perform the underlying I2C operations (because they sleep).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) * So we must hand them off to a thread (workqueue) and cope with asynch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) * completion, potentially including some re-ordering, of these requests.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) static void twl4030_sih_mask(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) struct sih_agent *agent = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) agent->imr |= BIT(data->irq - agent->irq_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) agent->imr_change_pending = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) static void twl4030_sih_unmask(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) struct sih_agent *agent = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) agent->imr &= ~BIT(data->irq - agent->irq_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) agent->imr_change_pending = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) static int twl4030_sih_set_type(struct irq_data *data, unsigned trigger)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) struct sih_agent *agent = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) if (irqd_get_trigger_type(data) != trigger)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) agent->edge_change |= BIT(data->irq - agent->irq_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) static void twl4030_sih_bus_lock(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) struct sih_agent *agent = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) mutex_lock(&agent->irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) static void twl4030_sih_bus_sync_unlock(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) struct sih_agent *agent = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) const struct sih *sih = agent->sih;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) if (agent->imr_change_pending) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) __le32 word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) u8 bytes[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) } imr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) /* byte[0] gets overwritten as we write ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) imr.word = cpu_to_le32(agent->imr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) agent->imr_change_pending = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) /* write the whole mask ... simpler than subsetting it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) status = twl_i2c_write(sih->module, imr.bytes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) sih->mask[irq_line].imr_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) sih->bytes_ixr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) pr_err("twl4030: %s, %s --> %d\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) "write", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) if (agent->edge_change) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) u32 edge_change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) u8 bytes[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) edge_change = agent->edge_change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) agent->edge_change = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) * Read, reserving first byte for write scratch. Yes, this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) * could be cached for some speedup ... but be careful about
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) * any processor on the other IRQ line, EDR registers are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) * shared.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) status = twl_i2c_read(sih->module, bytes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) sih->edr_offset, sih->bytes_edr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) if (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) pr_err("twl4030: %s, %s --> %d\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) "read", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) /* Modify only the bits we know must change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) while (edge_change) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) int i = fls(edge_change) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) int byte = i >> 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) int off = (i & 0x3) * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) unsigned int type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) bytes[byte] &= ~(0x03 << off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) type = irq_get_trigger_type(i + agent->irq_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) if (type & IRQ_TYPE_EDGE_RISING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) bytes[byte] |= BIT(off + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) if (type & IRQ_TYPE_EDGE_FALLING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) bytes[byte] |= BIT(off + 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) edge_change &= ~BIT(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) /* Write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) status = twl_i2c_write(sih->module, bytes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) sih->edr_offset, sih->bytes_edr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) pr_err("twl4030: %s, %s --> %d\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) "write", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) mutex_unlock(&agent->irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) static struct irq_chip twl4030_sih_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) .name = "twl4030",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) .irq_mask = twl4030_sih_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) .irq_unmask = twl4030_sih_unmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) .irq_set_type = twl4030_sih_set_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) .irq_bus_lock = twl4030_sih_bus_lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) .irq_bus_sync_unlock = twl4030_sih_bus_sync_unlock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) .flags = IRQCHIP_SKIP_SET_WAKE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) /*----------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) static inline int sih_read_isr(const struct sih *sih)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) u8 bytes[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) __le32 word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) } isr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) /* FIXME need retry-on-error ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) isr.word = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) status = twl_i2c_read(sih->module, isr.bytes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) sih->mask[irq_line].isr_offset, sih->bytes_ixr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) return (status < 0) ? status : le32_to_cpu(isr.word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) * Generic handler for SIH interrupts ... we "know" this is called
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) * in task context, with IRQs enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) static irqreturn_t handle_twl4030_sih(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) struct sih_agent *agent = irq_get_handler_data(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) const struct sih *sih = agent->sih;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) int isr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) /* reading ISR acks the IRQs, using clear-on-read mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) isr = sih_read_isr(sih);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) if (isr < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) pr_err("twl4030: %s SIH, read ISR error %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) sih->name, isr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) /* REVISIT: recover; eventually mask it all, etc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) while (isr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) irq = fls(isr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) irq--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) isr &= ~BIT(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) if (irq < sih->bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) handle_nested_irq(agent->irq_base + irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) pr_err("twl4030: %s SIH, invalid ISR bit %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) sih->name, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) /* returns the first IRQ used by this SIH bank, or negative errno */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) int twl4030_sih_setup(struct device *dev, int module, int irq_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) int sih_mod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) const struct sih *sih = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) struct sih_agent *agent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) int i, irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) int status = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) /* only support modules with standard clear-on-read for now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) for (sih_mod = 0, sih = sih_modules; sih_mod < nr_sih_modules;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) sih_mod++, sih++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) if (sih->module == module && sih->set_cor) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) if (status < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) dev_err(dev, "module to setup SIH for not found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) agent = kzalloc(sizeof(*agent), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) if (!agent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) agent->irq_base = irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) agent->sih = sih;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) agent->imr = ~0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) mutex_init(&agent->irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) for (i = 0; i < sih->bits; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) irq = irq_base + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) irq_set_chip_data(irq, agent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) irq_set_chip_and_handler(irq, &twl4030_sih_irq_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) handle_edge_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) irq_set_nested_thread(irq, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) activate_irq(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) /* replace generic PIH handler (handle_simple_irq) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) irq = sih_mod + twl4030_irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) irq_set_handler_data(irq, agent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) agent->irq_name = kasprintf(GFP_KERNEL, "twl4030_%s", sih->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) status = request_threaded_irq(irq, NULL, handle_twl4030_sih,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) IRQF_EARLY_RESUME | IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) agent->irq_name ?: sih->name, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) dev_info(dev, "%s (irq %d) chaining IRQs %d..%d\n", sih->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) irq, irq_base, irq_base + i - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) return status < 0 ? status : irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) /* FIXME need a call to reverse twl4030_sih_setup() ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) /*----------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) /* FIXME pass in which interrupt line we'll use ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) #define twl_irq_line 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) int twl4030_init_irq(struct device *dev, int irq_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) static struct irq_chip twl4030_irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) int status, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) int irq_base, irq_end, nr_irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) * TWL core and pwr interrupts must be contiguous because
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) * the hwirqs numbers are defined contiguously from 1 to 15.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) * Create only one domain for both.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) nr_irqs = TWL4030_PWR_NR_IRQS + TWL4030_CORE_NR_IRQS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) irq_base = irq_alloc_descs(-1, 0, nr_irqs, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) if (irq_base < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) dev_err(dev, "Fail to allocate IRQ descs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) return irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) irq_domain_add_legacy(node, nr_irqs, irq_base, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) &irq_domain_simple_ops, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) irq_end = irq_base + TWL4030_CORE_NR_IRQS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) * Mask and clear all TWL4030 interrupts since initially we do
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) * not have any TWL4030 module interrupt handlers present
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) status = twl4030_init_sih_modules(twl_irq_line);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) twl4030_irq_base = irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) * Install an irq handler for each of the SIH modules;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) * clone dummy irq_chip since PIH can't *do* anything
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) twl4030_irq_chip = dummy_irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) twl4030_irq_chip.name = "twl4030";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) twl4030_sih_irq_chip.irq_ack = dummy_irq_chip.irq_ack;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) for (i = irq_base; i < irq_end; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) irq_set_chip_and_handler(i, &twl4030_irq_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) handle_simple_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) irq_set_nested_thread(i, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) activate_irq(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) dev_info(dev, "%s (irq %d) chaining IRQs %d..%d\n", "PIH",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) irq_num, irq_base, irq_end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) /* ... and the PWR_INT module ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) status = twl4030_sih_setup(dev, TWL4030_MODULE_INT, irq_end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) if (status < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) dev_err(dev, "sih_setup PWR INT --> %d\n", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) /* install an irq handler to demultiplex the TWL4030 interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) status = request_threaded_irq(irq_num, NULL, handle_twl4030_pih,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) "TWL4030-PIH", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) if (status < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) dev_err(dev, "could not claim irq%d: %d\n", irq_num, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) goto fail_rqirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) enable_irq_wake(irq_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) return irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) fail_rqirq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) /* clean up twl4030_sih_setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) for (i = irq_base; i < irq_end; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) irq_set_nested_thread(i, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) irq_set_chip_and_handler(i, NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) int twl4030_exit_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) /* FIXME undo twl_init_irq() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) if (twl4030_irq_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) pr_err("twl4030: can't yet clean up IRQs?\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) return -ENOSYS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) int twl4030_init_chip_irq(const char *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) if (!strcmp(chip, "twl5031")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) sih_modules = sih_modules_twl5031;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) nr_sih_modules = ARRAY_SIZE(sih_modules_twl5031);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) sih_modules = sih_modules_twl4030;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) nr_sih_modules = ARRAY_SIZE(sih_modules_twl4030);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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