^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * tps80031.c -- TI TPS80031/TPS80032 mfd core driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * MFD core driver for TI TPS80031/TPS80032 Fully Integrated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Power Management with Power Path and Battery Charger
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (c) 2012, NVIDIA Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Author: Laxman Dewangan <ldewangan@nvidia.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * This program is free software; you can redistribute it and/or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * modify it under the terms of the GNU General Public License as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * published by the Free Software Foundation version 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * This program is distributed "as is" WITHOUT ANY WARRANTY of any kind,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * whether express or implied; without even the implied warranty of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * You should have received a copy of the GNU General Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * along with this program; if not, write to the Free Software
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * 02111-1307, USA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/mfd/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/mfd/tps80031.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static struct resource tps80031_rtc_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) .start = TPS80031_INT_RTC_ALARM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) .end = TPS80031_INT_RTC_ALARM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* TPS80031 sub mfd devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static const struct mfd_cell tps80031_cell[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) .name = "tps80031-pmic",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .name = "tps80031-clock",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .name = "tps80031-rtc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) .num_resources = ARRAY_SIZE(tps80031_rtc_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) .resources = tps80031_rtc_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .name = "tps80031-gpadc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .name = "tps80031-fuel-gauge",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .name = "tps80031-charger",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static int tps80031_slave_address[TPS80031_NUM_SLAVES] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) TPS80031_I2C_ID0_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) TPS80031_I2C_ID1_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) TPS80031_I2C_ID2_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) TPS80031_I2C_ID3_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct tps80031_pupd_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u8 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) u8 pullup_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) u8 pulldown_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define TPS80031_IRQ(_reg, _mask) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .reg_offset = (TPS80031_INT_MSK_LINE_##_reg) - \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) TPS80031_INT_MSK_LINE_A, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .mask = BIT(_mask), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static const struct regmap_irq tps80031_main_irqs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) [TPS80031_INT_PWRON] = TPS80031_IRQ(A, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) [TPS80031_INT_RPWRON] = TPS80031_IRQ(A, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) [TPS80031_INT_SYS_VLOW] = TPS80031_IRQ(A, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) [TPS80031_INT_RTC_ALARM] = TPS80031_IRQ(A, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) [TPS80031_INT_RTC_PERIOD] = TPS80031_IRQ(A, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) [TPS80031_INT_HOT_DIE] = TPS80031_IRQ(A, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) [TPS80031_INT_VXX_SHORT] = TPS80031_IRQ(A, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) [TPS80031_INT_SPDURATION] = TPS80031_IRQ(A, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) [TPS80031_INT_WATCHDOG] = TPS80031_IRQ(B, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) [TPS80031_INT_BAT] = TPS80031_IRQ(B, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) [TPS80031_INT_SIM] = TPS80031_IRQ(B, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) [TPS80031_INT_MMC] = TPS80031_IRQ(B, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) [TPS80031_INT_RES] = TPS80031_IRQ(B, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) [TPS80031_INT_GPADC_RT] = TPS80031_IRQ(B, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) [TPS80031_INT_GPADC_SW2_EOC] = TPS80031_IRQ(B, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) [TPS80031_INT_CC_AUTOCAL] = TPS80031_IRQ(B, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) [TPS80031_INT_ID_WKUP] = TPS80031_IRQ(C, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) [TPS80031_INT_VBUSS_WKUP] = TPS80031_IRQ(C, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) [TPS80031_INT_ID] = TPS80031_IRQ(C, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) [TPS80031_INT_VBUS] = TPS80031_IRQ(C, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) [TPS80031_INT_CHRG_CTRL] = TPS80031_IRQ(C, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) [TPS80031_INT_EXT_CHRG] = TPS80031_IRQ(C, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) [TPS80031_INT_INT_CHRG] = TPS80031_IRQ(C, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) [TPS80031_INT_RES2] = TPS80031_IRQ(C, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static struct regmap_irq_chip tps80031_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .name = "tps80031",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .irqs = tps80031_main_irqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .num_irqs = ARRAY_SIZE(tps80031_main_irqs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .num_regs = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .status_base = TPS80031_INT_STS_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .mask_base = TPS80031_INT_MSK_LINE_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define PUPD_DATA(_reg, _pulldown_bit, _pullup_bit) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .reg = TPS80031_CFG_INPUT_PUPD##_reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .pulldown_bit = _pulldown_bit, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .pullup_bit = _pullup_bit, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static const struct tps80031_pupd_data tps80031_pupds[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) [TPS80031_PREQ1] = PUPD_DATA(1, BIT(0), BIT(1)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) [TPS80031_PREQ2A] = PUPD_DATA(1, BIT(2), BIT(3)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) [TPS80031_PREQ2B] = PUPD_DATA(1, BIT(4), BIT(5)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) [TPS80031_PREQ2C] = PUPD_DATA(1, BIT(6), BIT(7)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) [TPS80031_PREQ3] = PUPD_DATA(2, BIT(0), BIT(1)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) [TPS80031_NRES_WARM] = PUPD_DATA(2, 0, BIT(2)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) [TPS80031_PWM_FORCE] = PUPD_DATA(2, BIT(5), 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) [TPS80031_CHRG_EXT_CHRG_STATZ] = PUPD_DATA(2, 0, BIT(6)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) [TPS80031_SIM] = PUPD_DATA(3, BIT(0), BIT(1)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) [TPS80031_MMC] = PUPD_DATA(3, BIT(2), BIT(3)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) [TPS80031_GPADC_START] = PUPD_DATA(3, BIT(4), 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) [TPS80031_DVSI2C_SCL] = PUPD_DATA(4, 0, BIT(0)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) [TPS80031_DVSI2C_SDA] = PUPD_DATA(4, 0, BIT(1)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) [TPS80031_CTLI2C_SCL] = PUPD_DATA(4, 0, BIT(2)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) [TPS80031_CTLI2C_SDA] = PUPD_DATA(4, 0, BIT(3)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static struct tps80031 *tps80031_power_off_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) int tps80031_ext_power_req_config(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) unsigned long ext_ctrl_flag, int preq_bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) int state_reg_add, int trans_reg_add)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) u8 res_ass_reg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) int preq_mask_bit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (!(ext_ctrl_flag & TPS80031_EXT_PWR_REQ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (ext_ctrl_flag & TPS80031_PWR_REQ_INPUT_PREQ1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) res_ass_reg = TPS80031_PREQ1_RES_ASS_A + (preq_bit >> 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) preq_mask_bit = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) } else if (ext_ctrl_flag & TPS80031_PWR_REQ_INPUT_PREQ2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) res_ass_reg = TPS80031_PREQ2_RES_ASS_A + (preq_bit >> 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) preq_mask_bit = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) } else if (ext_ctrl_flag & TPS80031_PWR_REQ_INPUT_PREQ3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) res_ass_reg = TPS80031_PREQ3_RES_ASS_A + (preq_bit >> 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) preq_mask_bit = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /* Configure REQ_ASS registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) ret = tps80031_set_bits(dev, TPS80031_SLAVE_ID1, res_ass_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) BIT(preq_bit & 0x7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) dev_err(dev, "reg 0x%02x setbit failed, err = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) res_ass_reg, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* Unmask the PREQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) ret = tps80031_clr_bits(dev, TPS80031_SLAVE_ID1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) TPS80031_PHOENIX_MSK_TRANSITION, BIT(preq_mask_bit));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) dev_err(dev, "reg 0x%02x clrbit failed, err = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) TPS80031_PHOENIX_MSK_TRANSITION, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /* Switch regulator control to resource now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) if (ext_ctrl_flag & (TPS80031_PWR_REQ_INPUT_PREQ2 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) TPS80031_PWR_REQ_INPUT_PREQ3)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) ret = tps80031_update(dev, TPS80031_SLAVE_ID1, state_reg_add,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 0x0, TPS80031_STATE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) dev_err(dev, "reg 0x%02x update failed, err = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) state_reg_add, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) ret = tps80031_update(dev, TPS80031_SLAVE_ID1, trans_reg_add,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) TPS80031_TRANS_SLEEP_OFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) TPS80031_TRANS_SLEEP_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) dev_err(dev, "reg 0x%02x update failed, err = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) trans_reg_add, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) EXPORT_SYMBOL_GPL(tps80031_ext_power_req_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static void tps80031_power_off(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) dev_info(tps80031_power_off_dev->dev, "switching off PMU\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) tps80031_write(tps80031_power_off_dev->dev, TPS80031_SLAVE_ID1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) TPS80031_PHOENIX_DEV_ON, TPS80031_DEVOFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static void tps80031_pupd_init(struct tps80031 *tps80031,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) struct tps80031_platform_data *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) struct tps80031_pupd_init_data *pupd_init_data = pdata->pupd_init_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) int data_size = pdata->pupd_init_data_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) for (i = 0; i < data_size; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) struct tps80031_pupd_init_data *pupd_init = &pupd_init_data[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) const struct tps80031_pupd_data *pupd =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) &tps80031_pupds[pupd_init->input_pin];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) u8 update_value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) u8 update_mask = pupd->pulldown_bit | pupd->pullup_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) if (pupd_init->setting == TPS80031_PUPD_PULLDOWN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) update_value = pupd->pulldown_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) else if (pupd_init->setting == TPS80031_PUPD_PULLUP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) update_value = pupd->pullup_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) tps80031_update(tps80031->dev, TPS80031_SLAVE_ID1, pupd->reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) update_value, update_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static int tps80031_init_ext_control(struct tps80031 *tps80031,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) struct tps80031_platform_data *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) struct device *dev = tps80031->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /* Clear all external control for this rail */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) for (i = 0; i < 9; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) ret = tps80031_write(dev, TPS80031_SLAVE_ID1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) TPS80031_PREQ1_RES_ASS_A + i, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) dev_err(dev, "reg 0x%02x write failed, err = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) TPS80031_PREQ1_RES_ASS_A + i, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /* Mask the PREQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) ret = tps80031_set_bits(dev, TPS80031_SLAVE_ID1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) TPS80031_PHOENIX_MSK_TRANSITION, 0x7 << 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) dev_err(dev, "reg 0x%02x set_bits failed, err = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) TPS80031_PHOENIX_MSK_TRANSITION, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static int tps80031_irq_init(struct tps80031 *tps80031, int irq, int irq_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) struct device *dev = tps80031->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) * The MASK register used for updating status register when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) * interrupt occurs and LINE register used to pass the status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) * to actual interrupt line. As per datasheet:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) * When INT_MSK_LINE [i] is set to 1, the associated interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * number i is INT line masked, which means that no interrupt is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) * generated on the INT line.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) * When INT_MSK_LINE [i] is set to 0, the associated interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) * number i is line enabled: An interrupt is generated on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * INT line.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * In any case, the INT_STS [i] status bit may or may not be updated,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * only linked to the INT_MSK_STS [i] configuration register bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * When INT_MSK_STS [i] is set to 1, the associated interrupt number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) * i is status masked, which means that no interrupt is stored in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) * the INT_STS[i] status bit. Note that no interrupt number i is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) * generated on the INT line, even if the INT_MSK_LINE [i] register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) * bit is set to 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) * When INT_MSK_STS [i] is set to 0, the associated interrupt number i
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) * is status enabled: An interrupt status is updated in the INT_STS [i]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) * register. The interrupt may or may not be generated on the INT line,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) * depending on the INT_MSK_LINE [i] configuration register bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) for (i = 0; i < 3; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) tps80031_write(dev, TPS80031_SLAVE_ID2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) TPS80031_INT_MSK_STS_A + i, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) ret = regmap_add_irq_chip(tps80031->regmap[TPS80031_SLAVE_ID2], irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) IRQF_ONESHOT, irq_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) &tps80031_irq_chip, &tps80031->irq_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) dev_err(dev, "add irq failed, err = %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static bool rd_wr_reg_id0(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) case TPS80031_SMPS1_CFG_FORCE ... TPS80031_SMPS2_CFG_VOLTAGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static bool rd_wr_reg_id1(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) case TPS80031_SECONDS_REG ... TPS80031_RTC_RESET_STATUS_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) case TPS80031_VALIDITY0 ... TPS80031_VALIDITY7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) case TPS80031_PHOENIX_START_CONDITION ... TPS80031_KEY_PRESS_DUR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) case TPS80031_SMPS4_CFG_TRANS ... TPS80031_SMPS3_CFG_VOLTAGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) case TPS80031_BROADCAST_ADDR_ALL ... TPS80031_BROADCAST_ADDR_CLK_RST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) case TPS80031_VANA_CFG_TRANS ... TPS80031_LDO7_CFG_VOLTAGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) case TPS80031_REGEN1_CFG_TRANS ... TPS80031_TMP_CFG_STATE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) case TPS80031_PREQ1_RES_ASS_A ... TPS80031_PREQ3_RES_ASS_C:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) case TPS80031_SMPS_OFFSET ... TPS80031_BATDEBOUNCING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) case TPS80031_CFG_INPUT_PUPD1 ... TPS80031_CFG_SMPS_PD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) case TPS80031_BACKUP_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static bool is_volatile_reg_id1(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) case TPS80031_SMPS4_CFG_TRANS ... TPS80031_SMPS3_CFG_VOLTAGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) case TPS80031_VANA_CFG_TRANS ... TPS80031_LDO7_CFG_VOLTAGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) case TPS80031_REGEN1_CFG_TRANS ... TPS80031_TMP_CFG_STATE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) case TPS80031_PREQ1_RES_ASS_A ... TPS80031_PREQ3_RES_ASS_C:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) case TPS80031_SMPS_OFFSET ... TPS80031_BATDEBOUNCING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) case TPS80031_CFG_INPUT_PUPD1 ... TPS80031_CFG_SMPS_PD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static bool rd_wr_reg_id2(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) case TPS80031_USB_VENDOR_ID_LSB ... TPS80031_USB_OTG_REVISION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) case TPS80031_GPADC_CTRL ... TPS80031_CTRL_P1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) case TPS80031_RTCH0_LSB ... TPS80031_GPCH0_MSB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) case TPS80031_TOGGLE1 ... TPS80031_VIBMODE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) case TPS80031_PWM1ON ... TPS80031_PWM2OFF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) case TPS80031_FG_REG_00 ... TPS80031_FG_REG_11:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) case TPS80031_INT_STS_A ... TPS80031_INT_MSK_STS_C:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) case TPS80031_CONTROLLER_CTRL2 ... TPS80031_LED_PWM_CTRL2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) static bool rd_wr_reg_id3(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) case TPS80031_GPADC_TRIM0 ... TPS80031_GPADC_TRIM18:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) static const struct regmap_config tps80031_regmap_configs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .writeable_reg = rd_wr_reg_id0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .readable_reg = rd_wr_reg_id0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .max_register = TPS80031_MAX_REGISTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .writeable_reg = rd_wr_reg_id1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .readable_reg = rd_wr_reg_id1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .volatile_reg = is_volatile_reg_id1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .max_register = TPS80031_MAX_REGISTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .writeable_reg = rd_wr_reg_id2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) .readable_reg = rd_wr_reg_id2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) .max_register = TPS80031_MAX_REGISTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) .reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) .val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) .writeable_reg = rd_wr_reg_id3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) .readable_reg = rd_wr_reg_id3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) .max_register = TPS80031_MAX_REGISTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) static int tps80031_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) struct tps80031_platform_data *pdata = dev_get_platdata(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) struct tps80031 *tps80031;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) uint8_t es_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) uint8_t ep_ver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) if (!pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) dev_err(&client->dev, "tps80031 requires platform data\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) tps80031 = devm_kzalloc(&client->dev, sizeof(*tps80031), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) if (!tps80031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) for (i = 0; i < TPS80031_NUM_SLAVES; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) if (tps80031_slave_address[i] == client->addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) tps80031->clients[i] = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) tps80031->clients[i] = devm_i2c_new_dummy_device(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) client->adapter, tps80031_slave_address[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) if (IS_ERR(tps80031->clients[i])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) dev_err(&client->dev, "can't attach client %d\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) return PTR_ERR(tps80031->clients[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) i2c_set_clientdata(tps80031->clients[i], tps80031);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) tps80031->regmap[i] = devm_regmap_init_i2c(tps80031->clients[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) &tps80031_regmap_configs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) if (IS_ERR(tps80031->regmap[i])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) ret = PTR_ERR(tps80031->regmap[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) "regmap %d init failed, err %d\n", i, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) ret = tps80031_read(&client->dev, TPS80031_SLAVE_ID3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) TPS80031_JTAGVERNUM, &es_version);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) "Silicon version number read failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) ret = tps80031_read(&client->dev, TPS80031_SLAVE_ID3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) TPS80031_EPROM_REV, &ep_ver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) "Silicon eeprom version read failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) dev_info(&client->dev, "ES version 0x%02x and EPROM version 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) es_version, ep_ver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) tps80031->es_version = es_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) tps80031->dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) i2c_set_clientdata(client, tps80031);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) tps80031->chip_info = id->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) ret = tps80031_irq_init(tps80031, client->irq, pdata->irq_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) dev_err(&client->dev, "IRQ init failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) tps80031_pupd_init(tps80031, pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) tps80031_init_ext_control(tps80031, pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) ret = mfd_add_devices(tps80031->dev, -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) tps80031_cell, ARRAY_SIZE(tps80031_cell),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) NULL, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) regmap_irq_get_domain(tps80031->irq_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) dev_err(&client->dev, "mfd_add_devices failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) goto fail_mfd_add;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) if (pdata->use_power_off && !pm_power_off) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) tps80031_power_off_dev = tps80031;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) pm_power_off = tps80031_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) fail_mfd_add:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) regmap_del_irq_chip(client->irq, tps80031->irq_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) static const struct i2c_device_id tps80031_id_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) { "tps80031", TPS80031 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) { "tps80032", TPS80032 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) static struct i2c_driver tps80031_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) .name = "tps80031",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) .suppress_bind_attrs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) .probe = tps80031_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) .id_table = tps80031_id_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) static int __init tps80031_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) return i2c_add_driver(&tps80031_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) subsys_initcall(tps80031_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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