^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * tps65910.c -- TI TPS6591x chip family multi-function driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2010 Texas Instruments Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Graeme Gregory <gg@slimlogic.co.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Author: Jorge Eduardo Candelaria <jedu@slimlogic.co.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/mfd/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/mfd/tps65910.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) static struct resource rtc_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) .start = TPS65910_IRQ_RTC_ALARM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) .end = TPS65910_IRQ_RTC_ALARM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static const struct mfd_cell tps65910s[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) .name = "tps65910-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) .name = "tps65910-pmic",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) .name = "tps65910-rtc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) .num_resources = ARRAY_SIZE(rtc_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) .resources = &rtc_resources[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) .name = "tps65910-power",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static const struct regmap_irq tps65911_irqs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* INT_STS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) [TPS65911_IRQ_PWRHOLD_F] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) .mask = INT_MSK_PWRHOLD_F_IT_MSK_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .reg_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) [TPS65911_IRQ_VBAT_VMHI] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .mask = INT_MSK_VMBHI_IT_MSK_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .reg_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) [TPS65911_IRQ_PWRON] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .mask = INT_MSK_PWRON_IT_MSK_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .reg_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) [TPS65911_IRQ_PWRON_LP] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .mask = INT_MSK_PWRON_LP_IT_MSK_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .reg_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) [TPS65911_IRQ_PWRHOLD_R] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) .mask = INT_MSK_PWRHOLD_R_IT_MSK_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) .reg_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) [TPS65911_IRQ_HOTDIE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .mask = INT_MSK_HOTDIE_IT_MSK_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .reg_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) [TPS65911_IRQ_RTC_ALARM] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .mask = INT_MSK_RTC_ALARM_IT_MSK_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .reg_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) [TPS65911_IRQ_RTC_PERIOD] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .mask = INT_MSK_RTC_PERIOD_IT_MSK_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .reg_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* INT_STS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) [TPS65911_IRQ_GPIO0_R] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .mask = INT_MSK2_GPIO0_R_IT_MSK_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) [TPS65911_IRQ_GPIO0_F] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .mask = INT_MSK2_GPIO0_F_IT_MSK_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) [TPS65911_IRQ_GPIO1_R] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .mask = INT_MSK2_GPIO1_R_IT_MSK_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) [TPS65911_IRQ_GPIO1_F] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .mask = INT_MSK2_GPIO1_F_IT_MSK_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) [TPS65911_IRQ_GPIO2_R] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .mask = INT_MSK2_GPIO2_R_IT_MSK_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) [TPS65911_IRQ_GPIO2_F] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .mask = INT_MSK2_GPIO2_F_IT_MSK_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) [TPS65911_IRQ_GPIO3_R] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .mask = INT_MSK2_GPIO3_R_IT_MSK_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) [TPS65911_IRQ_GPIO3_F] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .mask = INT_MSK2_GPIO3_F_IT_MSK_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* INT_STS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) [TPS65911_IRQ_GPIO4_R] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .mask = INT_MSK3_GPIO4_R_IT_MSK_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .reg_offset = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) [TPS65911_IRQ_GPIO4_F] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .mask = INT_MSK3_GPIO4_F_IT_MSK_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .reg_offset = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) [TPS65911_IRQ_GPIO5_R] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .mask = INT_MSK3_GPIO5_R_IT_MSK_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .reg_offset = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) [TPS65911_IRQ_GPIO5_F] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .mask = INT_MSK3_GPIO5_F_IT_MSK_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .reg_offset = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) [TPS65911_IRQ_WTCHDG] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .mask = INT_MSK3_WTCHDG_IT_MSK_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .reg_offset = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) [TPS65911_IRQ_VMBCH2_H] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .mask = INT_MSK3_VMBCH2_H_IT_MSK_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .reg_offset = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) [TPS65911_IRQ_VMBCH2_L] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .mask = INT_MSK3_VMBCH2_L_IT_MSK_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .reg_offset = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) [TPS65911_IRQ_PWRDN] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .mask = INT_MSK3_PWRDN_IT_MSK_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .reg_offset = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static const struct regmap_irq tps65910_irqs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* INT_STS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) [TPS65910_IRQ_VBAT_VMBDCH] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .mask = TPS65910_INT_MSK_VMBDCH_IT_MSK_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .reg_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) [TPS65910_IRQ_VBAT_VMHI] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .mask = TPS65910_INT_MSK_VMBHI_IT_MSK_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .reg_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) [TPS65910_IRQ_PWRON] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .mask = TPS65910_INT_MSK_PWRON_IT_MSK_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .reg_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) [TPS65910_IRQ_PWRON_LP] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .mask = TPS65910_INT_MSK_PWRON_LP_IT_MSK_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .reg_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) [TPS65910_IRQ_PWRHOLD] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .mask = TPS65910_INT_MSK_PWRHOLD_IT_MSK_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .reg_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) [TPS65910_IRQ_HOTDIE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .mask = TPS65910_INT_MSK_HOTDIE_IT_MSK_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .reg_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) [TPS65910_IRQ_RTC_ALARM] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .mask = TPS65910_INT_MSK_RTC_ALARM_IT_MSK_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .reg_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) [TPS65910_IRQ_RTC_PERIOD] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .mask = TPS65910_INT_MSK_RTC_PERIOD_IT_MSK_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .reg_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* INT_STS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) [TPS65910_IRQ_GPIO_R] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .mask = TPS65910_INT_MSK2_GPIO0_F_IT_MSK_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) [TPS65910_IRQ_GPIO_F] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .mask = TPS65910_INT_MSK2_GPIO0_R_IT_MSK_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static struct regmap_irq_chip tps65911_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .name = "tps65910",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .irqs = tps65911_irqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .num_irqs = ARRAY_SIZE(tps65911_irqs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .num_regs = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .irq_reg_stride = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .status_base = TPS65910_INT_STS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .mask_base = TPS65910_INT_MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .ack_base = TPS65910_INT_STS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static struct regmap_irq_chip tps65910_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .name = "tps65910",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .irqs = tps65910_irqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .num_irqs = ARRAY_SIZE(tps65910_irqs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .num_regs = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .irq_reg_stride = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .status_base = TPS65910_INT_STS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .mask_base = TPS65910_INT_MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .ack_base = TPS65910_INT_STS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static int tps65910_irq_init(struct tps65910 *tps65910, int irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) struct tps65910_platform_data *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static struct regmap_irq_chip *tps6591x_irqs_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if (!irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) dev_warn(tps65910->dev, "No interrupt support, no core IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) if (!pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) dev_warn(tps65910->dev, "No interrupt support, no pdata\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) switch (tps65910_chip_id(tps65910)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) case TPS65910:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) tps6591x_irqs_chip = &tps65910_irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) case TPS65911:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) tps6591x_irqs_chip = &tps65911_irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) tps65910->chip_irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) ret = devm_regmap_add_irq_chip(tps65910->dev, tps65910->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) tps65910->chip_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) IRQF_ONESHOT, pdata->irq_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) tps6591x_irqs_chip, &tps65910->irq_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) dev_warn(tps65910->dev, "Failed to add irq_chip %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) tps65910->chip_irq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static bool is_volatile_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) struct tps65910 *tps65910 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) * Caching all regulator registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) * All regualator register address range is same for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) * TPS65910 and TPS65911
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) if ((reg >= TPS65910_VIO) && (reg <= TPS65910_VDAC)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /* Check for non-existing register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) if (tps65910_chip_id(tps65910) == TPS65910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) if ((reg == TPS65911_VDDCTRL_OP) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) (reg == TPS65911_VDDCTRL_SR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static const struct regmap_config tps65910_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) .reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) .volatile_reg = is_volatile_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .max_register = TPS65910_MAX_REGISTER - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .cache_type = REGCACHE_RBTREE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) static int tps65910_ck32k_init(struct tps65910 *tps65910,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) struct tps65910_board *pmic_pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) if (!pmic_pdata->en_ck32k_xtal)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) ret = tps65910_reg_clear_bits(tps65910, TPS65910_DEVCTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) DEVCTRL_CK32K_CTRL_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) dev_err(tps65910->dev, "clear ck32k_ctrl failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static int tps65910_sleepinit(struct tps65910 *tps65910,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) struct tps65910_board *pmic_pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) if (!pmic_pdata->en_dev_slp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) dev = tps65910->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) /* enabling SLEEP device state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) ret = tps65910_reg_set_bits(tps65910, TPS65910_DEVCTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) DEVCTRL_DEV_SLP_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) dev_err(dev, "set dev_slp failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) goto err_sleep_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) if (pmic_pdata->slp_keepon.therm_keepon) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) ret = tps65910_reg_set_bits(tps65910,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) TPS65910_SLEEP_KEEP_RES_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) SLEEP_KEEP_RES_ON_THERM_KEEPON_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) dev_err(dev, "set therm_keepon failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) goto disable_dev_slp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) if (pmic_pdata->slp_keepon.clkout32k_keepon) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) ret = tps65910_reg_set_bits(tps65910,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) TPS65910_SLEEP_KEEP_RES_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) SLEEP_KEEP_RES_ON_CLKOUT32K_KEEPON_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) dev_err(dev, "set clkout32k_keepon failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) goto disable_dev_slp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) if (pmic_pdata->slp_keepon.i2chs_keepon) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) ret = tps65910_reg_set_bits(tps65910,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) TPS65910_SLEEP_KEEP_RES_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) SLEEP_KEEP_RES_ON_I2CHS_KEEPON_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) dev_err(dev, "set i2chs_keepon failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) goto disable_dev_slp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) disable_dev_slp:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) tps65910_reg_clear_bits(tps65910, TPS65910_DEVCTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) DEVCTRL_DEV_SLP_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) err_sleep_init:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) static const struct of_device_id tps65910_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) { .compatible = "ti,tps65910", .data = (void *)TPS65910},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) { .compatible = "ti,tps65911", .data = (void *)TPS65911},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) static struct tps65910_board *tps65910_parse_dt(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) unsigned long *chip_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) struct device_node *np = client->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) struct tps65910_board *board_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) unsigned int prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) match = of_match_device(tps65910_of_match, &client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) if (!match) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) dev_err(&client->dev, "Failed to find matching dt id\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) *chip_id = (unsigned long)match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) board_info = devm_kzalloc(&client->dev, sizeof(*board_info),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) if (!board_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) ret = of_property_read_u32(np, "ti,vmbch-threshold", &prop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) board_info->vmbch_threshold = prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) ret = of_property_read_u32(np, "ti,vmbch2-threshold", &prop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) board_info->vmbch2_threshold = prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) prop = of_property_read_bool(np, "ti,en-ck32k-xtal");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) board_info->en_ck32k_xtal = prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) prop = of_property_read_bool(np, "ti,sleep-enable");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) board_info->en_dev_slp = prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) prop = of_property_read_bool(np, "ti,sleep-keep-therm");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) board_info->slp_keepon.therm_keepon = prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) prop = of_property_read_bool(np, "ti,sleep-keep-ck32k");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) board_info->slp_keepon.clkout32k_keepon = prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) prop = of_property_read_bool(np, "ti,sleep-keep-hsclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) board_info->slp_keepon.i2chs_keepon = prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) board_info->irq = client->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) board_info->irq_base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) board_info->pm_off = of_property_read_bool(np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) "ti,system-power-controller");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) return board_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) static inline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) struct tps65910_board *tps65910_parse_dt(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) unsigned long *chip_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) static struct i2c_client *tps65910_i2c_client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) static void tps65910_power_off(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) struct tps65910 *tps65910;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) tps65910 = dev_get_drvdata(&tps65910_i2c_client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) if (tps65910_reg_set_bits(tps65910, TPS65910_DEVCTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) DEVCTRL_PWR_OFF_MASK) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) tps65910_reg_clear_bits(tps65910, TPS65910_DEVCTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) DEVCTRL_DEV_ON_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) static int tps65910_i2c_probe(struct i2c_client *i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) struct tps65910 *tps65910;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) struct tps65910_board *pmic_plat_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) struct tps65910_board *of_pmic_plat_data = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) struct tps65910_platform_data *init_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) unsigned long chip_id = id->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) pmic_plat_data = dev_get_platdata(&i2c->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) if (!pmic_plat_data && i2c->dev.of_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) pmic_plat_data = tps65910_parse_dt(i2c, &chip_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) of_pmic_plat_data = pmic_plat_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) if (!pmic_plat_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) init_data = devm_kzalloc(&i2c->dev, sizeof(*init_data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) if (init_data == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) tps65910 = devm_kzalloc(&i2c->dev, sizeof(*tps65910), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) if (tps65910 == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) tps65910->of_plat_data = of_pmic_plat_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) i2c_set_clientdata(i2c, tps65910);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) tps65910->dev = &i2c->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) tps65910->i2c_client = i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) tps65910->id = chip_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) /* Work around silicon erratum SWCZ010: the tps65910 may miss the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) * first I2C transfer. So issue a dummy transfer before the first
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) * real transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) i2c_master_send(i2c, "", 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) tps65910->regmap = devm_regmap_init_i2c(i2c, &tps65910_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) if (IS_ERR(tps65910->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) ret = PTR_ERR(tps65910->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) dev_err(&i2c->dev, "regmap initialization failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) init_data->irq = pmic_plat_data->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) init_data->irq_base = pmic_plat_data->irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) tps65910_irq_init(tps65910, init_data->irq, init_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) tps65910_ck32k_init(tps65910, pmic_plat_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) tps65910_sleepinit(tps65910, pmic_plat_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) if (pmic_plat_data->pm_off && !pm_power_off) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) tps65910_i2c_client = i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) pm_power_off = tps65910_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) ret = devm_mfd_add_devices(tps65910->dev, -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) tps65910s, ARRAY_SIZE(tps65910s),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) NULL, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) regmap_irq_get_domain(tps65910->irq_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) dev_err(&i2c->dev, "mfd_add_devices failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) static const struct i2c_device_id tps65910_i2c_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) { "tps65910", TPS65910 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) { "tps65911", TPS65911 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) static struct i2c_driver tps65910_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) .name = "tps65910",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) .of_match_table = of_match_ptr(tps65910_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) .probe = tps65910_i2c_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) .id_table = tps65910_i2c_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) static int __init tps65910_i2c_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) return i2c_add_driver(&tps65910_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) /* init early so consumer devices can complete system boot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) subsys_initcall(tps65910_i2c_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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