^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Driver for TPS65218 Integrated power management chipsets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * This program is free software; you can redistribute it and/or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * modify it under the terms of the GNU General Public License version 2 as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * published by the Free Software Foundation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * This program is distributed "as is" WITHOUT ANY WARRANTY of any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * kind, whether expressed or implied; without even the implied warranty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * GNU General Public License version 2 for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/mfd/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/mfd/tps65218.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define TPS65218_PASSWORD_REGS_UNLOCK 0x7D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static const struct mfd_cell tps65218_cells[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) .name = "tps65218-pwrbutton",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) .of_compatible = "ti,tps65218-pwrbutton",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) .name = "tps65218-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) .of_compatible = "ti,tps65218-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) { .name = "tps65218-regulator", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * tps65218_reg_write: Write a single tps65218 register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * @tps: Device to write to.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * @reg: Register to write to.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * @val: Value to write.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * @level: Password protected level
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) int tps65218_reg_write(struct tps65218 *tps, unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) unsigned int val, unsigned int level)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) unsigned int xor_reg_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) switch (level) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) case TPS65218_PROTECT_NONE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) return regmap_write(tps->regmap, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) case TPS65218_PROTECT_L1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) xor_reg_val = reg ^ TPS65218_PASSWORD_REGS_UNLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) ret = regmap_write(tps->regmap, TPS65218_REG_PASSWORD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) xor_reg_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) return regmap_write(tps->regmap, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) EXPORT_SYMBOL_GPL(tps65218_reg_write);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * tps65218_update_bits: Modify bits w.r.t mask, val and level.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * @tps: Device to write to.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * @reg: Register to read-write to.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * @mask: Mask.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * @val: Value to write.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * @level: Password protected level
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static int tps65218_update_bits(struct tps65218 *tps, unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) unsigned int mask, unsigned int val, unsigned int level)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) unsigned int data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) ret = regmap_read(tps->regmap, reg, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) dev_err(tps->dev, "Read from reg 0x%x failed\n", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) data &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) data |= val & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) mutex_lock(&tps->tps_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) ret = tps65218_reg_write(tps, reg, data, level);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) dev_err(tps->dev, "Write for reg 0x%x failed\n", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) mutex_unlock(&tps->tps_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) int tps65218_set_bits(struct tps65218 *tps, unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) unsigned int mask, unsigned int val, unsigned int level)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) return tps65218_update_bits(tps, reg, mask, val, level);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) EXPORT_SYMBOL_GPL(tps65218_set_bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) int tps65218_clear_bits(struct tps65218 *tps, unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) unsigned int mask, unsigned int level)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) return tps65218_update_bits(tps, reg, mask, 0, level);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) EXPORT_SYMBOL_GPL(tps65218_clear_bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static const struct regmap_range tps65218_yes_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) regmap_reg_range(TPS65218_REG_INT1, TPS65218_REG_INT2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) regmap_reg_range(TPS65218_REG_STATUS, TPS65218_REG_STATUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static const struct regmap_access_table tps65218_volatile_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .yes_ranges = tps65218_yes_ranges,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .n_yes_ranges = ARRAY_SIZE(tps65218_yes_ranges),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static const struct regmap_config tps65218_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .cache_type = REGCACHE_RBTREE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .volatile_table = &tps65218_volatile_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static const struct regmap_irq tps65218_irqs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* INT1 IRQs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) [TPS65218_PRGC_IRQ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .mask = TPS65218_INT1_PRGC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) [TPS65218_CC_AQC_IRQ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .mask = TPS65218_INT1_CC_AQC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) [TPS65218_HOT_IRQ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .mask = TPS65218_INT1_HOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) [TPS65218_PB_IRQ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .mask = TPS65218_INT1_PB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) [TPS65218_AC_IRQ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .mask = TPS65218_INT1_AC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) [TPS65218_VPRG_IRQ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .mask = TPS65218_INT1_VPRG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) [TPS65218_INVALID1_IRQ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) [TPS65218_INVALID2_IRQ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* INT2 IRQs*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) [TPS65218_LS1_I_IRQ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .mask = TPS65218_INT2_LS1_I,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) [TPS65218_LS2_I_IRQ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .mask = TPS65218_INT2_LS2_I,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) [TPS65218_LS3_I_IRQ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .mask = TPS65218_INT2_LS3_I,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) [TPS65218_LS1_F_IRQ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .mask = TPS65218_INT2_LS1_F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) [TPS65218_LS2_F_IRQ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .mask = TPS65218_INT2_LS2_F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) [TPS65218_LS3_F_IRQ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .mask = TPS65218_INT2_LS3_F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) [TPS65218_INVALID3_IRQ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) [TPS65218_INVALID4_IRQ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static struct regmap_irq_chip tps65218_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .name = "tps65218",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .irqs = tps65218_irqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .num_irqs = ARRAY_SIZE(tps65218_irqs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .num_regs = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .mask_base = TPS65218_REG_INT_MASK1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .status_base = TPS65218_REG_INT1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static const struct of_device_id of_tps65218_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) { .compatible = "ti,tps65218", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) MODULE_DEVICE_TABLE(of, of_tps65218_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static int tps65218_voltage_set_strict(struct tps65218 *tps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) u32 strict;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) if (of_property_read_u32(tps->dev->of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) "ti,strict-supply-voltage-supervision",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) &strict))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if (strict != 0 && strict != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) dev_err(tps->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) "Invalid ti,strict-supply-voltage-supervision value\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) tps65218_update_bits(tps, TPS65218_REG_CONFIG1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) TPS65218_CONFIG1_STRICT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) strict ? TPS65218_CONFIG1_STRICT : 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) TPS65218_PROTECT_L1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static int tps65218_voltage_set_uv_hyst(struct tps65218 *tps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) u32 hyst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) if (of_property_read_u32(tps->dev->of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) "ti,under-voltage-hyst-microvolt", &hyst))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (hyst != 400000 && hyst != 200000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) dev_err(tps->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) "Invalid ti,under-voltage-hyst-microvolt value\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) tps65218_update_bits(tps, TPS65218_REG_CONFIG2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) TPS65218_CONFIG2_UVLOHYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) hyst == 400000 ? TPS65218_CONFIG2_UVLOHYS : 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) TPS65218_PROTECT_L1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static int tps65218_voltage_set_uvlo(struct tps65218 *tps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) u32 uvlo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) int uvloval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) if (of_property_read_u32(tps->dev->of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) "ti,under-voltage-limit-microvolt", &uvlo))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) switch (uvlo) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) case 2750000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) uvloval = TPS65218_CONFIG1_UVLO_2750000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) case 2950000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) uvloval = TPS65218_CONFIG1_UVLO_2950000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) case 3250000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) uvloval = TPS65218_CONFIG1_UVLO_3250000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) case 3350000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) uvloval = TPS65218_CONFIG1_UVLO_3350000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) dev_err(tps->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) "Invalid ti,under-voltage-limit-microvolt value\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) tps65218_update_bits(tps, TPS65218_REG_CONFIG1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) TPS65218_CONFIG1_UVLO_MASK, uvloval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) TPS65218_PROTECT_L1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static int tps65218_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) const struct i2c_device_id *ids)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) struct tps65218 *tps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) unsigned int chipid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) tps = devm_kzalloc(&client->dev, sizeof(*tps), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) if (!tps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) i2c_set_clientdata(client, tps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) tps->dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) tps->irq = client->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) tps->regmap = devm_regmap_init_i2c(client, &tps65218_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) if (IS_ERR(tps->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) ret = PTR_ERR(tps->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) dev_err(tps->dev, "Failed to allocate register map: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) mutex_init(&tps->tps_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) ret = devm_regmap_add_irq_chip(&client->dev, tps->regmap, tps->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) IRQF_ONESHOT, 0, &tps65218_irq_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) &tps->irq_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) ret = regmap_read(tps->regmap, TPS65218_REG_CHIPID, &chipid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) dev_err(tps->dev, "Failed to read chipid: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) tps->rev = chipid & TPS65218_CHIPID_REV_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) ret = tps65218_voltage_set_strict(tps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) ret = tps65218_voltage_set_uvlo(tps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) ret = tps65218_voltage_set_uv_hyst(tps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) ret = mfd_add_devices(tps->dev, PLATFORM_DEVID_AUTO, tps65218_cells,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) ARRAY_SIZE(tps65218_cells), NULL, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) regmap_irq_get_domain(tps->irq_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) static const struct i2c_device_id tps65218_id_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) { "tps65218", TPS65218 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) MODULE_DEVICE_TABLE(i2c, tps65218_id_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static struct i2c_driver tps65218_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .name = "tps65218",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .of_match_table = of_tps65218_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .probe = tps65218_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .id_table = tps65218_id_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) module_i2c_driver(tps65218_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) MODULE_AUTHOR("J Keerthy <j-keerthy@ti.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) MODULE_DESCRIPTION("TPS65218 chip family multi-function driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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