^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * tps65217.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * TPS65217 chip family multi-function driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * This program is free software; you can redistribute it and/or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * modify it under the terms of the GNU General Public License as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * published by the Free Software Foundation version 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * This program is distributed "as is" WITHOUT ANY WARRANTY of any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * kind, whether express or implied; without even the implied warranty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/mfd/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/mfd/tps65217.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static struct resource charger_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) DEFINE_RES_IRQ_NAMED(TPS65217_IRQ_AC, "AC"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) DEFINE_RES_IRQ_NAMED(TPS65217_IRQ_USB, "USB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static struct resource pb_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) DEFINE_RES_IRQ_NAMED(TPS65217_IRQ_PB, "PB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static void tps65217_irq_lock(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct tps65217 *tps = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) mutex_lock(&tps->irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static void tps65217_irq_sync_unlock(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct tps65217 *tps = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) ret = tps65217_set_bits(tps, TPS65217_REG_INT, TPS65217_INT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) tps->irq_mask, TPS65217_PROTECT_NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) if (ret != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) dev_err(tps->dev, "Failed to sync IRQ masks\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) mutex_unlock(&tps->irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static void tps65217_irq_enable(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct tps65217 *tps = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) u8 mask = BIT(data->hwirq) << TPS65217_INT_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) tps->irq_mask &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static void tps65217_irq_disable(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct tps65217 *tps = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) u8 mask = BIT(data->hwirq) << TPS65217_INT_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) tps->irq_mask |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static struct irq_chip tps65217_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .name = "tps65217",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .irq_bus_lock = tps65217_irq_lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .irq_bus_sync_unlock = tps65217_irq_sync_unlock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .irq_enable = tps65217_irq_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .irq_disable = tps65217_irq_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static struct mfd_cell tps65217s[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .name = "tps65217-pmic",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .of_compatible = "ti,tps65217-pmic",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .name = "tps65217-bl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .of_compatible = "ti,tps65217-bl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .name = "tps65217-charger",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .num_resources = ARRAY_SIZE(charger_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .resources = charger_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .of_compatible = "ti,tps65217-charger",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .name = "tps65217-pwrbutton",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .num_resources = ARRAY_SIZE(pb_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .resources = pb_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .of_compatible = "ti,tps65217-pwrbutton",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static irqreturn_t tps65217_irq_thread(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct tps65217 *tps = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) unsigned int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) bool handled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) ret = tps65217_reg_read(tps, TPS65217_REG_INT, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) dev_err(tps->dev, "Failed to read IRQ status: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) for (i = 0; i < TPS65217_NUM_IRQ; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) if (status & BIT(i)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) handle_nested_irq(irq_find_mapping(tps->irq_domain, i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) handled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) if (handled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static int tps65217_irq_map(struct irq_domain *h, unsigned int virq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) irq_hw_number_t hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct tps65217 *tps = h->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) irq_set_chip_data(virq, tps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) irq_set_chip_and_handler(virq, &tps65217_irq_chip, handle_edge_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) irq_set_nested_thread(virq, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) irq_set_parent(virq, tps->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) irq_set_noprobe(virq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static const struct irq_domain_ops tps65217_irq_domain_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .map = tps65217_irq_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static int tps65217_irq_init(struct tps65217 *tps, int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) mutex_init(&tps->irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) tps->irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* Mask all interrupt sources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) tps->irq_mask = TPS65217_INT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) tps65217_set_bits(tps, TPS65217_REG_INT, TPS65217_INT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) TPS65217_INT_MASK, TPS65217_PROTECT_NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) tps->irq_domain = irq_domain_add_linear(tps->dev->of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) TPS65217_NUM_IRQ, &tps65217_irq_domain_ops, tps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (!tps->irq_domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) dev_err(tps->dev, "Could not create IRQ domain\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) ret = devm_request_threaded_irq(tps->dev, irq, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) tps65217_irq_thread, IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) "tps65217-irq", tps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) dev_err(tps->dev, "Failed to request IRQ %d: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) irq, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) enable_irq_wake(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * tps65217_reg_read: Read a single tps65217 register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * @tps: Device to read from.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * @reg: Register to read.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * @val: Contians the value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) int tps65217_reg_read(struct tps65217 *tps, unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) unsigned int *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) return regmap_read(tps->regmap, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) EXPORT_SYMBOL_GPL(tps65217_reg_read);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * tps65217_reg_write: Write a single tps65217 register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * @tps: Device to write to.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * @reg: Register to write to.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * @val: Value to write.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * @level: Password protected level
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) int tps65217_reg_write(struct tps65217 *tps, unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) unsigned int val, unsigned int level)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) unsigned int xor_reg_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) switch (level) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) case TPS65217_PROTECT_NONE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) return regmap_write(tps->regmap, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) case TPS65217_PROTECT_L1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) xor_reg_val = reg ^ TPS65217_PASSWORD_REGS_UNLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) ret = regmap_write(tps->regmap, TPS65217_REG_PASSWORD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) xor_reg_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) return regmap_write(tps->regmap, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) case TPS65217_PROTECT_L2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) xor_reg_val = reg ^ TPS65217_PASSWORD_REGS_UNLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) ret = regmap_write(tps->regmap, TPS65217_REG_PASSWORD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) xor_reg_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) ret = regmap_write(tps->regmap, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) ret = regmap_write(tps->regmap, TPS65217_REG_PASSWORD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) xor_reg_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) return regmap_write(tps->regmap, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) EXPORT_SYMBOL_GPL(tps65217_reg_write);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) * tps65217_update_bits: Modify bits w.r.t mask, val and level.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * @tps: Device to write to.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) * @reg: Register to read-write to.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * @mask: Mask.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * @val: Value to write.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * @level: Password protected level
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static int tps65217_update_bits(struct tps65217 *tps, unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) unsigned int mask, unsigned int val, unsigned int level)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) unsigned int data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) ret = tps65217_reg_read(tps, reg, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) dev_err(tps->dev, "Read from reg 0x%x failed\n", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) data &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) data |= val & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) ret = tps65217_reg_write(tps, reg, data, level);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) dev_err(tps->dev, "Write for reg 0x%x failed\n", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) int tps65217_set_bits(struct tps65217 *tps, unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) unsigned int mask, unsigned int val, unsigned int level)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) return tps65217_update_bits(tps, reg, mask, val, level);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) EXPORT_SYMBOL_GPL(tps65217_set_bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) int tps65217_clear_bits(struct tps65217 *tps, unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) unsigned int mask, unsigned int level)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) return tps65217_update_bits(tps, reg, mask, 0, level);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) EXPORT_SYMBOL_GPL(tps65217_clear_bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static bool tps65217_volatile_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) case TPS65217_REG_INT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static const struct regmap_config tps65217_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .max_register = TPS65217_REG_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .volatile_reg = tps65217_volatile_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static const struct of_device_id tps65217_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) { .compatible = "ti,tps65217"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) MODULE_DEVICE_TABLE(of, tps65217_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static int tps65217_probe(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) struct tps65217 *tps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) unsigned int version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) bool status_off = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) status_off = of_property_read_bool(client->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) "ti,pmic-shutdown-controller");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) tps = devm_kzalloc(&client->dev, sizeof(*tps), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) if (!tps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) i2c_set_clientdata(client, tps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) tps->dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) tps->regmap = devm_regmap_init_i2c(client, &tps65217_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) if (IS_ERR(tps->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) ret = PTR_ERR(tps->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) dev_err(tps->dev, "Failed to allocate register map: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) if (client->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) tps65217_irq_init(tps, client->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) /* Don't tell children about IRQ resources which won't fire */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) for (i = 0; i < ARRAY_SIZE(tps65217s); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) tps65217s[i].num_resources = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) ret = devm_mfd_add_devices(tps->dev, -1, tps65217s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) ARRAY_SIZE(tps65217s), NULL, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) tps->irq_domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) dev_err(tps->dev, "mfd_add_devices failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) ret = tps65217_reg_read(tps, TPS65217_REG_CHIPID, &version);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) dev_err(tps->dev, "Failed to read revision register: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) /* Set the PMIC to shutdown on PWR_EN toggle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if (status_off) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) ret = tps65217_set_bits(tps, TPS65217_REG_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) TPS65217_STATUS_OFF, TPS65217_STATUS_OFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) TPS65217_PROTECT_NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) dev_warn(tps->dev, "unable to set the status OFF\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) dev_info(tps->dev, "TPS65217 ID %#x version 1.%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) (version & TPS65217_CHIPID_CHIP_MASK) >> 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) version & TPS65217_CHIPID_REV_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) static int tps65217_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) struct tps65217 *tps = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) unsigned int virq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) for (i = 0; i < TPS65217_NUM_IRQ; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) virq = irq_find_mapping(tps->irq_domain, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) if (virq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) irq_dispose_mapping(virq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) irq_domain_remove(tps->irq_domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) tps->irq_domain = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) static const struct i2c_device_id tps65217_id_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) {"tps65217", TPS65217},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) MODULE_DEVICE_TABLE(i2c, tps65217_id_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) static struct i2c_driver tps65217_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) .name = "tps65217",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) .of_match_table = tps65217_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) .id_table = tps65217_id_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) .probe_new = tps65217_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) .remove = tps65217_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) static int __init tps65217_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) return i2c_add_driver(&tps65217_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) subsys_initcall(tps65217_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) static void __exit tps65217_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) i2c_del_driver(&tps65217_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) module_exit(tps65217_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) MODULE_AUTHOR("AnilKumar Ch <anilkumar@ti.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) MODULE_DESCRIPTION("TPS65217 chip family multi-function driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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