Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Core driver for TI TPS65090 PMIC family
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Author: Venu Byravarasu <vbyravarasu@nvidia.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/mfd/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/mfd/tps65090.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define NUM_INT_REG 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define TPS65090_INT1_MASK_VAC_STATUS_CHANGE		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define TPS65090_INT1_MASK_VSYS_STATUS_CHANGE		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define TPS65090_INT1_MASK_BAT_STATUS_CHANGE		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define TPS65090_INT1_MASK_CHARGING_STATUS_CHANGE	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define TPS65090_INT1_MASK_CHARGING_COMPLETE		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define TPS65090_INT1_MASK_OVERLOAD_DCDC1		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define TPS65090_INT1_MASK_OVERLOAD_DCDC2		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define TPS65090_INT2_MASK_OVERLOAD_DCDC3		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define TPS65090_INT2_MASK_OVERLOAD_FET1		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define TPS65090_INT2_MASK_OVERLOAD_FET2		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define TPS65090_INT2_MASK_OVERLOAD_FET3		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define TPS65090_INT2_MASK_OVERLOAD_FET4		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define TPS65090_INT2_MASK_OVERLOAD_FET5		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define TPS65090_INT2_MASK_OVERLOAD_FET6		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define TPS65090_INT2_MASK_OVERLOAD_FET7		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) static struct resource charger_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 		.start  = TPS65090_IRQ_VAC_STATUS_CHANGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 		.end    = TPS65090_IRQ_VAC_STATUS_CHANGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 		.flags  = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) enum tps65090_cells {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	PMIC = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	CHARGER = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) static struct mfd_cell tps65090s[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	[PMIC] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 		.name = "tps65090-pmic",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	[CHARGER] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 		.name = "tps65090-charger",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 		.num_resources = ARRAY_SIZE(charger_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 		.resources = &charger_resources[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 		.of_compatible = "ti,tps65090-charger",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) static const struct regmap_irq tps65090_irqs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	/* INT1 IRQs*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	[TPS65090_IRQ_VAC_STATUS_CHANGE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 		.mask = TPS65090_INT1_MASK_VAC_STATUS_CHANGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	[TPS65090_IRQ_VSYS_STATUS_CHANGE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 		.mask = TPS65090_INT1_MASK_VSYS_STATUS_CHANGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	[TPS65090_IRQ_BAT_STATUS_CHANGE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		.mask = TPS65090_INT1_MASK_BAT_STATUS_CHANGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	[TPS65090_IRQ_CHARGING_STATUS_CHANGE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 		.mask = TPS65090_INT1_MASK_CHARGING_STATUS_CHANGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	[TPS65090_IRQ_CHARGING_COMPLETE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		.mask = TPS65090_INT1_MASK_CHARGING_COMPLETE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	[TPS65090_IRQ_OVERLOAD_DCDC1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		.mask = TPS65090_INT1_MASK_OVERLOAD_DCDC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	[TPS65090_IRQ_OVERLOAD_DCDC2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 		.mask = TPS65090_INT1_MASK_OVERLOAD_DCDC2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	/* INT2 IRQs*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	[TPS65090_IRQ_OVERLOAD_DCDC3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		.reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		.mask = TPS65090_INT2_MASK_OVERLOAD_DCDC3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	[TPS65090_IRQ_OVERLOAD_FET1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		.reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		.mask = TPS65090_INT2_MASK_OVERLOAD_FET1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	[TPS65090_IRQ_OVERLOAD_FET2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		.reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		.mask = TPS65090_INT2_MASK_OVERLOAD_FET2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	[TPS65090_IRQ_OVERLOAD_FET3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		.reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		.mask = TPS65090_INT2_MASK_OVERLOAD_FET3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	[TPS65090_IRQ_OVERLOAD_FET4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		.reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		.mask = TPS65090_INT2_MASK_OVERLOAD_FET4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	[TPS65090_IRQ_OVERLOAD_FET5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		.reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		.mask = TPS65090_INT2_MASK_OVERLOAD_FET5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	[TPS65090_IRQ_OVERLOAD_FET6] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		.reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		.mask = TPS65090_INT2_MASK_OVERLOAD_FET6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	[TPS65090_IRQ_OVERLOAD_FET7] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		.reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		.mask = TPS65090_INT2_MASK_OVERLOAD_FET7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static struct regmap_irq_chip tps65090_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	.name = "tps65090",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	.irqs = tps65090_irqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	.num_irqs = ARRAY_SIZE(tps65090_irqs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	.num_regs = NUM_INT_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	.status_base = TPS65090_REG_INTR_STS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	.mask_base = TPS65090_REG_INTR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	.mask_invert = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static bool is_volatile_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	/* Nearly all registers have status bits mixed in, except a few */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	case TPS65090_REG_INTR_MASK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	case TPS65090_REG_INTR_MASK2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	case TPS65090_REG_CG_CTRL0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	case TPS65090_REG_CG_CTRL1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	case TPS65090_REG_CG_CTRL2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	case TPS65090_REG_CG_CTRL3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	case TPS65090_REG_CG_CTRL4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	case TPS65090_REG_CG_CTRL5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static const struct regmap_config tps65090_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	.reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	.val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	.max_register = TPS65090_MAX_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	.num_reg_defaults_raw = TPS65090_NUM_REGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	.cache_type = REGCACHE_RBTREE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	.volatile_reg = is_volatile_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static const struct of_device_id tps65090_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	{ .compatible = "ti,tps65090",},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static int tps65090_i2c_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 			      const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	struct tps65090_platform_data *pdata = dev_get_platdata(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	int irq_base = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	struct tps65090 *tps65090;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	if (!pdata && !client->dev.of_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 			"tps65090 requires platform data or of_node\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	if (pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		irq_base = pdata->irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	tps65090 = devm_kzalloc(&client->dev, sizeof(*tps65090), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	if (!tps65090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	tps65090->dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	i2c_set_clientdata(client, tps65090);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	tps65090->rmap = devm_regmap_init_i2c(client, &tps65090_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	if (IS_ERR(tps65090->rmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		ret = PTR_ERR(tps65090->rmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		dev_err(&client->dev, "regmap_init failed with err: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	if (client->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		ret = regmap_add_irq_chip(tps65090->rmap, client->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 					  IRQF_ONESHOT | IRQF_TRIGGER_LOW, irq_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 					  &tps65090_irq_chip, &tps65090->irq_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 			dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 				"IRQ init failed with err: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		/* Don't tell children they have an IRQ that'll never fire */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		tps65090s[CHARGER].num_resources = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	ret = mfd_add_devices(tps65090->dev, -1, tps65090s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 			      ARRAY_SIZE(tps65090s), NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 			      0, regmap_irq_get_domain(tps65090->irq_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		dev_err(&client->dev, "add mfd devices failed with err: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 			ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		goto err_irq_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) err_irq_exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	if (client->irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		regmap_del_irq_chip(client->irq, tps65090->irq_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static const struct i2c_device_id tps65090_id_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	{ "tps65090", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	{ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static struct i2c_driver tps65090_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	.driver	= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		.name	= "tps65090",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		.suppress_bind_attrs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		.of_match_table = of_match_ptr(tps65090_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	.probe		= tps65090_i2c_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	.id_table	= tps65090_id_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static int __init tps65090_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	return i2c_add_driver(&tps65090_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) subsys_initcall(tps65090_init);