^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * timberdale.h timberdale FPGA MFD driver defines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2009 Intel Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) /* Supports:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Timberdale FPGA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #ifndef MFD_TIMBERDALE_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define MFD_TIMBERDALE_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define DRV_VERSION "0.3"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /* This driver only support versions >= 3.8 and < 4.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define TIMB_SUPPORTED_MAJOR 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /* This driver only support minor >= 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define TIMB_REQUIRED_MINOR 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* Registers of the control area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define TIMB_REV_MAJOR 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define TIMB_REV_MINOR 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define TIMB_HW_CONFIG 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define TIMB_SW_RST 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* bits in the TIMB_HW_CONFIG register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define TIMB_HW_CONFIG_SPI_8BIT 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define TIMB_HW_VER_MASK 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define TIMB_HW_VER0 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define TIMB_HW_VER1 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define TIMB_HW_VER2 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define TIMB_HW_VER3 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define OCORESOFFSET 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define OCORESEND 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SPIOFFSET 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SPIEND 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define UARTLITEOFFSET 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define UARTLITEEND 0x10f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define RDSOFFSET 0x180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define RDSEND 0x183
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define ETHOFFSET 0x300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define ETHEND 0x3ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define GPIOOFFSET 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define GPIOEND 0x7ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define CHIPCTLOFFSET 0x800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define CHIPCTLEND 0x8ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define CHIPCTLSIZE (CHIPCTLEND - CHIPCTLOFFSET + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define INTCOFFSET 0xc00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define INTCEND 0xfff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define INTCSIZE (INTCEND - INTCOFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define MOSTOFFSET 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define MOSTEND 0x13ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define UARTOFFSET 0x1400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define UARTEND 0x17ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define XIICOFFSET 0x1800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define XIICEND 0x19ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define I2SOFFSET 0x1C00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define I2SEND 0x1fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define LOGIWOFFSET 0x30000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define LOGIWEND 0x37fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define MLCOREOFFSET 0x40000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define MLCOREEND 0x43fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define DMAOFFSET 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define DMAEND 0x013fffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* SDHC0 is placed in PCI bar 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define SDHC0OFFSET 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define SDHC0END 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* SDHC1 is placed in PCI bar 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define SDHC1OFFSET 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define SDHC1END 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define PCI_VENDOR_ID_TIMB 0x10ee
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define PCI_DEVICE_ID_TIMB 0xa123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define IRQ_TIMBERDALE_INIC 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define IRQ_TIMBERDALE_MLB 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define IRQ_TIMBERDALE_GPIO 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define IRQ_TIMBERDALE_I2C 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define IRQ_TIMBERDALE_UART 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define IRQ_TIMBERDALE_DMA 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define IRQ_TIMBERDALE_I2S 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define IRQ_TIMBERDALE_TSC_INT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define IRQ_TIMBERDALE_SDHC 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define IRQ_TIMBERDALE_ADV7180 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define IRQ_TIMBERDALE_ETHSW_IF 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define IRQ_TIMBERDALE_SPI 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define IRQ_TIMBERDALE_UARTLITE 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define IRQ_TIMBERDALE_MLCORE 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define IRQ_TIMBERDALE_MLCORE_BUF 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define IRQ_TIMBERDALE_RDS 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define TIMBERDALE_NR_IRQS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define GPIO_PIN_ASCB 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define GPIO_PIN_INIC_RST 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define GPIO_PIN_BT_RST 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define GPIO_NR_PINS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* DMA Channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define DMA_UART_RX 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define DMA_UART_TX 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define DMA_MLB_RX 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define DMA_MLB_TX 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define DMA_VIDEO_RX 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define DMA_VIDEO_DROP 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define DMA_SDHCI_RX 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define DMA_SDHCI_TX 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define DMA_ETH_RX 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define DMA_ETH_TX 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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