Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * TI Touch Screen / ADC MFD driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * This program is free software; you can redistribute it and/or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * modify it under the terms of the GNU General Public License as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * published by the Free Software Foundation version 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * kind, whether express or implied; without even the implied warranty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/mfd/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #include <linux/mfd/ti_am335x_tscadc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) static const struct regmap_config tscadc_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	.name = "ti_tscadc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	.reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	.reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	.val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) void am335x_tsc_se_set_cache(struct ti_tscadc_dev *tscadc, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	spin_lock_irqsave(&tscadc->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	tscadc->reg_se_cache |= val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	if (tscadc->adc_waiting)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 		wake_up(&tscadc->reg_se_wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	else if (!tscadc->adc_in_use)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 		regmap_write(tscadc->regmap, REG_SE, tscadc->reg_se_cache);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	spin_unlock_irqrestore(&tscadc->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) EXPORT_SYMBOL_GPL(am335x_tsc_se_set_cache);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) static void am335x_tscadc_need_adc(struct ti_tscadc_dev *tscadc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	DEFINE_WAIT(wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	regmap_read(tscadc->regmap, REG_ADCFSM, &reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	if (reg & SEQ_STATUS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 		tscadc->adc_waiting = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 		prepare_to_wait(&tscadc->reg_se_wait, &wait,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 				TASK_UNINTERRUPTIBLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 		spin_unlock_irq(&tscadc->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 		schedule();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 		spin_lock_irq(&tscadc->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 		finish_wait(&tscadc->reg_se_wait, &wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 		 * Sequencer should either be idle or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 		 * busy applying the charge step.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 		regmap_read(tscadc->regmap, REG_ADCFSM, &reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		WARN_ON((reg & SEQ_STATUS) && !(reg & CHARGE_STEP));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		tscadc->adc_waiting = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	tscadc->adc_in_use = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) void am335x_tsc_se_set_once(struct ti_tscadc_dev *tscadc, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	spin_lock_irq(&tscadc->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	am335x_tscadc_need_adc(tscadc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	regmap_write(tscadc->regmap, REG_SE, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	spin_unlock_irq(&tscadc->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) EXPORT_SYMBOL_GPL(am335x_tsc_se_set_once);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) void am335x_tsc_se_adc_done(struct ti_tscadc_dev *tscadc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	spin_lock_irqsave(&tscadc->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	tscadc->adc_in_use = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	regmap_write(tscadc->regmap, REG_SE, tscadc->reg_se_cache);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	spin_unlock_irqrestore(&tscadc->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) EXPORT_SYMBOL_GPL(am335x_tsc_se_adc_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) void am335x_tsc_se_clr(struct ti_tscadc_dev *tscadc, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	spin_lock_irqsave(&tscadc->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	tscadc->reg_se_cache &= ~val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	regmap_write(tscadc->regmap, REG_SE, tscadc->reg_se_cache);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	spin_unlock_irqrestore(&tscadc->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) EXPORT_SYMBOL_GPL(am335x_tsc_se_clr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static void tscadc_idle_config(struct ti_tscadc_dev *tscadc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	unsigned int idleconfig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	idleconfig = STEPCONFIG_YNN | STEPCONFIG_INM_ADCREFM |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 			STEPCONFIG_INP_ADCREFM | STEPCONFIG_YPN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	regmap_write(tscadc->regmap, REG_IDLECONFIG, idleconfig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static	int ti_tscadc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	struct ti_tscadc_dev	*tscadc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	struct resource		*res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	struct clk		*clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	struct device_node	*node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	struct mfd_cell		*cell;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	struct property         *prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	const __be32            *cur;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	u32			val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	int			err, ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	int			clock_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	int			tsc_wires = 0, adc_channels = 0, total_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	int			readouts = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	if (!pdev->dev.of_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		dev_err(&pdev->dev, "Could not find valid DT data.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	node = of_get_child_by_name(pdev->dev.of_node, "tsc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	of_property_read_u32(node, "ti,wires", &tsc_wires);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	of_property_read_u32(node, "ti,coordiante-readouts", &readouts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	node = of_get_child_by_name(pdev->dev.of_node, "adc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	of_property_for_each_u32(node, "ti,adc-channels", prop, cur, val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		adc_channels++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		if (val > 7) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 			dev_err(&pdev->dev, " PIN numbers are 0..7 (not %d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 					val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	total_channels = tsc_wires + adc_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	if (total_channels > 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		dev_err(&pdev->dev, "Number of i/p channels more than 8\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	if (total_channels == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		dev_err(&pdev->dev, "Need atleast one channel.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	if (readouts * 2 + 2 + adc_channels > 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		dev_err(&pdev->dev, "Too many step configurations requested\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	/* Allocate memory for device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	tscadc = devm_kzalloc(&pdev->dev, sizeof(*tscadc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	if (!tscadc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	tscadc->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	err = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		dev_err(&pdev->dev, "no irq ID is specified.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		goto ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	} else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		tscadc->irq = err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	tscadc->tscadc_base = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	if (IS_ERR(tscadc->tscadc_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		return PTR_ERR(tscadc->tscadc_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	tscadc->tscadc_phys_base = res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	tscadc->regmap = devm_regmap_init_mmio(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 			tscadc->tscadc_base, &tscadc_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	if (IS_ERR(tscadc->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		dev_err(&pdev->dev, "regmap init failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		err = PTR_ERR(tscadc->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		goto ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	spin_lock_init(&tscadc->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	init_waitqueue_head(&tscadc->reg_se_wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	pm_runtime_enable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	pm_runtime_get_sync(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	 * The TSC_ADC_Subsystem has 2 clock domains
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	 * OCP_CLK and ADC_CLK.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	 * The ADC clock is expected to run at target of 3MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	 * and expected to capture 12-bit data at a rate of 200 KSPS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	 * The TSC_ADC_SS controller design assumes the OCP clock is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	 * at least 6x faster than the ADC clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	clk = devm_clk_get(&pdev->dev, "adc_tsc_fck");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		dev_err(&pdev->dev, "failed to get TSC fck\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		err = PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		goto err_disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	clock_rate = clk_get_rate(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	tscadc->clk_div = clock_rate / ADC_CLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	/* TSCADC_CLKDIV needs to be configured to the value minus 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	tscadc->clk_div--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	regmap_write(tscadc->regmap, REG_CLKDIV, tscadc->clk_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	/* Set the control register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	ctrl = CNTRLREG_STEPCONFIGWRT |	CNTRLREG_STEPID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	regmap_write(tscadc->regmap, REG_CTRL, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	/* Set register bits for Idle Config Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	if (tsc_wires > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		tscadc->tsc_wires = tsc_wires;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		if (tsc_wires == 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 			ctrl |= CNTRLREG_5WIRE | CNTRLREG_TSCENB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 			ctrl |= CNTRLREG_4WIRE | CNTRLREG_TSCENB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		tscadc_idle_config(tscadc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	/* Enable the TSC module enable bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	ctrl |= CNTRLREG_TSCSSENB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	regmap_write(tscadc->regmap, REG_CTRL, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	tscadc->used_cells = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	tscadc->tsc_cell = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	tscadc->adc_cell = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	/* TSC Cell */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	if (tsc_wires > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		tscadc->tsc_cell = tscadc->used_cells;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		cell = &tscadc->cells[tscadc->used_cells++];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		cell->name = "TI-am335x-tsc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		cell->of_compatible = "ti,am3359-tsc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		cell->platform_data = &tscadc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		cell->pdata_size = sizeof(tscadc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	/* ADC Cell */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	if (adc_channels > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		tscadc->adc_cell = tscadc->used_cells;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		cell = &tscadc->cells[tscadc->used_cells++];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		cell->name = "TI-am335x-adc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		cell->of_compatible = "ti,am3359-adc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		cell->platform_data = &tscadc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		cell->pdata_size = sizeof(tscadc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	err = mfd_add_devices(&pdev->dev, PLATFORM_DEVID_AUTO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 			      tscadc->cells, tscadc->used_cells, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 			      0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		goto err_disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	platform_set_drvdata(pdev, tscadc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) err_disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	pm_runtime_put_sync(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) ret:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static int ti_tscadc_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	struct ti_tscadc_dev	*tscadc = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	regmap_write(tscadc->regmap, REG_SE, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	pm_runtime_put_sync(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	mfd_remove_devices(tscadc->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static int __maybe_unused ti_tscadc_can_wakeup(struct device *dev, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	return device_may_wakeup(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static int __maybe_unused tscadc_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	struct ti_tscadc_dev	*tscadc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	regmap_write(tscadc->regmap, REG_SE, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	if (device_for_each_child(dev, NULL, ti_tscadc_can_wakeup)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 		u32 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 		regmap_read(tscadc->regmap, REG_CTRL, &ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 		ctrl &= ~(CNTRLREG_POWERDOWN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 		ctrl |= CNTRLREG_TSCSSENB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 		regmap_write(tscadc->regmap, REG_CTRL, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	pm_runtime_put_sync(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static int __maybe_unused tscadc_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	struct ti_tscadc_dev	*tscadc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	u32 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	pm_runtime_get_sync(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	/* context restore */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	ctrl = CNTRLREG_STEPCONFIGWRT |	CNTRLREG_STEPID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	regmap_write(tscadc->regmap, REG_CTRL, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	if (tscadc->tsc_cell != -1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 		if (tscadc->tsc_wires == 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 			ctrl |= CNTRLREG_5WIRE | CNTRLREG_TSCENB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 			ctrl |= CNTRLREG_4WIRE | CNTRLREG_TSCENB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 		tscadc_idle_config(tscadc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	ctrl |= CNTRLREG_TSCSSENB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	regmap_write(tscadc->regmap, REG_CTRL, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	regmap_write(tscadc->regmap, REG_CLKDIV, tscadc->clk_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static SIMPLE_DEV_PM_OPS(tscadc_pm_ops, tscadc_suspend, tscadc_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) static const struct of_device_id ti_tscadc_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	{ .compatible = "ti,am3359-tscadc", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) MODULE_DEVICE_TABLE(of, ti_tscadc_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static struct platform_driver ti_tscadc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 		.name   = "ti_am3359-tscadc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 		.pm	= &tscadc_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 		.of_match_table = ti_tscadc_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	.probe	= ti_tscadc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	.remove	= ti_tscadc_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) module_platform_driver(ti_tscadc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) MODULE_DESCRIPTION("TI touchscreen / ADC MFD controller driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) MODULE_AUTHOR("Rachna Patil <rachna@ti.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) MODULE_LICENSE("GPL");