^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Toshiba TC6393XB SoC support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright(c) 2005-2006 Chris Humbert
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright(c) 2005 Dirk Opfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright(c) 2005 Ian Molton <spyro@f2s.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright(c) 2007 Dmitry Baryshkov
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Based on code written by Sharp/Lineo for 2.4 kernels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Based on locomo.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/mfd/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/mfd/tmio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/mfd/tc6393xb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SCR_REVID 0x08 /* b Revision ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SCR_ISR 0x50 /* b Interrupt Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SCR_IMR 0x52 /* b Interrupt Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SCR_IRR 0x54 /* b Interrupt Routing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SCR_GPER 0x60 /* w GP Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SCR_GPI_SR(i) (0x64 + (i)) /* b3 GPI Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SCR_GPI_IMR(i) (0x68 + (i)) /* b3 GPI INT Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SCR_GPI_EDER(i) (0x6c + (i)) /* b3 GPI Edge Detect Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SCR_GPI_LIR(i) (0x70 + (i)) /* b3 GPI Level Invert */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SCR_GPO_DSR(i) (0x78 + (i)) /* b3 GPO Data Set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SCR_GPO_DOECR(i) (0x7c + (i)) /* b3 GPO Data OE Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SCR_GP_IARCR(i) (0x80 + (i)) /* b3 GP Internal Active Register Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SCR_GP_IARLCR(i) (0x84 + (i)) /* b3 GP INTERNAL Active Register Level Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SCR_GPI_BCR(i) (0x88 + (i)) /* b3 GPI Buffer Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SCR_GPA_IARCR 0x8c /* w GPa Internal Active Register Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SCR_GPA_IARLCR 0x90 /* w GPa Internal Active Register Level Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SCR_GPA_BCR 0x94 /* w GPa Buffer Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SCR_CCR 0x98 /* w Clock Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SCR_PLL2CR 0x9a /* w PLL2 Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SCR_PLL1CR 0x9c /* l PLL1 Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SCR_DIARCR 0xa0 /* b Device Internal Active Register Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SCR_DBOCR 0xa1 /* b Device Buffer Off Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SCR_FER 0xe0 /* b Function Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SCR_MCR 0xe4 /* w Mode Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SCR_CONFIG 0xfc /* b Configuration Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SCR_DEBUG 0xff /* b Debug */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SCR_CCR_CK32K BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SCR_CCR_USBCK BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SCR_CCR_UNK1 BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SCR_CCR_MCLK_MASK (7 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SCR_CCR_MCLK_OFF (0 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SCR_CCR_MCLK_12 (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SCR_CCR_MCLK_24 (2 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SCR_CCR_MCLK_48 (3 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SCR_CCR_HCLK_MASK (3 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SCR_CCR_HCLK_24 (0 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SCR_CCR_HCLK_48 (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SCR_FER_USBEN BIT(0) /* USB host enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SCR_FER_LCDCVEN BIT(1) /* polysilicon TFT enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SCR_FER_SLCDEN BIT(2) /* SLCD enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SCR_MCR_RDY_MASK (3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SCR_MCR_RDY_OPENDRAIN (0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SCR_MCR_RDY_TRISTATE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SCR_MCR_RDY_PUSHPULL (2 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SCR_MCR_RDY_UNK BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define SCR_MCR_RDY_EN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define SCR_MCR_INT_MASK (3 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define SCR_MCR_INT_OPENDRAIN (0 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define SCR_MCR_INT_TRISTATE (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define SCR_MCR_INT_PUSHPULL (2 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define SCR_MCR_INT_UNK BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SCR_MCR_INT_EN BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* bits 8 - 16 are unknown */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define TC_GPIO_BIT(i) (1 << (i & 0x7))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /*--------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct tc6393xb {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) void __iomem *scr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct gpio_chip gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct clk *clk; /* 3,6 Mhz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) raw_spinlock_t lock; /* protects RMW cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) u8 fer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) u16 ccr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) u8 gpi_bcr[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) u8 gpo_dsr[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) u8 gpo_doecr[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) } suspend_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct resource rscr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct resource *iomem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) int irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) TC6393XB_CELL_NAND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) TC6393XB_CELL_MMC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) TC6393XB_CELL_OHCI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) TC6393XB_CELL_FB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /*--------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static int tc6393xb_nand_enable(struct platform_device *nand)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct tc6393xb *tc6393xb = dev_get_drvdata(nand->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) raw_spin_lock_irqsave(&tc6393xb->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* SMD buffer on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) dev_dbg(nand->dev.parent, "SMD buffer on\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) tmio_iowrite8(0xff, tc6393xb->scr + SCR_GPI_BCR(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) raw_spin_unlock_irqrestore(&tc6393xb->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static struct resource tc6393xb_nand_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .start = 0x1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .end = 0x1007,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .start = 0x0100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .end = 0x01ff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .start = IRQ_TC6393_NAND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .end = IRQ_TC6393_NAND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static struct resource tc6393xb_mmc_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .start = 0x800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .end = 0x9ff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .start = IRQ_TC6393_MMC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .end = IRQ_TC6393_MMC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static const struct resource tc6393xb_ohci_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .start = 0x3000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .end = 0x31ff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .start = 0x0300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .end = 0x03ff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .start = 0x010000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .end = 0x017fff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .start = 0x018000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .end = 0x01ffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .start = IRQ_TC6393_OHCI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .end = IRQ_TC6393_OHCI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static struct resource tc6393xb_fb_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .start = 0x5000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .end = 0x51ff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .start = 0x0500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .end = 0x05ff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .start = 0x100000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .end = 0x1fffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .start = IRQ_TC6393_FB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .end = IRQ_TC6393_FB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static int tc6393xb_ohci_enable(struct platform_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) struct tc6393xb *tc6393xb = dev_get_drvdata(dev->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) u16 ccr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) u8 fer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) raw_spin_lock_irqsave(&tc6393xb->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) ccr = tmio_ioread16(tc6393xb->scr + SCR_CCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) ccr |= SCR_CCR_USBCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) tmio_iowrite16(ccr, tc6393xb->scr + SCR_CCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) fer = tmio_ioread8(tc6393xb->scr + SCR_FER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) fer |= SCR_FER_USBEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) tmio_iowrite8(fer, tc6393xb->scr + SCR_FER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) raw_spin_unlock_irqrestore(&tc6393xb->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static int tc6393xb_ohci_disable(struct platform_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) struct tc6393xb *tc6393xb = dev_get_drvdata(dev->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) u16 ccr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) u8 fer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) raw_spin_lock_irqsave(&tc6393xb->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) fer = tmio_ioread8(tc6393xb->scr + SCR_FER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) fer &= ~SCR_FER_USBEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) tmio_iowrite8(fer, tc6393xb->scr + SCR_FER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) ccr = tmio_ioread16(tc6393xb->scr + SCR_CCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) ccr &= ~SCR_CCR_USBCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) tmio_iowrite16(ccr, tc6393xb->scr + SCR_CCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) raw_spin_unlock_irqrestore(&tc6393xb->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static int tc6393xb_ohci_suspend(struct platform_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) struct tc6393xb_platform_data *tcpd = dev_get_platdata(dev->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /* We can't properly store/restore OHCI state, so fail here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (tcpd->resume_restore)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) return tc6393xb_ohci_disable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) static int tc6393xb_fb_enable(struct platform_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) struct tc6393xb *tc6393xb = dev_get_drvdata(dev->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) u16 ccr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) raw_spin_lock_irqsave(&tc6393xb->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) ccr = tmio_ioread16(tc6393xb->scr + SCR_CCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) ccr &= ~SCR_CCR_MCLK_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) ccr |= SCR_CCR_MCLK_48;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) tmio_iowrite16(ccr, tc6393xb->scr + SCR_CCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) raw_spin_unlock_irqrestore(&tc6393xb->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static int tc6393xb_fb_disable(struct platform_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) struct tc6393xb *tc6393xb = dev_get_drvdata(dev->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) u16 ccr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) raw_spin_lock_irqsave(&tc6393xb->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) ccr = tmio_ioread16(tc6393xb->scr + SCR_CCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) ccr &= ~SCR_CCR_MCLK_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) ccr |= SCR_CCR_MCLK_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) tmio_iowrite16(ccr, tc6393xb->scr + SCR_CCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) raw_spin_unlock_irqrestore(&tc6393xb->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) int tc6393xb_lcd_set_power(struct platform_device *fb, bool on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) struct tc6393xb *tc6393xb = dev_get_drvdata(fb->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) u8 fer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) raw_spin_lock_irqsave(&tc6393xb->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) fer = ioread8(tc6393xb->scr + SCR_FER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) if (on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) fer |= SCR_FER_SLCDEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) fer &= ~SCR_FER_SLCDEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) iowrite8(fer, tc6393xb->scr + SCR_FER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) raw_spin_unlock_irqrestore(&tc6393xb->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) EXPORT_SYMBOL(tc6393xb_lcd_set_power);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) int tc6393xb_lcd_mode(struct platform_device *fb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) const struct fb_videomode *mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) struct tc6393xb *tc6393xb = dev_get_drvdata(fb->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) raw_spin_lock_irqsave(&tc6393xb->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) iowrite16(mode->pixclock, tc6393xb->scr + SCR_PLL1CR + 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) iowrite16(mode->pixclock >> 16, tc6393xb->scr + SCR_PLL1CR + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) raw_spin_unlock_irqrestore(&tc6393xb->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) EXPORT_SYMBOL(tc6393xb_lcd_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static int tc6393xb_mmc_enable(struct platform_device *mmc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) struct tc6393xb *tc6393xb = dev_get_drvdata(mmc->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) tmio_core_mmc_enable(tc6393xb->scr + 0x200, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) tc6393xb_mmc_resources[0].start & 0xfffe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static int tc6393xb_mmc_resume(struct platform_device *mmc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) struct tc6393xb *tc6393xb = dev_get_drvdata(mmc->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) tmio_core_mmc_resume(tc6393xb->scr + 0x200, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) tc6393xb_mmc_resources[0].start & 0xfffe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) static void tc6393xb_mmc_pwr(struct platform_device *mmc, int state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) struct tc6393xb *tc6393xb = dev_get_drvdata(mmc->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) tmio_core_mmc_pwr(tc6393xb->scr + 0x200, 0, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static void tc6393xb_mmc_clk_div(struct platform_device *mmc, int state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) struct tc6393xb *tc6393xb = dev_get_drvdata(mmc->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) tmio_core_mmc_clk_div(tc6393xb->scr + 0x200, 0, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) static struct tmio_mmc_data tc6393xb_mmc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .hclk = 24000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .set_pwr = tc6393xb_mmc_pwr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .set_clk_div = tc6393xb_mmc_clk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) static struct mfd_cell tc6393xb_cells[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) [TC6393XB_CELL_NAND] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .name = "tmio-nand",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .enable = tc6393xb_nand_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .num_resources = ARRAY_SIZE(tc6393xb_nand_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .resources = tc6393xb_nand_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) [TC6393XB_CELL_MMC] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .name = "tmio-mmc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .enable = tc6393xb_mmc_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .resume = tc6393xb_mmc_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .platform_data = &tc6393xb_mmc_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .pdata_size = sizeof(tc6393xb_mmc_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .num_resources = ARRAY_SIZE(tc6393xb_mmc_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) .resources = tc6393xb_mmc_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) [TC6393XB_CELL_OHCI] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .name = "tmio-ohci",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .num_resources = ARRAY_SIZE(tc6393xb_ohci_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) .resources = tc6393xb_ohci_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) .enable = tc6393xb_ohci_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) .suspend = tc6393xb_ohci_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) .resume = tc6393xb_ohci_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) .disable = tc6393xb_ohci_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) [TC6393XB_CELL_FB] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) .name = "tmio-fb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) .num_resources = ARRAY_SIZE(tc6393xb_fb_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) .resources = tc6393xb_fb_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) .enable = tc6393xb_fb_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) .suspend = tc6393xb_fb_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) .resume = tc6393xb_fb_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) .disable = tc6393xb_fb_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) /*--------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) static int tc6393xb_gpio_get(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) struct tc6393xb *tc6393xb = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) /* XXX: does dsr also represent inputs? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) return !!(tmio_ioread8(tc6393xb->scr + SCR_GPO_DSR(offset / 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) & TC_GPIO_BIT(offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) static void __tc6393xb_gpio_set(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) unsigned offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) struct tc6393xb *tc6393xb = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) u8 dsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) dsr = tmio_ioread8(tc6393xb->scr + SCR_GPO_DSR(offset / 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) if (value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) dsr |= TC_GPIO_BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) dsr &= ~TC_GPIO_BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) tmio_iowrite8(dsr, tc6393xb->scr + SCR_GPO_DSR(offset / 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) static void tc6393xb_gpio_set(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) unsigned offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) struct tc6393xb *tc6393xb = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) raw_spin_lock_irqsave(&tc6393xb->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) __tc6393xb_gpio_set(chip, offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) raw_spin_unlock_irqrestore(&tc6393xb->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) static int tc6393xb_gpio_direction_input(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) struct tc6393xb *tc6393xb = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) u8 doecr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) raw_spin_lock_irqsave(&tc6393xb->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) doecr = tmio_ioread8(tc6393xb->scr + SCR_GPO_DOECR(offset / 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) doecr &= ~TC_GPIO_BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) tmio_iowrite8(doecr, tc6393xb->scr + SCR_GPO_DOECR(offset / 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) raw_spin_unlock_irqrestore(&tc6393xb->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) static int tc6393xb_gpio_direction_output(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) unsigned offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) struct tc6393xb *tc6393xb = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) u8 doecr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) raw_spin_lock_irqsave(&tc6393xb->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) __tc6393xb_gpio_set(chip, offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) doecr = tmio_ioread8(tc6393xb->scr + SCR_GPO_DOECR(offset / 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) doecr |= TC_GPIO_BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) tmio_iowrite8(doecr, tc6393xb->scr + SCR_GPO_DOECR(offset / 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) raw_spin_unlock_irqrestore(&tc6393xb->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) static int tc6393xb_register_gpio(struct tc6393xb *tc6393xb, int gpio_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) tc6393xb->gpio.label = "tc6393xb";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) tc6393xb->gpio.base = gpio_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) tc6393xb->gpio.ngpio = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) tc6393xb->gpio.set = tc6393xb_gpio_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) tc6393xb->gpio.get = tc6393xb_gpio_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) tc6393xb->gpio.direction_input = tc6393xb_gpio_direction_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) tc6393xb->gpio.direction_output = tc6393xb_gpio_direction_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) return gpiochip_add_data(&tc6393xb->gpio, tc6393xb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) /*--------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) static void tc6393xb_irq(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) struct tc6393xb *tc6393xb = irq_desc_get_handler_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) unsigned int isr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) unsigned int i, irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) irq_base = tc6393xb->irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) while ((isr = tmio_ioread8(tc6393xb->scr + SCR_ISR) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) ~tmio_ioread8(tc6393xb->scr + SCR_IMR)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) for (i = 0; i < TC6393XB_NR_IRQS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) if (isr & (1 << i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) generic_handle_irq(irq_base + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) static void tc6393xb_irq_ack(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) static void tc6393xb_irq_mask(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) struct tc6393xb *tc6393xb = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) u8 imr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) raw_spin_lock_irqsave(&tc6393xb->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) imr = tmio_ioread8(tc6393xb->scr + SCR_IMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) imr |= 1 << (data->irq - tc6393xb->irq_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) tmio_iowrite8(imr, tc6393xb->scr + SCR_IMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) raw_spin_unlock_irqrestore(&tc6393xb->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) static void tc6393xb_irq_unmask(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) struct tc6393xb *tc6393xb = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) u8 imr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) raw_spin_lock_irqsave(&tc6393xb->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) imr = tmio_ioread8(tc6393xb->scr + SCR_IMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) imr &= ~(1 << (data->irq - tc6393xb->irq_base));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) tmio_iowrite8(imr, tc6393xb->scr + SCR_IMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) raw_spin_unlock_irqrestore(&tc6393xb->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) static struct irq_chip tc6393xb_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) .name = "tc6393xb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) .irq_ack = tc6393xb_irq_ack,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) .irq_mask = tc6393xb_irq_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) .irq_unmask = tc6393xb_irq_unmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) static void tc6393xb_attach_irq(struct platform_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) struct tc6393xb *tc6393xb = platform_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) unsigned int irq, irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) irq_base = tc6393xb->irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) for (irq = irq_base; irq < irq_base + TC6393XB_NR_IRQS; irq++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) irq_set_chip_and_handler(irq, &tc6393xb_chip, handle_edge_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) irq_set_chip_data(irq, tc6393xb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) irq_set_irq_type(tc6393xb->irq, IRQ_TYPE_EDGE_FALLING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) irq_set_chained_handler_and_data(tc6393xb->irq, tc6393xb_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) tc6393xb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) static void tc6393xb_detach_irq(struct platform_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) struct tc6393xb *tc6393xb = platform_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) unsigned int irq, irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) irq_set_chained_handler_and_data(tc6393xb->irq, NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) irq_base = tc6393xb->irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) for (irq = irq_base; irq < irq_base + TC6393XB_NR_IRQS; irq++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) irq_set_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) irq_set_chip(irq, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) irq_set_chip_data(irq, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) /*--------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) static int tc6393xb_probe(struct platform_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) struct tc6393xb_platform_data *tcpd = dev_get_platdata(&dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) struct tc6393xb *tc6393xb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) struct resource *iomem, *rscr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) iomem = platform_get_resource(dev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) if (!iomem)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) tc6393xb = kzalloc(sizeof *tc6393xb, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) if (!tc6393xb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) goto err_kzalloc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) raw_spin_lock_init(&tc6393xb->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) platform_set_drvdata(dev, tc6393xb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) ret = platform_get_irq(dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) if (ret >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) tc6393xb->irq = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) goto err_noirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) tc6393xb->iomem = iomem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) tc6393xb->irq_base = tcpd->irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) tc6393xb->clk = clk_get(&dev->dev, "CLK_CK3P6MI");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) if (IS_ERR(tc6393xb->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) ret = PTR_ERR(tc6393xb->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) goto err_clk_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) rscr = &tc6393xb->rscr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) rscr->name = "tc6393xb-core";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) rscr->start = iomem->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) rscr->end = iomem->start + 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) rscr->flags = IORESOURCE_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) ret = request_resource(iomem, rscr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) goto err_request_scr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) tc6393xb->scr = ioremap(rscr->start, resource_size(rscr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) if (!tc6393xb->scr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) goto err_ioremap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) ret = clk_prepare_enable(tc6393xb->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) goto err_clk_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) ret = tcpd->enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) goto err_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) iowrite8(0, tc6393xb->scr + SCR_FER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) iowrite16(tcpd->scr_pll2cr, tc6393xb->scr + SCR_PLL2CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) iowrite16(SCR_CCR_UNK1 | SCR_CCR_HCLK_48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) tc6393xb->scr + SCR_CCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) iowrite16(SCR_MCR_RDY_OPENDRAIN | SCR_MCR_RDY_UNK | SCR_MCR_RDY_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) SCR_MCR_INT_OPENDRAIN | SCR_MCR_INT_UNK | SCR_MCR_INT_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) BIT(15), tc6393xb->scr + SCR_MCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) iowrite16(tcpd->scr_gper, tc6393xb->scr + SCR_GPER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) iowrite8(0, tc6393xb->scr + SCR_IRR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) iowrite8(0xbf, tc6393xb->scr + SCR_IMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) printk(KERN_INFO "Toshiba tc6393xb revision %d at 0x%08lx, irq %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) tmio_ioread8(tc6393xb->scr + SCR_REVID),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) (unsigned long) iomem->start, tc6393xb->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) tc6393xb->gpio.base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) if (tcpd->gpio_base >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) ret = tc6393xb_register_gpio(tc6393xb, tcpd->gpio_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) goto err_gpio_add;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) tc6393xb_attach_irq(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) if (tcpd->setup) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) ret = tcpd->setup(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) goto err_setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) tc6393xb_cells[TC6393XB_CELL_NAND].platform_data = tcpd->nand_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) tc6393xb_cells[TC6393XB_CELL_NAND].pdata_size =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) sizeof(*tcpd->nand_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) tc6393xb_cells[TC6393XB_CELL_FB].platform_data = tcpd->fb_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) tc6393xb_cells[TC6393XB_CELL_FB].pdata_size = sizeof(*tcpd->fb_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) ret = mfd_add_devices(&dev->dev, dev->id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) tc6393xb_cells, ARRAY_SIZE(tc6393xb_cells),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) iomem, tcpd->irq_base, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) if (tcpd->teardown)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) tcpd->teardown(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) err_setup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) tc6393xb_detach_irq(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) err_gpio_add:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) if (tc6393xb->gpio.base != -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) gpiochip_remove(&tc6393xb->gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) tcpd->disable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) err_enable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) clk_disable_unprepare(tc6393xb->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) err_clk_enable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) iounmap(tc6393xb->scr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) err_ioremap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) release_resource(&tc6393xb->rscr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) err_request_scr:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) clk_put(tc6393xb->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) err_noirq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) err_clk_get:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) kfree(tc6393xb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) err_kzalloc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) static int tc6393xb_remove(struct platform_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) struct tc6393xb_platform_data *tcpd = dev_get_platdata(&dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) struct tc6393xb *tc6393xb = platform_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) mfd_remove_devices(&dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) if (tcpd->teardown)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) tcpd->teardown(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) tc6393xb_detach_irq(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) if (tc6393xb->gpio.base != -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) gpiochip_remove(&tc6393xb->gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) ret = tcpd->disable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) clk_disable_unprepare(tc6393xb->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) iounmap(tc6393xb->scr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) release_resource(&tc6393xb->rscr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) clk_put(tc6393xb->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) kfree(tc6393xb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) static int tc6393xb_suspend(struct platform_device *dev, pm_message_t state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) struct tc6393xb_platform_data *tcpd = dev_get_platdata(&dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) struct tc6393xb *tc6393xb = platform_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) tc6393xb->suspend_state.ccr = ioread16(tc6393xb->scr + SCR_CCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) tc6393xb->suspend_state.fer = ioread8(tc6393xb->scr + SCR_FER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) for (i = 0; i < 3; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) tc6393xb->suspend_state.gpo_dsr[i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) ioread8(tc6393xb->scr + SCR_GPO_DSR(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) tc6393xb->suspend_state.gpo_doecr[i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) ioread8(tc6393xb->scr + SCR_GPO_DOECR(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) tc6393xb->suspend_state.gpi_bcr[i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) ioread8(tc6393xb->scr + SCR_GPI_BCR(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) ret = tcpd->suspend(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) clk_disable_unprepare(tc6393xb->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) static int tc6393xb_resume(struct platform_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) struct tc6393xb_platform_data *tcpd = dev_get_platdata(&dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) struct tc6393xb *tc6393xb = platform_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) ret = clk_prepare_enable(tc6393xb->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) ret = tcpd->resume(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) if (!tcpd->resume_restore)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) iowrite8(tc6393xb->suspend_state.fer, tc6393xb->scr + SCR_FER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) iowrite16(tcpd->scr_pll2cr, tc6393xb->scr + SCR_PLL2CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) iowrite16(tc6393xb->suspend_state.ccr, tc6393xb->scr + SCR_CCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) iowrite16(SCR_MCR_RDY_OPENDRAIN | SCR_MCR_RDY_UNK | SCR_MCR_RDY_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) SCR_MCR_INT_OPENDRAIN | SCR_MCR_INT_UNK | SCR_MCR_INT_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) BIT(15), tc6393xb->scr + SCR_MCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) iowrite16(tcpd->scr_gper, tc6393xb->scr + SCR_GPER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) iowrite8(0, tc6393xb->scr + SCR_IRR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) iowrite8(0xbf, tc6393xb->scr + SCR_IMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) for (i = 0; i < 3; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) iowrite8(tc6393xb->suspend_state.gpo_dsr[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) tc6393xb->scr + SCR_GPO_DSR(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) iowrite8(tc6393xb->suspend_state.gpo_doecr[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) tc6393xb->scr + SCR_GPO_DOECR(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) iowrite8(tc6393xb->suspend_state.gpi_bcr[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) tc6393xb->scr + SCR_GPI_BCR(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) #define tc6393xb_suspend NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) #define tc6393xb_resume NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) static struct platform_driver tc6393xb_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) .probe = tc6393xb_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) .remove = tc6393xb_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) .suspend = tc6393xb_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) .resume = tc6393xb_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) .name = "tc6393xb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) static int __init tc6393xb_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) return platform_driver_register(&tc6393xb_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) static void __exit tc6393xb_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) platform_driver_unregister(&tc6393xb_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) subsys_initcall(tc6393xb_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) module_exit(tc6393xb_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) MODULE_AUTHOR("Ian Molton, Dmitry Baryshkov and Dirk Opfer");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) MODULE_DESCRIPTION("tc6393xb Toshiba Mobile IO Controller");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) MODULE_ALIAS("platform:tc6393xb");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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