^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Toshiba T7L66XB core mfd support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (c) 2005, 2007, 2008 Ian Molton
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (c) 2008 Dmitry Baryshkov
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * T7L66 features:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Supported in this driver:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * SD/MMC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * SM/NAND flash controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * As yet not supported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * GPIO interface (on NAND pins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * Serial interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * TFT 'interface converter'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * PCMCIA interface logic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/mfd/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/mfd/tmio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/mfd/t7l66xb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) T7L66XB_CELL_NAND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) T7L66XB_CELL_MMC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static const struct resource t7l66xb_mmc_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) .start = 0x800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) .end = 0x9ff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) .start = IRQ_T7L66XB_MMC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) .end = IRQ_T7L66XB_MMC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SCR_REVID 0x08 /* b Revision ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SCR_IMR 0x42 /* b Interrupt Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SCR_DEV_CTL 0xe0 /* b Device control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SCR_ISR 0xe1 /* b Interrupt Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SCR_GPO_OC 0xf0 /* b GPO output control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SCR_GPO_OS 0xf1 /* b GPO output enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SCR_GPI_S 0xf2 /* w GPI status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SCR_APDC 0xf8 /* b Active pullup down ctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SCR_DEV_CTL_USB BIT(0) /* USB enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SCR_DEV_CTL_MMC BIT(1) /* MMC enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /*--------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct t7l66xb {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) void __iomem *scr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* Lock to protect registers requiring read/modify/write ops. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) raw_spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct resource rscr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct clk *clk48m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct clk *clk32k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) int irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /*--------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static int t7l66xb_mmc_enable(struct platform_device *mmc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct t7l66xb *t7l66xb = dev_get_drvdata(mmc->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) u8 dev_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) ret = clk_prepare_enable(t7l66xb->clk32k);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) raw_spin_lock_irqsave(&t7l66xb->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) dev_ctl = tmio_ioread8(t7l66xb->scr + SCR_DEV_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) dev_ctl |= SCR_DEV_CTL_MMC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) tmio_iowrite8(dev_ctl, t7l66xb->scr + SCR_DEV_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) raw_spin_unlock_irqrestore(&t7l66xb->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) tmio_core_mmc_enable(t7l66xb->scr + 0x200, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) t7l66xb_mmc_resources[0].start & 0xfffe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static int t7l66xb_mmc_disable(struct platform_device *mmc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct t7l66xb *t7l66xb = dev_get_drvdata(mmc->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) u8 dev_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) raw_spin_lock_irqsave(&t7l66xb->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) dev_ctl = tmio_ioread8(t7l66xb->scr + SCR_DEV_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) dev_ctl &= ~SCR_DEV_CTL_MMC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) tmio_iowrite8(dev_ctl, t7l66xb->scr + SCR_DEV_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) raw_spin_unlock_irqrestore(&t7l66xb->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) clk_disable_unprepare(t7l66xb->clk32k);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static void t7l66xb_mmc_pwr(struct platform_device *mmc, int state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct t7l66xb *t7l66xb = dev_get_drvdata(mmc->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) tmio_core_mmc_pwr(t7l66xb->scr + 0x200, 0, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static void t7l66xb_mmc_clk_div(struct platform_device *mmc, int state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct t7l66xb *t7l66xb = dev_get_drvdata(mmc->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) tmio_core_mmc_clk_div(t7l66xb->scr + 0x200, 0, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /*--------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static struct tmio_mmc_data t7166xb_mmc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .hclk = 24000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .set_pwr = t7l66xb_mmc_pwr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .set_clk_div = t7l66xb_mmc_clk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static const struct resource t7l66xb_nand_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .start = 0xc00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .end = 0xc07,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .start = 0x0100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .end = 0x01ff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .start = IRQ_T7L66XB_NAND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .end = IRQ_T7L66XB_NAND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static struct mfd_cell t7l66xb_cells[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) [T7L66XB_CELL_MMC] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .name = "tmio-mmc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .enable = t7l66xb_mmc_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .disable = t7l66xb_mmc_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .platform_data = &t7166xb_mmc_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .pdata_size = sizeof(t7166xb_mmc_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .num_resources = ARRAY_SIZE(t7l66xb_mmc_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .resources = t7l66xb_mmc_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) [T7L66XB_CELL_NAND] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .name = "tmio-nand",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .num_resources = ARRAY_SIZE(t7l66xb_nand_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .resources = t7l66xb_nand_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /*--------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /* Handle the T7L66XB interrupt mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static void t7l66xb_irq(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) struct t7l66xb *t7l66xb = irq_desc_get_handler_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) unsigned int isr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) unsigned int i, irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) irq_base = t7l66xb->irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) while ((isr = tmio_ioread8(t7l66xb->scr + SCR_ISR) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) ~tmio_ioread8(t7l66xb->scr + SCR_IMR)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) for (i = 0; i < T7L66XB_NR_IRQS; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (isr & (1 << i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) generic_handle_irq(irq_base + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static void t7l66xb_irq_mask(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) struct t7l66xb *t7l66xb = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) u8 imr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) raw_spin_lock_irqsave(&t7l66xb->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) imr = tmio_ioread8(t7l66xb->scr + SCR_IMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) imr |= 1 << (data->irq - t7l66xb->irq_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) tmio_iowrite8(imr, t7l66xb->scr + SCR_IMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) raw_spin_unlock_irqrestore(&t7l66xb->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static void t7l66xb_irq_unmask(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) struct t7l66xb *t7l66xb = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) u8 imr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) raw_spin_lock_irqsave(&t7l66xb->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) imr = tmio_ioread8(t7l66xb->scr + SCR_IMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) imr &= ~(1 << (data->irq - t7l66xb->irq_base));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) tmio_iowrite8(imr, t7l66xb->scr + SCR_IMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) raw_spin_unlock_irqrestore(&t7l66xb->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static struct irq_chip t7l66xb_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .name = "t7l66xb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .irq_ack = t7l66xb_irq_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) .irq_mask = t7l66xb_irq_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .irq_unmask = t7l66xb_irq_unmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /*--------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /* Install the IRQ handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static void t7l66xb_attach_irq(struct platform_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) struct t7l66xb *t7l66xb = platform_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) unsigned int irq, irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) irq_base = t7l66xb->irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) for (irq = irq_base; irq < irq_base + T7L66XB_NR_IRQS; irq++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) irq_set_chip_and_handler(irq, &t7l66xb_chip, handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) irq_set_chip_data(irq, t7l66xb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) irq_set_irq_type(t7l66xb->irq, IRQ_TYPE_EDGE_FALLING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) irq_set_chained_handler_and_data(t7l66xb->irq, t7l66xb_irq, t7l66xb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static void t7l66xb_detach_irq(struct platform_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) struct t7l66xb *t7l66xb = platform_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) unsigned int irq, irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) irq_base = t7l66xb->irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) irq_set_chained_handler_and_data(t7l66xb->irq, NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) for (irq = irq_base; irq < irq_base + T7L66XB_NR_IRQS; irq++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) irq_set_chip(irq, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) irq_set_chip_data(irq, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /*--------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static int t7l66xb_suspend(struct platform_device *dev, pm_message_t state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) struct t7l66xb *t7l66xb = platform_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) struct t7l66xb_platform_data *pdata = dev_get_platdata(&dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) if (pdata && pdata->suspend)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) pdata->suspend(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) clk_disable_unprepare(t7l66xb->clk48m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static int t7l66xb_resume(struct platform_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) struct t7l66xb *t7l66xb = platform_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) struct t7l66xb_platform_data *pdata = dev_get_platdata(&dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) ret = clk_prepare_enable(t7l66xb->clk48m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) if (pdata && pdata->resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) pdata->resume(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) tmio_core_mmc_enable(t7l66xb->scr + 0x200, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) t7l66xb_mmc_resources[0].start & 0xfffe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define t7l66xb_suspend NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define t7l66xb_resume NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) /*--------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static int t7l66xb_probe(struct platform_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) struct t7l66xb_platform_data *pdata = dev_get_platdata(&dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) struct t7l66xb *t7l66xb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) struct resource *iomem, *rscr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (!pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) iomem = platform_get_resource(dev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) if (!iomem)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) t7l66xb = kzalloc(sizeof *t7l66xb, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) if (!t7l66xb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) raw_spin_lock_init(&t7l66xb->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) platform_set_drvdata(dev, t7l66xb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) ret = platform_get_irq(dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) if (ret >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) t7l66xb->irq = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) goto err_noirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) t7l66xb->irq_base = pdata->irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) t7l66xb->clk32k = clk_get(&dev->dev, "CLK_CK32K");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) if (IS_ERR(t7l66xb->clk32k)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) ret = PTR_ERR(t7l66xb->clk32k);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) goto err_clk32k_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) t7l66xb->clk48m = clk_get(&dev->dev, "CLK_CK48M");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) if (IS_ERR(t7l66xb->clk48m)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) ret = PTR_ERR(t7l66xb->clk48m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) goto err_clk48m_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) rscr = &t7l66xb->rscr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) rscr->name = "t7l66xb-core";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) rscr->start = iomem->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) rscr->end = iomem->start + 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) rscr->flags = IORESOURCE_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) ret = request_resource(iomem, rscr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) goto err_request_scr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) t7l66xb->scr = ioremap(rscr->start, resource_size(rscr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) if (!t7l66xb->scr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) goto err_ioremap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) ret = clk_prepare_enable(t7l66xb->clk48m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) goto err_clk_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) if (pdata->enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) pdata->enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) /* Mask all interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) tmio_iowrite8(0xbf, t7l66xb->scr + SCR_IMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) printk(KERN_INFO "%s rev %d @ 0x%08lx, irq %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) dev->name, tmio_ioread8(t7l66xb->scr + SCR_REVID),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) (unsigned long)iomem->start, t7l66xb->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) t7l66xb_attach_irq(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) t7l66xb_cells[T7L66XB_CELL_NAND].platform_data = pdata->nand_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) t7l66xb_cells[T7L66XB_CELL_NAND].pdata_size = sizeof(*pdata->nand_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) ret = mfd_add_devices(&dev->dev, dev->id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) t7l66xb_cells, ARRAY_SIZE(t7l66xb_cells),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) iomem, t7l66xb->irq_base, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) t7l66xb_detach_irq(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) clk_disable_unprepare(t7l66xb->clk48m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) err_clk_enable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) iounmap(t7l66xb->scr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) err_ioremap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) release_resource(&t7l66xb->rscr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) err_request_scr:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) clk_put(t7l66xb->clk48m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) err_clk48m_get:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) clk_put(t7l66xb->clk32k);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) err_clk32k_get:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) err_noirq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) kfree(t7l66xb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) static int t7l66xb_remove(struct platform_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) struct t7l66xb_platform_data *pdata = dev_get_platdata(&dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) struct t7l66xb *t7l66xb = platform_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) ret = pdata->disable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) clk_disable_unprepare(t7l66xb->clk48m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) clk_put(t7l66xb->clk48m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) clk_disable_unprepare(t7l66xb->clk32k);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) clk_put(t7l66xb->clk32k);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) t7l66xb_detach_irq(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) iounmap(t7l66xb->scr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) release_resource(&t7l66xb->rscr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) mfd_remove_devices(&dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) kfree(t7l66xb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) static struct platform_driver t7l66xb_platform_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .name = "t7l66xb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) .suspend = t7l66xb_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) .resume = t7l66xb_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) .probe = t7l66xb_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .remove = t7l66xb_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) /*--------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) module_platform_driver(t7l66xb_platform_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) MODULE_DESCRIPTION("Toshiba T7L66XB core driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) MODULE_AUTHOR("Ian Molton");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) MODULE_ALIAS("platform:t7l66xb");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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