Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Core driver for STw4810/STw4811
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2013 ST-Ericsson SA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Written on behalf of Linaro for ST-Ericsson
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Author: Linus Walleij <linus.walleij@linaro.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/mfd/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/mfd/stw481x.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  * This driver can only access the non-USB portions of STw4811, the register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  * range 0x00-0x10 dealing with USB is bound to the two special I2C pins used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  * for USB control.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) /* Registers inside the power control address space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define STW_PC_VCORE_SEL	0x05U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define STW_PC_VAUX_SEL		0x06U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define STW_PC_VPLL_SEL		0x07U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33)  * stw481x_get_pctl_reg() - get a power control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34)  * @stw481x: handle to the stw481x chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35)  * @reg: power control register to fetch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37)  * The power control registers is a set of one-time-programmable registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38)  * in its own register space, accessed by writing addess bits to these
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39)  * two registers: bits 7,6,5 of PCTL_REG_LO corresponds to the 3 LSBs of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40)  * the address and bits 8,9 of PCTL_REG_HI corresponds to the 2 MSBs of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41)  * the address, forming an address space of 5 bits, i.e. 32 registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42)  * 0x00 ... 0x1f can be obtained.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) static int stw481x_get_pctl_reg(struct stw481x *stw481x, u8 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	u8 msb = (reg >> 3) & 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	u8 lsb = (reg << 5) & 0xe0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	u8 vrfy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	ret = regmap_write(stw481x->map, STW_PCTL_REG_HI, msb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	ret = regmap_write(stw481x->map, STW_PCTL_REG_LO, lsb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	ret = regmap_read(stw481x->map, STW_PCTL_REG_HI, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	vrfy = (val & 0x03) << 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	ret = regmap_read(stw481x->map, STW_PCTL_REG_LO, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	vrfy |= ((val >> 5) & 0x07);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	if (vrfy != reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 		return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	return (val >> 1) & 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) static int stw481x_startup(struct stw481x *stw481x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	/* Voltages multiplied by 100 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	static const u8 vcore_val[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		100, 105, 110, 115, 120, 122, 124, 126, 128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 		130, 132, 134, 136, 138, 140, 145
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	static const u8 vpll_val[] = { 105, 120, 130, 180 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	static const u8 vaux_val[] = { 15, 18, 25, 28 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	u8 vcore;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	u8 vcore_slp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	u8 vpll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	u8 vaux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	bool vaux_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	bool it_warn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	ret = regmap_read(stw481x->map, STW_CONF1, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	vaux_en = !!(val & STW_CONF1_PDN_VAUX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	it_warn = !!(val & STW_CONF1_IT_WARN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	dev_info(&stw481x->client->dev, "voltages %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		(val & STW_CONF1_V_MONITORING) ? "OK" : "LOW");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	dev_info(&stw481x->client->dev, "MMC level shifter %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		(val & STW_CONF1_MMC_LS_STATUS) ? "high impedance" : "ON");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	dev_info(&stw481x->client->dev, "VMMC: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		(val & STW_CONF1_PDN_VMMC) ? "ON" : "disabled");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	dev_info(&stw481x->client->dev, "STw481x power control registers:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	ret = stw481x_get_pctl_reg(stw481x, STW_PC_VCORE_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	vcore = ret & 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	ret = stw481x_get_pctl_reg(stw481x, STW_PC_VAUX_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	vaux = (ret >> 2) & 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	vpll = (ret >> 4) & 1; /* Save bit 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	ret = stw481x_get_pctl_reg(stw481x, STW_PC_VPLL_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	vpll |= (ret >> 1) & 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	dev_info(&stw481x->client->dev, "VCORE: %u.%uV %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		vcore_val[vcore] / 100, vcore_val[vcore] % 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		(ret & 4) ? "ON" : "OFF");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	dev_info(&stw481x->client->dev, "VPLL:  %u.%uV %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		vpll_val[vpll] / 100, vpll_val[vpll] % 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		(ret & 0x10) ? "ON" : "OFF");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	dev_info(&stw481x->client->dev, "VAUX:  %u.%uV %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		vaux_val[vaux] / 10, vaux_val[vaux] % 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		vaux_en ? "ON" : "OFF");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	ret = regmap_read(stw481x->map, STW_CONF2, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	dev_info(&stw481x->client->dev, "TWARN: %s threshold, %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		it_warn ? "below" : "above",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		(val & STW_CONF2_MASK_TWARN) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		 "enabled" : "mask through VDDOK");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	dev_info(&stw481x->client->dev, "VMMC: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		(val & STW_CONF2_VMMC_EXT) ? "internal" : "external");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	dev_info(&stw481x->client->dev, "IT WAKE UP: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		(val & STW_CONF2_MASK_IT_WAKE_UP) ? "enabled" : "masked");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	dev_info(&stw481x->client->dev, "GPO1: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		(val & STW_CONF2_GPO1) ? "low" : "high impedance");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	dev_info(&stw481x->client->dev, "GPO2: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		(val & STW_CONF2_GPO2) ? "low" : "high impedance");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	ret = regmap_read(stw481x->map, STW_VCORE_SLEEP, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	vcore_slp = val & 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	dev_info(&stw481x->client->dev, "VCORE SLEEP: %u.%uV\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		vcore_val[vcore_slp] / 100, vcore_val[vcore_slp] % 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)  * MFD cells - we have one cell which is selected operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)  * mode, and we always have a GPIO cell.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static struct mfd_cell stw481x_cells[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		.of_compatible = "st,stw481x-vmmc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		.name = "stw481x-vmmc-regulator",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		.id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static const struct regmap_config stw481x_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	.reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	.val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static int stw481x_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 			 const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	struct stw481x			*stw481x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	stw481x = devm_kzalloc(&client->dev, sizeof(*stw481x), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	if (!stw481x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	i2c_set_clientdata(client, stw481x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	stw481x->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	stw481x->map = devm_regmap_init_i2c(client, &stw481x_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	if (IS_ERR(stw481x->map)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		ret = PTR_ERR(stw481x->map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		dev_err(&client->dev, "Failed to allocate register map: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 			ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	ret = stw481x_startup(stw481x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		dev_err(&client->dev, "chip initialization failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	/* Set up and register the platform devices. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	for (i = 0; i < ARRAY_SIZE(stw481x_cells); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		/* One state holder for all drivers, this is simple */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		stw481x_cells[i].platform_data = stw481x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		stw481x_cells[i].pdata_size = sizeof(*stw481x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	ret = devm_mfd_add_devices(&client->dev, 0, stw481x_cells,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 				   ARRAY_SIZE(stw481x_cells), NULL, 0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	dev_info(&client->dev, "initialized STw481x device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)  * This ID table is completely unused, as this is a pure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)  * device-tree probed driver, but it has to be here due to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)  * the structure of the I2C core.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static const struct i2c_device_id stw481x_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	{ "stw481x", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	{ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) MODULE_DEVICE_TABLE(i2c, stw481x_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static const struct of_device_id stw481x_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	{ .compatible = "st,stw4810", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	{ .compatible = "st,stw4811", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	{ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) MODULE_DEVICE_TABLE(of, stw481x_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static struct i2c_driver stw481x_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		.name	= "stw481x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		.of_match_table = stw481x_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	.probe		= stw481x_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	.id_table	= stw481x_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) module_i2c_driver(stw481x_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) MODULE_AUTHOR("Linus Walleij");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) MODULE_DESCRIPTION("STw481x PMIC driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) MODULE_LICENSE("GPL v2");