Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) // Copyright (C) STMicroelectronics 2018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) // Author: Pascal Paillet <p.paillet@st.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/mfd/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/mfd/stpmic1.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/pm_wakeirq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <dt-bindings/mfd/st,stpmic1.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define STPMIC1_MAIN_IRQ 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) static const struct regmap_range stpmic1_readable_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 	regmap_reg_range(TURN_ON_SR, VERSION_SR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	regmap_reg_range(SWOFF_PWRCTRL_CR, LDO6_STDBY_CR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	regmap_reg_range(BST_SW_CR, BST_SW_CR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	regmap_reg_range(INT_PENDING_R1, INT_PENDING_R4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	regmap_reg_range(INT_CLEAR_R1, INT_CLEAR_R4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	regmap_reg_range(INT_MASK_R1, INT_MASK_R4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	regmap_reg_range(INT_SET_MASK_R1, INT_SET_MASK_R4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	regmap_reg_range(INT_CLEAR_MASK_R1, INT_CLEAR_MASK_R4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	regmap_reg_range(INT_SRC_R1, INT_SRC_R1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) static const struct regmap_range stpmic1_writeable_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	regmap_reg_range(SWOFF_PWRCTRL_CR, LDO6_STDBY_CR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	regmap_reg_range(BST_SW_CR, BST_SW_CR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	regmap_reg_range(INT_CLEAR_R1, INT_CLEAR_R4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	regmap_reg_range(INT_SET_MASK_R1, INT_SET_MASK_R4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	regmap_reg_range(INT_CLEAR_MASK_R1, INT_CLEAR_MASK_R4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) static const struct regmap_range stpmic1_volatile_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	regmap_reg_range(TURN_ON_SR, VERSION_SR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	regmap_reg_range(WCHDG_CR, WCHDG_CR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	regmap_reg_range(INT_PENDING_R1, INT_PENDING_R4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	regmap_reg_range(INT_SRC_R1, INT_SRC_R4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) static const struct regmap_access_table stpmic1_readable_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	.yes_ranges = stpmic1_readable_ranges,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	.n_yes_ranges = ARRAY_SIZE(stpmic1_readable_ranges),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) static const struct regmap_access_table stpmic1_writeable_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	.yes_ranges = stpmic1_writeable_ranges,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	.n_yes_ranges = ARRAY_SIZE(stpmic1_writeable_ranges),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) static const struct regmap_access_table stpmic1_volatile_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	.yes_ranges = stpmic1_volatile_ranges,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	.n_yes_ranges = ARRAY_SIZE(stpmic1_volatile_ranges),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) static const struct regmap_config stpmic1_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	.reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	.val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	.cache_type = REGCACHE_RBTREE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	.max_register = PMIC_MAX_REGISTER_ADDRESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	.rd_table = &stpmic1_readable_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	.wr_table = &stpmic1_writeable_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	.volatile_table = &stpmic1_volatile_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) static const struct regmap_irq stpmic1_irqs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	REGMAP_IRQ_REG(IT_PONKEY_F, 0, 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	REGMAP_IRQ_REG(IT_PONKEY_R, 0, 0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	REGMAP_IRQ_REG(IT_WAKEUP_F, 0, 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	REGMAP_IRQ_REG(IT_WAKEUP_R, 0, 0x08),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	REGMAP_IRQ_REG(IT_VBUS_OTG_F, 0, 0x10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	REGMAP_IRQ_REG(IT_VBUS_OTG_R, 0, 0x20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	REGMAP_IRQ_REG(IT_SWOUT_F, 0, 0x40),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	REGMAP_IRQ_REG(IT_SWOUT_R, 0, 0x80),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	REGMAP_IRQ_REG(IT_CURLIM_BUCK1, 1, 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	REGMAP_IRQ_REG(IT_CURLIM_BUCK2, 1, 0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	REGMAP_IRQ_REG(IT_CURLIM_BUCK3, 1, 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	REGMAP_IRQ_REG(IT_CURLIM_BUCK4, 1, 0x08),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	REGMAP_IRQ_REG(IT_OCP_OTG, 1, 0x10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	REGMAP_IRQ_REG(IT_OCP_SWOUT, 1, 0x20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	REGMAP_IRQ_REG(IT_OCP_BOOST, 1, 0x40),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	REGMAP_IRQ_REG(IT_OVP_BOOST, 1, 0x80),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	REGMAP_IRQ_REG(IT_CURLIM_LDO1, 2, 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	REGMAP_IRQ_REG(IT_CURLIM_LDO2, 2, 0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	REGMAP_IRQ_REG(IT_CURLIM_LDO3, 2, 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	REGMAP_IRQ_REG(IT_CURLIM_LDO4, 2, 0x08),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	REGMAP_IRQ_REG(IT_CURLIM_LDO5, 2, 0x10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	REGMAP_IRQ_REG(IT_CURLIM_LDO6, 2, 0x20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	REGMAP_IRQ_REG(IT_SHORT_SWOTG, 2, 0x40),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	REGMAP_IRQ_REG(IT_SHORT_SWOUT, 2, 0x80),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	REGMAP_IRQ_REG(IT_TWARN_F, 3, 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	REGMAP_IRQ_REG(IT_TWARN_R, 3, 0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	REGMAP_IRQ_REG(IT_VINLOW_F, 3, 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	REGMAP_IRQ_REG(IT_VINLOW_R, 3, 0x08),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	REGMAP_IRQ_REG(IT_SWIN_F, 3, 0x40),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	REGMAP_IRQ_REG(IT_SWIN_R, 3, 0x80),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static const struct regmap_irq_chip stpmic1_regmap_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	.name = "pmic_irq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	.status_base = INT_PENDING_R1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	.mask_base = INT_CLEAR_MASK_R1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	.unmask_base = INT_SET_MASK_R1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	.ack_base = INT_CLEAR_R1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	.num_regs = STPMIC1_PMIC_NUM_IRQ_REGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	.irqs = stpmic1_irqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	.num_irqs = ARRAY_SIZE(stpmic1_irqs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static int stpmic1_probe(struct i2c_client *i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 			 const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	struct stpmic1 *ddata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	struct device *dev = &i2c->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	ddata = devm_kzalloc(dev, sizeof(struct stpmic1), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	if (!ddata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	i2c_set_clientdata(i2c, ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	ddata->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	ddata->regmap = devm_regmap_init_i2c(i2c, &stpmic1_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	if (IS_ERR(ddata->regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		return PTR_ERR(ddata->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	ddata->irq = of_irq_get(np, STPMIC1_MAIN_IRQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	if (ddata->irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		dev_err(dev, "Failed to get main IRQ: %d\n", ddata->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		return ddata->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	ret = regmap_read(ddata->regmap, VERSION_SR, &reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		dev_err(dev, "Unable to read PMIC version\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	dev_info(dev, "PMIC Chip Version: 0x%x\n", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	/* Initialize PMIC IRQ Chip & associated IRQ domains */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	ret = devm_regmap_add_irq_chip(dev, ddata->regmap, ddata->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 				       IRQF_ONESHOT | IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 				       0, &stpmic1_regmap_irq_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 				       &ddata->irq_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		dev_err(dev, "IRQ Chip registration failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	return devm_of_platform_populate(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static int stpmic1_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	struct i2c_client *i2c = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	struct stpmic1 *pmic_dev = i2c_get_clientdata(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	disable_irq(pmic_dev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static int stpmic1_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	struct i2c_client *i2c = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	struct stpmic1 *pmic_dev = i2c_get_clientdata(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	ret = regcache_sync(pmic_dev->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	enable_irq(pmic_dev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static SIMPLE_DEV_PM_OPS(stpmic1_pm, stpmic1_suspend, stpmic1_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static const struct of_device_id stpmic1_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	{ .compatible = "st,stpmic1", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) MODULE_DEVICE_TABLE(of, stpmic1_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static struct i2c_driver stpmic1_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		.name = "stpmic1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		.of_match_table = of_match_ptr(stpmic1_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		.pm = &stpmic1_pm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	.probe = stpmic1_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) module_i2c_driver(stpmic1_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) MODULE_DESCRIPTION("STPMIC1 PMIC Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) MODULE_AUTHOR("Pascal Paillet <p.paillet@st.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) MODULE_LICENSE("GPL v2");