^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) ST-Ericsson SA 2010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef __STMPE_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define __STMPE_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/mfd/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/mfd/stmpe.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/printk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) extern const struct dev_pm_ops stmpe_dev_pm_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #ifdef STMPE_DUMP_BYTES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) static inline void stmpe_dump_bytes(const char *str, const void *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) size_t len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) print_hex_dump_bytes(str, DUMP_PREFIX_OFFSET, buf, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) static inline void stmpe_dump_bytes(const char *str, const void *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) size_t len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * struct stmpe_variant_block - information about block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * @cell: base mfd cell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * @irq: interrupt number to be added to each IORESOURCE_IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * in the cell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * @block: block id; used for identification with platform data and for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * enable and altfunc callbacks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct stmpe_variant_block {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) const struct mfd_cell *cell;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) enum stmpe_block block;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * struct stmpe_variant_info - variant-specific information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * @name: part name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * @id_val: content of CHIPID register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * @id_mask: bits valid in CHIPID register for comparison with id_val
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * @num_gpios: number of GPIOS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * @af_bits: number of bits used to specify the alternate function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * @regs: variant specific registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * @blocks: list of blocks present on this device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * @num_blocks: number of blocks present on this device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * @num_irqs: number of internal IRQs available on this device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * @enable: callback to enable the specified blocks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * Called with the I/O lock held.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * @get_altfunc: callback to get the alternate function number for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * specific block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * @enable_autosleep: callback to configure autosleep with specified timeout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct stmpe_variant_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) u16 id_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) u16 id_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) int num_gpios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) int af_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) const u8 *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct stmpe_variant_block *blocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) int num_blocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) int num_irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) int (*enable)(struct stmpe *stmpe, unsigned int blocks, bool enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) int (*get_altfunc)(struct stmpe *stmpe, enum stmpe_block block);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) int (*enable_autosleep)(struct stmpe *stmpe, int autosleep_timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * struct stmpe_client_info - i2c or spi specific routines/info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * @data: client specific data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * @read_byte: read single byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * @write_byte: write single byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * @read_block: read block or multiple bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * @write_block: write block or multiple bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * @init: client init routine, called during probe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct stmpe_client_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) void *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) void *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) int (*read_byte)(struct stmpe *stmpe, u8 reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) int (*write_byte)(struct stmpe *stmpe, u8 reg, u8 val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) int (*read_block)(struct stmpe *stmpe, u8 reg, u8 len, u8 *values);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) int (*write_block)(struct stmpe *stmpe, u8 reg, u8 len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) const u8 *values);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) void (*init)(struct stmpe *stmpe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) int stmpe_probe(struct stmpe_client_info *ci, enum stmpe_partnum partnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) int stmpe_remove(struct stmpe *stmpe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define STMPE_ICR_LSB_HIGH (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define STMPE_ICR_LSB_EDGE (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define STMPE_ICR_LSB_GIM (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define STMPE_SYS_CTRL_RESET (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define STMPE_SYS_CTRL_INT_EN (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define STMPE_SYS_CTRL_INT_HI (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * STMPE801
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define STMPE801_ID 0x0108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define STMPE801_NR_INTERNAL_IRQS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define STMPE801_REG_CHIP_ID 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define STMPE801_REG_VERSION_ID 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define STMPE801_REG_SYS_CTRL 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define STMPE801_REG_GPIO_INT_EN 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define STMPE801_REG_GPIO_INT_STA 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define STMPE801_REG_GPIO_MP_STA 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define STMPE801_REG_GPIO_SET_PIN 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define STMPE801_REG_GPIO_DIR 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * STMPE811
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define STMPE811_ID 0x0811
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define STMPE811_IRQ_TOUCH_DET 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define STMPE811_IRQ_FIFO_TH 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define STMPE811_IRQ_FIFO_OFLOW 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define STMPE811_IRQ_FIFO_FULL 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define STMPE811_IRQ_FIFO_EMPTY 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define STMPE811_IRQ_TEMP_SENS 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define STMPE811_IRQ_ADC 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define STMPE811_IRQ_GPIOC 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define STMPE811_NR_INTERNAL_IRQS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define STMPE811_REG_CHIP_ID 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define STMPE811_REG_SYS_CTRL 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define STMPE811_REG_SYS_CTRL2 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define STMPE811_REG_SPI_CFG 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define STMPE811_REG_INT_CTRL 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define STMPE811_REG_INT_EN 0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define STMPE811_REG_INT_STA 0x0B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define STMPE811_REG_GPIO_INT_EN 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define STMPE811_REG_GPIO_INT_STA 0x0D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define STMPE811_REG_GPIO_SET_PIN 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define STMPE811_REG_GPIO_CLR_PIN 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define STMPE811_REG_GPIO_MP_STA 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define STMPE811_REG_GPIO_DIR 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define STMPE811_REG_GPIO_ED 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define STMPE811_REG_GPIO_RE 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define STMPE811_REG_GPIO_FE 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define STMPE811_REG_GPIO_AF 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define STMPE811_SYS_CTRL_RESET (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define STMPE811_SYS_CTRL2_ADC_OFF (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define STMPE811_SYS_CTRL2_TSC_OFF (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define STMPE811_SYS_CTRL2_GPIO_OFF (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define STMPE811_SYS_CTRL2_TS_OFF (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * STMPE1600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define STMPE1600_ID 0x0016
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define STMPE1600_NR_INTERNAL_IRQS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define STMPE1600_REG_CHIP_ID 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define STMPE1600_REG_SYS_CTRL 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define STMPE1600_REG_IEGPIOR_LSB 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define STMPE1600_REG_IEGPIOR_MSB 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define STMPE1600_REG_ISGPIOR_LSB 0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define STMPE1600_REG_ISGPIOR_MSB 0x0B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define STMPE1600_REG_GPMR_LSB 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define STMPE1600_REG_GPMR_MSB 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define STMPE1600_REG_GPSR_LSB 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define STMPE1600_REG_GPSR_MSB 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define STMPE1600_REG_GPDR_LSB 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define STMPE1600_REG_GPDR_MSB 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define STMPE1600_REG_GPPIR_LSB 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define STMPE1600_REG_GPPIR_MSB 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * STMPE1601
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define STMPE1601_IRQ_GPIOC 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define STMPE1601_IRQ_PWM3 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define STMPE1601_IRQ_PWM2 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define STMPE1601_IRQ_PWM1 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define STMPE1601_IRQ_PWM0 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define STMPE1601_IRQ_KEYPAD_OVER 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define STMPE1601_IRQ_KEYPAD 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define STMPE1601_IRQ_WAKEUP 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define STMPE1601_NR_INTERNAL_IRQS 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define STMPE1601_REG_SYS_CTRL 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define STMPE1601_REG_SYS_CTRL2 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define STMPE1601_REG_ICR_MSB 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define STMPE1601_REG_ICR_LSB 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define STMPE1601_REG_IER_MSB 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define STMPE1601_REG_IER_LSB 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define STMPE1601_REG_ISR_MSB 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define STMPE1601_REG_ISR_LSB 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define STMPE1601_REG_INT_EN_GPIO_MASK_MSB 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define STMPE1601_REG_INT_EN_GPIO_MASK_LSB 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define STMPE1601_REG_INT_STA_GPIO_MSB 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define STMPE1601_REG_INT_STA_GPIO_LSB 0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define STMPE1601_REG_CHIP_ID 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define STMPE1601_REG_GPIO_SET_MSB 0x82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define STMPE1601_REG_GPIO_SET_LSB 0x83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define STMPE1601_REG_GPIO_CLR_MSB 0x84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define STMPE1601_REG_GPIO_CLR_LSB 0x85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define STMPE1601_REG_GPIO_MP_MSB 0x86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define STMPE1601_REG_GPIO_MP_LSB 0x87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define STMPE1601_REG_GPIO_SET_DIR_MSB 0x88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define STMPE1601_REG_GPIO_SET_DIR_LSB 0x89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define STMPE1601_REG_GPIO_ED_MSB 0x8A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define STMPE1601_REG_GPIO_ED_LSB 0x8B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define STMPE1601_REG_GPIO_RE_MSB 0x8C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define STMPE1601_REG_GPIO_RE_LSB 0x8D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define STMPE1601_REG_GPIO_FE_MSB 0x8E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define STMPE1601_REG_GPIO_FE_LSB 0x8F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define STMPE1601_REG_GPIO_PU_MSB 0x90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define STMPE1601_REG_GPIO_PU_LSB 0x91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define STMPE1601_REG_GPIO_AF_U_MSB 0x92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define STMPE1601_SYS_CTRL_ENABLE_GPIO (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define STMPE1601_SYS_CTRL_ENABLE_KPC (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define STMPE1601_SYS_CTRL_ENABLE_SPWM (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /* The 1601/2403 share the same masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define STMPE1601_AUTOSLEEP_TIMEOUT_MASK (0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define STPME1601_AUTOSLEEP_ENABLE (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) * STMPE1801
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define STMPE1801_ID 0xc110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define STMPE1801_NR_INTERNAL_IRQS 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define STMPE1801_IRQ_KEYPAD_COMBI 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define STMPE1801_IRQ_GPIOC 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define STMPE1801_IRQ_KEYPAD_OVER 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define STMPE1801_IRQ_KEYPAD 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define STMPE1801_IRQ_WAKEUP 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define STMPE1801_REG_CHIP_ID 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define STMPE1801_REG_SYS_CTRL 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define STMPE1801_REG_INT_CTRL_LOW 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define STMPE1801_REG_INT_EN_MASK_LOW 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define STMPE1801_REG_INT_STA_LOW 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define STMPE1801_REG_INT_EN_GPIO_MASK_LOW 0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define STMPE1801_REG_INT_EN_GPIO_MASK_MID 0x0B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define STMPE1801_REG_INT_EN_GPIO_MASK_HIGH 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define STMPE1801_REG_INT_STA_GPIO_LOW 0x0D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define STMPE1801_REG_INT_STA_GPIO_MID 0x0E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define STMPE1801_REG_INT_STA_GPIO_HIGH 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define STMPE1801_REG_GPIO_SET_LOW 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define STMPE1801_REG_GPIO_SET_MID 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define STMPE1801_REG_GPIO_SET_HIGH 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define STMPE1801_REG_GPIO_CLR_LOW 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define STMPE1801_REG_GPIO_CLR_MID 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define STMPE1801_REG_GPIO_CLR_HIGH 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define STMPE1801_REG_GPIO_MP_LOW 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define STMPE1801_REG_GPIO_MP_MID 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define STMPE1801_REG_GPIO_MP_HIGH 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define STMPE1801_REG_GPIO_SET_DIR_LOW 0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define STMPE1801_REG_GPIO_SET_DIR_MID 0x1A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define STMPE1801_REG_GPIO_SET_DIR_HIGH 0x1B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define STMPE1801_REG_GPIO_RE_LOW 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define STMPE1801_REG_GPIO_RE_MID 0x1D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define STMPE1801_REG_GPIO_RE_HIGH 0x1E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define STMPE1801_REG_GPIO_FE_LOW 0x1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define STMPE1801_REG_GPIO_FE_MID 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define STMPE1801_REG_GPIO_FE_HIGH 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define STMPE1801_REG_GPIO_PULL_UP_LOW 0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define STMPE1801_REG_GPIO_PULL_UP_MID 0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define STMPE1801_REG_GPIO_PULL_UP_HIGH 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define STMPE1801_MSK_INT_EN_KPC (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define STMPE1801_MSK_INT_EN_GPIO (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * STMPE24xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define STMPE24XX_IRQ_GPIOC 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define STMPE24XX_IRQ_PWM2 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define STMPE24XX_IRQ_PWM1 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define STMPE24XX_IRQ_PWM0 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define STMPE24XX_IRQ_ROT_OVER 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define STMPE24XX_IRQ_ROT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define STMPE24XX_IRQ_KEYPAD_OVER 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define STMPE24XX_IRQ_KEYPAD 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define STMPE24XX_IRQ_WAKEUP 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define STMPE24XX_NR_INTERNAL_IRQS 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define STMPE24XX_REG_SYS_CTRL 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define STMPE24XX_REG_SYS_CTRL2 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define STMPE24XX_REG_ICR_MSB 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define STMPE24XX_REG_ICR_LSB 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define STMPE24XX_REG_IER_MSB 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define STMPE24XX_REG_IER_LSB 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define STMPE24XX_REG_ISR_MSB 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define STMPE24XX_REG_ISR_LSB 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define STMPE24XX_REG_IEGPIOR_MSB 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define STMPE24XX_REG_IEGPIOR_CSB 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define STMPE24XX_REG_IEGPIOR_LSB 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define STMPE24XX_REG_ISGPIOR_MSB 0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define STMPE24XX_REG_ISGPIOR_CSB 0x1A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define STMPE24XX_REG_ISGPIOR_LSB 0x1B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define STMPE24XX_REG_CHIP_ID 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define STMPE24XX_REG_GPSR_MSB 0x83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define STMPE24XX_REG_GPSR_CSB 0x84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define STMPE24XX_REG_GPSR_LSB 0x85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define STMPE24XX_REG_GPCR_MSB 0x86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define STMPE24XX_REG_GPCR_CSB 0x87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define STMPE24XX_REG_GPCR_LSB 0x88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define STMPE24XX_REG_GPDR_MSB 0x89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define STMPE24XX_REG_GPDR_CSB 0x8A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define STMPE24XX_REG_GPDR_LSB 0x8B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define STMPE24XX_REG_GPEDR_MSB 0x8C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define STMPE24XX_REG_GPEDR_CSB 0x8D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define STMPE24XX_REG_GPEDR_LSB 0x8E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define STMPE24XX_REG_GPRER_MSB 0x8F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define STMPE24XX_REG_GPRER_CSB 0x90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define STMPE24XX_REG_GPRER_LSB 0x91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define STMPE24XX_REG_GPFER_MSB 0x92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define STMPE24XX_REG_GPFER_CSB 0x93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define STMPE24XX_REG_GPFER_LSB 0x94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define STMPE24XX_REG_GPPUR_MSB 0x95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define STMPE24XX_REG_GPPUR_CSB 0x96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define STMPE24XX_REG_GPPUR_LSB 0x97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define STMPE24XX_REG_GPPDR_MSB 0x98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define STMPE24XX_REG_GPPDR_CSB 0x99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define STMPE24XX_REG_GPPDR_LSB 0x9A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define STMPE24XX_REG_GPAFR_U_MSB 0x9B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define STMPE24XX_REG_GPMR_MSB 0xA2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define STMPE24XX_REG_GPMR_CSB 0xA3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define STMPE24XX_REG_GPMR_LSB 0xA4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define STMPE24XX_SYS_CTRL_ENABLE_GPIO (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define STMPE24XX_SYSCON_ENABLE_PWM (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define STMPE24XX_SYS_CTRL_ENABLE_KPC (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define STMPE24XX_SYSCON_ENABLE_ROT (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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