^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) STMicroelectronics 2016
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Benjamin Gaignard <benjamin.gaignard@st.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/mfd/stm32-timers.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define STM32_TIMERS_MAX_REGISTERS 0x3fc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /* DIER register DMA enable bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) static const u32 stm32_timers_dier_dmaen[STM32_TIMERS_MAX_DMAS] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) TIM_DIER_CC1DE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) TIM_DIER_CC2DE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) TIM_DIER_CC3DE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) TIM_DIER_CC4DE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) TIM_DIER_UIE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) TIM_DIER_TDE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) TIM_DIER_COMDE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) static void stm32_timers_dma_done(void *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) struct stm32_timers_dma *dma = p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct dma_tx_state state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) enum dma_status status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) status = dmaengine_tx_status(dma->chan, dma->chan->cookie, &state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) if (status == DMA_COMPLETE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) complete(&dma->completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * stm32_timers_dma_burst_read - Read from timers registers using DMA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * Read from STM32 timers registers using DMA on a single event.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * @dev: reference to stm32_timers MFD device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * @buf: DMA'able destination buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * @id: stm32_timers_dmas event identifier (ch[1..4], up, trig or com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * @reg: registers start offset for DMA to read from (like CCRx for capture)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * @num_reg: number of registers to read upon each DMA request, starting @reg.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * @bursts: number of bursts to read (e.g. like two for pwm period capture)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * @tmo_ms: timeout (milliseconds)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) int stm32_timers_dma_burst_read(struct device *dev, u32 *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) enum stm32_timers_dmas id, u32 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) unsigned int num_reg, unsigned int bursts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) unsigned long tmo_ms)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct stm32_timers *ddata = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) unsigned long timeout = msecs_to_jiffies(tmo_ms);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct regmap *regmap = ddata->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct stm32_timers_dma *dma = &ddata->dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) size_t len = num_reg * bursts * sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct dma_async_tx_descriptor *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct dma_slave_config config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) dma_cookie_t cookie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) dma_addr_t dma_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) u32 dbl, dba;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) long err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* Sanity check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) if (id < STM32_TIMERS_DMA_CH1 || id >= STM32_TIMERS_MAX_DMAS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) if (!num_reg || !bursts || reg > STM32_TIMERS_MAX_REGISTERS ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) (reg + num_reg * sizeof(u32)) > STM32_TIMERS_MAX_REGISTERS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) if (!dma->chans[id])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) mutex_lock(&dma->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* Select DMA channel in use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) dma->chan = dma->chans[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) dma_buf = dma_map_single(dev, buf, len, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) if (dma_mapping_error(dev, dma_buf)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* Prepare DMA read from timer registers, using DMA burst mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) memset(&config, 0, sizeof(config));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) config.src_addr = (dma_addr_t)dma->phys_base + TIM_DMAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) ret = dmaengine_slave_config(dma->chan, &config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) goto unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) desc = dmaengine_prep_slave_single(dma->chan, dma_buf, len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) if (!desc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) ret = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) goto unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) desc->callback = stm32_timers_dma_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) desc->callback_param = dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) cookie = dmaengine_submit(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) ret = dma_submit_error(cookie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) goto dma_term;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) reinit_completion(&dma->completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) dma_async_issue_pending(dma->chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* Setup and enable timer DMA burst mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) dbl = FIELD_PREP(TIM_DCR_DBL, bursts - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) dba = FIELD_PREP(TIM_DCR_DBA, reg >> 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) ret = regmap_write(regmap, TIM_DCR, dbl | dba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) goto dma_term;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* Clear pending flags before enabling DMA request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) ret = regmap_write(regmap, TIM_SR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) goto dcr_clr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) ret = regmap_update_bits(regmap, TIM_DIER, stm32_timers_dier_dmaen[id],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) stm32_timers_dier_dmaen[id]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) goto dcr_clr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) err = wait_for_completion_interruptible_timeout(&dma->completion,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) if (err == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) ret = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) else if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) ret = err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) regmap_update_bits(regmap, TIM_DIER, stm32_timers_dier_dmaen[id], 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) regmap_write(regmap, TIM_SR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) dcr_clr:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) regmap_write(regmap, TIM_DCR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) dma_term:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) dmaengine_terminate_all(dma->chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) unmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) dma_unmap_single(dev, dma_buf, len, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) dma->chan = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) mutex_unlock(&dma->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) EXPORT_SYMBOL_GPL(stm32_timers_dma_burst_read);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static const struct regmap_config stm32_timers_regmap_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .reg_stride = sizeof(u32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .max_register = STM32_TIMERS_MAX_REGISTERS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static void stm32_timers_get_arr_size(struct stm32_timers *ddata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) u32 arr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /* Backup ARR to restore it after getting the maximum value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) regmap_read(ddata->regmap, TIM_ARR, &arr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * Only the available bits will be written so when readback
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * we get the maximum value of auto reload register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) regmap_write(ddata->regmap, TIM_ARR, ~0L);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) regmap_read(ddata->regmap, TIM_ARR, &ddata->max_arr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) regmap_write(ddata->regmap, TIM_ARR, arr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static int stm32_timers_dma_probe(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) struct stm32_timers *ddata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) char name[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) init_completion(&ddata->dma.completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) mutex_init(&ddata->dma.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* Optional DMA support: get valid DMA channel(s) or NULL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) for (i = STM32_TIMERS_DMA_CH1; i <= STM32_TIMERS_DMA_CH4; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) snprintf(name, ARRAY_SIZE(name), "ch%1d", i + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) ddata->dma.chans[i] = dma_request_chan(dev, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) ddata->dma.chans[STM32_TIMERS_DMA_UP] = dma_request_chan(dev, "up");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) ddata->dma.chans[STM32_TIMERS_DMA_TRIG] = dma_request_chan(dev, "trig");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) ddata->dma.chans[STM32_TIMERS_DMA_COM] = dma_request_chan(dev, "com");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) for (i = STM32_TIMERS_DMA_CH1; i < STM32_TIMERS_MAX_DMAS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (IS_ERR(ddata->dma.chans[i])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /* Save the first error code to return */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) if (PTR_ERR(ddata->dma.chans[i]) != -ENODEV && !ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) ret = PTR_ERR(ddata->dma.chans[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) ddata->dma.chans[i] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static void stm32_timers_dma_remove(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) struct stm32_timers *ddata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) for (i = STM32_TIMERS_DMA_CH1; i < STM32_TIMERS_MAX_DMAS; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) if (ddata->dma.chans[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) dma_release_channel(ddata->dma.chans[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static int stm32_timers_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) struct stm32_timers *ddata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) void __iomem *mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) ddata = devm_kzalloc(dev, sizeof(*ddata), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) if (!ddata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) mmio = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (IS_ERR(mmio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) return PTR_ERR(mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /* Timer physical addr for DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) ddata->dma.phys_base = res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) ddata->regmap = devm_regmap_init_mmio_clk(dev, "int", mmio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) &stm32_timers_regmap_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) if (IS_ERR(ddata->regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) return PTR_ERR(ddata->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) ddata->clk = devm_clk_get(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) if (IS_ERR(ddata->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) return PTR_ERR(ddata->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) stm32_timers_get_arr_size(ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) ret = stm32_timers_dma_probe(dev, ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) stm32_timers_dma_remove(dev, ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) platform_set_drvdata(pdev, ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) ret = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) stm32_timers_dma_remove(dev, ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static int stm32_timers_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) struct stm32_timers *ddata = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * Don't use devm_ here: enfore of_platform_depopulate() happens before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) * DMA are released, to avoid race on DMA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) of_platform_depopulate(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) stm32_timers_dma_remove(&pdev->dev, ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static const struct of_device_id stm32_timers_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) { .compatible = "st,stm32-timers", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) { /* end node */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) MODULE_DEVICE_TABLE(of, stm32_timers_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static struct platform_driver stm32_timers_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .probe = stm32_timers_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .remove = stm32_timers_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .name = "stm32-timers",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .of_match_table = stm32_timers_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) module_platform_driver(stm32_timers_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) MODULE_DESCRIPTION("STMicroelectronics STM32 Timers");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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