Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * STA2x11 mfd for GPIO, SCTL and APBREG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (c) 2009-2011 Wind River Systems, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright (c) 2011 ST Microelectronics (Alessandro Rubini, Davide Ciminaghi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/seq_file.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/mfd/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/mfd/sta2x11-mfd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include <asm/sta2x11.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) static inline int __reg_within_range(unsigned int r,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 				     unsigned int start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 				     unsigned int end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	return ((r >= start) && (r <= end));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) /* This describes STA2X11 MFD chip for us, we may have several */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) struct sta2x11_mfd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	struct sta2x11_instance *instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	struct regmap *regmap[sta2x11_n_mfd_plat_devs];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	spinlock_t lock[sta2x11_n_mfd_plat_devs];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	void __iomem *regs[sta2x11_n_mfd_plat_devs];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) static LIST_HEAD(sta2x11_mfd_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) /* Three functions to act on the list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) static struct sta2x11_mfd *sta2x11_mfd_find(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	struct sta2x11_instance *instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	struct sta2x11_mfd *mfd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	if (!pdev && !list_empty(&sta2x11_mfd_list)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 		pr_warn("%s: Unspecified device, using first instance\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 			__func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 		return list_entry(sta2x11_mfd_list.next,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 				  struct sta2x11_mfd, list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	instance = sta2x11_get_instance(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	if (!instance)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 		return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	list_for_each_entry(mfd, &sta2x11_mfd_list, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 		if (mfd->instance == instance)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 			return mfd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) static int sta2x11_mfd_add(struct pci_dev *pdev, gfp_t flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	struct sta2x11_mfd *mfd = sta2x11_mfd_find(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	struct sta2x11_instance *instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	if (mfd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 		return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	instance = sta2x11_get_instance(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	if (!instance)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	mfd = kzalloc(sizeof(*mfd), flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	if (!mfd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	INIT_LIST_HEAD(&mfd->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	for (i = 0; i < ARRAY_SIZE(mfd->lock); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		spin_lock_init(&mfd->lock[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	mfd->instance = instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	list_add(&mfd->list, &sta2x11_mfd_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) /* This function is exported and is not expected to fail */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) u32 __sta2x11_mfd_mask(struct pci_dev *pdev, u32 reg, u32 mask, u32 val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		       enum sta2x11_mfd_plat_dev index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	struct sta2x11_mfd *mfd = sta2x11_mfd_find(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	u32 r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	if (!mfd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		dev_warn(&pdev->dev, ": can't access sctl regs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	regs = mfd->regs[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	if (!regs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		dev_warn(&pdev->dev, ": system ctl not initialized\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	spin_lock_irqsave(&mfd->lock[index], flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	r = readl(regs + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	r &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	r |= val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	if (mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		writel(r, regs + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	spin_unlock_irqrestore(&mfd->lock[index], flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) EXPORT_SYMBOL(__sta2x11_mfd_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) int sta2x11_mfd_get_regs_data(struct platform_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 			      enum sta2x11_mfd_plat_dev index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 			      void __iomem **regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 			      spinlock_t **lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	struct pci_dev *pdev = *(struct pci_dev **)dev_get_platdata(&dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	struct sta2x11_mfd *mfd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	if (!pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	mfd = sta2x11_mfd_find(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	if (!mfd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	if (index >= sta2x11_n_mfd_plat_devs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	*regs = mfd->regs[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	*lock = &mfd->lock[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	pr_debug("%s %d *regs = %p\n", __func__, __LINE__, *regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	return *regs ? 0 : -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) EXPORT_SYMBOL(sta2x11_mfd_get_regs_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)  * Special sta2x11-mfd regmap lock/unlock functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static void sta2x11_regmap_lock(void *__lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	spinlock_t *lock = __lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	spin_lock(lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static void sta2x11_regmap_unlock(void *__lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	spinlock_t *lock = __lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	spin_unlock(lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* OTP (one time programmable registers do not require locking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static void sta2x11_regmap_nolock(void *__lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static const char *sta2x11_mfd_names[sta2x11_n_mfd_plat_devs] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	[sta2x11_sctl] = STA2X11_MFD_SCTL_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	[sta2x11_apbreg] = STA2X11_MFD_APBREG_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	[sta2x11_apb_soc_regs] = STA2X11_MFD_APB_SOC_REGS_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	[sta2x11_scr] = STA2X11_MFD_SCR_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static bool sta2x11_sctl_writeable_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	return !__reg_within_range(reg, SCTL_SCPCIECSBRST, SCTL_SCRSTSTA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static struct regmap_config sta2x11_sctl_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	.reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	.reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	.val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	.lock = sta2x11_regmap_lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	.unlock = sta2x11_regmap_unlock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	.max_register = SCTL_SCRSTSTA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	.writeable_reg = sta2x11_sctl_writeable_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static bool sta2x11_scr_readable_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	return (reg == STA2X11_SECR_CR) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		__reg_within_range(reg, STA2X11_SECR_FVR0, STA2X11_SECR_FVR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static bool sta2x11_scr_writeable_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static struct regmap_config sta2x11_scr_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	.reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	.reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	.val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	.lock = sta2x11_regmap_nolock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	.unlock = sta2x11_regmap_nolock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	.max_register = STA2X11_SECR_FVR1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	.readable_reg = sta2x11_scr_readable_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	.writeable_reg = sta2x11_scr_writeable_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static bool sta2x11_apbreg_readable_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	/* Two blocks (CAN and MLB, SARAC) 0x100 bytes apart */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	if (reg >= APBREG_BSR_SARAC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		reg -= APBREG_BSR_SARAC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	case APBREG_BSR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	case APBREG_PAER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	case APBREG_PWAC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	case APBREG_PRAC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	case APBREG_PCG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	case APBREG_PUR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	case APBREG_EMU_PCG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static bool sta2x11_apbreg_writeable_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	if (reg >= APBREG_BSR_SARAC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		reg -= APBREG_BSR_SARAC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	if (!sta2x11_apbreg_readable_reg(dev, reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	return reg != APBREG_PAER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static struct regmap_config sta2x11_apbreg_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	.reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	.reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	.val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	.lock = sta2x11_regmap_lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	.unlock = sta2x11_regmap_unlock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	.max_register = APBREG_EMU_PCG_SARAC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	.readable_reg = sta2x11_apbreg_readable_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	.writeable_reg = sta2x11_apbreg_writeable_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static bool sta2x11_apb_soc_regs_readable_reg(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 					      unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	return reg <= PCIE_SoC_INT_ROUTER_STATUS3_REG ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		__reg_within_range(reg, DMA_IP_CTRL_REG, SPARE3_RESERVED) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		__reg_within_range(reg, MASTER_LOCK_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 				   SYSTEM_CONFIG_STATUS_REG) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		reg == MSP_CLK_CTRL_REG ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		__reg_within_range(reg, COMPENSATION_REG1, TEST_CTL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static bool sta2x11_apb_soc_regs_writeable_reg(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 					       unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	if (!sta2x11_apb_soc_regs_readable_reg(dev, reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	case PCIE_COMMON_CLOCK_CONFIG_0_4_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	case SYSTEM_CONFIG_STATUS_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	case COMPENSATION_REG1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	case PCIE_SoC_INT_ROUTER_STATUS0_REG...PCIE_SoC_INT_ROUTER_STATUS3_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	case PCIE_PM_STATUS_0_PORT_0_4...PCIE_PM_STATUS_7_0_EP4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static struct regmap_config sta2x11_apb_soc_regs_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	.reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	.reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	.val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	.lock = sta2x11_regmap_lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	.unlock = sta2x11_regmap_unlock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	.max_register = TEST_CTL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	.readable_reg = sta2x11_apb_soc_regs_readable_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	.writeable_reg = sta2x11_apb_soc_regs_writeable_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) static struct regmap_config *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) sta2x11_mfd_regmap_configs[sta2x11_n_mfd_plat_devs] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	[sta2x11_sctl] = &sta2x11_sctl_regmap_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	[sta2x11_apbreg] = &sta2x11_apbreg_regmap_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	[sta2x11_apb_soc_regs] = &sta2x11_apb_soc_regs_regmap_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	[sta2x11_scr] = &sta2x11_scr_regmap_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /* Probe for the four platform devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static int sta2x11_mfd_platform_probe(struct platform_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 				      enum sta2x11_mfd_plat_dev index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	struct pci_dev **pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	struct sta2x11_mfd *mfd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	const char *name = sta2x11_mfd_names[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	struct regmap_config *regmap_config = sta2x11_mfd_regmap_configs[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	pdev = dev_get_platdata(&dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	mfd = sta2x11_mfd_find(*pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	if (!mfd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	if (!regmap_config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	res = platform_get_resource(dev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	if (!res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	if (!request_mem_region(res->start, resource_size(res), name))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 		return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	mfd->regs[index] = ioremap(res->start, resource_size(res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	if (!mfd->regs[index]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 		release_mem_region(res->start, resource_size(res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	regmap_config->lock_arg = &mfd->lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	   No caching, registers could be reached both via regmap and via
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	   void __iomem *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	regmap_config->cache_type = REGCACHE_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	mfd->regmap[index] = devm_regmap_init_mmio(&dev->dev, mfd->regs[index],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 						   regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	WARN_ON(IS_ERR(mfd->regmap[index]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static int sta2x11_sctl_probe(struct platform_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	return sta2x11_mfd_platform_probe(dev, sta2x11_sctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) static int sta2x11_apbreg_probe(struct platform_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	return sta2x11_mfd_platform_probe(dev, sta2x11_apbreg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static int sta2x11_apb_soc_regs_probe(struct platform_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	return sta2x11_mfd_platform_probe(dev, sta2x11_apb_soc_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) static int sta2x11_scr_probe(struct platform_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	return sta2x11_mfd_platform_probe(dev, sta2x11_scr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) /* The three platform drivers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static struct platform_driver sta2x11_sctl_platform_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 		.name	= STA2X11_MFD_SCTL_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	.probe		= sta2x11_sctl_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) static struct platform_driver sta2x11_platform_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 		.name	= STA2X11_MFD_APBREG_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	.probe		= sta2x11_apbreg_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) static struct platform_driver sta2x11_apb_soc_regs_platform_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 		.name	= STA2X11_MFD_APB_SOC_REGS_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	.probe		= sta2x11_apb_soc_regs_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) static struct platform_driver sta2x11_scr_platform_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 		.name = STA2X11_MFD_SCR_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	.probe = sta2x11_scr_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) static struct platform_driver * const drivers[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	&sta2x11_platform_driver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	&sta2x11_sctl_platform_driver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	&sta2x11_apb_soc_regs_platform_driver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	&sta2x11_scr_platform_driver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) static int __init sta2x11_drivers_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	return platform_register_drivers(drivers, ARRAY_SIZE(drivers));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)  * What follows are the PCI devices that host the above pdevs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)  * Each logic block is 4kB and they are all consecutive: we use this info.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) /* Mfd 0 device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) /* Mfd 0, Bar 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) enum mfd0_bar0_cells {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 	STA2X11_GPIO_0 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	STA2X11_GPIO_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	STA2X11_GPIO_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	STA2X11_GPIO_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	STA2X11_SCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	STA2X11_SCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	STA2X11_TIME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) /* Mfd 0 , Bar 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) enum mfd0_bar1_cells {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 	STA2X11_APBREG = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define CELL_4K(_name, _cell) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 		.name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 		.start = _cell * 4096, .end = _cell * 4096 + 4095, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 		.flags = IORESOURCE_MEM, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) static const struct resource gpio_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 		/* 4 consecutive cells, 1 driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 		.name = STA2X11_MFD_GPIO_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 		.start = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 		.end = (4 * 4096) - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 		.flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) static const struct resource sctl_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 	CELL_4K(STA2X11_MFD_SCTL_NAME, STA2X11_SCTL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) static const struct resource scr_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 	CELL_4K(STA2X11_MFD_SCR_NAME, STA2X11_SCR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) static const struct resource time_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 	CELL_4K(STA2X11_MFD_TIME_NAME, STA2X11_TIME),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) static const struct resource apbreg_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 	CELL_4K(STA2X11_MFD_APBREG_NAME, STA2X11_APBREG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define DEV(_name, _r) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 	{ .name = _name, .num_resources = ARRAY_SIZE(_r), .resources = _r, }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) static struct mfd_cell sta2x11_mfd0_bar0[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 	/* offset 0: we add pdata later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 	DEV(STA2X11_MFD_GPIO_NAME, gpio_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 	DEV(STA2X11_MFD_SCTL_NAME, sctl_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 	DEV(STA2X11_MFD_SCR_NAME,  scr_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 	DEV(STA2X11_MFD_TIME_NAME, time_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) static struct mfd_cell sta2x11_mfd0_bar1[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 	DEV(STA2X11_MFD_APBREG_NAME, apbreg_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) /* Mfd 1 devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) /* Mfd 1, Bar 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) enum mfd1_bar0_cells {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 	STA2X11_VIC = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) /* Mfd 1, Bar 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) enum mfd1_bar1_cells {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 	STA2X11_APB_SOC_REGS = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) static const struct resource vic_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 	CELL_4K(STA2X11_MFD_VIC_NAME, STA2X11_VIC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) static const struct resource apb_soc_regs_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 	CELL_4K(STA2X11_MFD_APB_SOC_REGS_NAME, STA2X11_APB_SOC_REGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) static struct mfd_cell sta2x11_mfd1_bar0[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 	DEV(STA2X11_MFD_VIC_NAME, vic_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) static struct mfd_cell sta2x11_mfd1_bar1[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 	DEV(STA2X11_MFD_APB_SOC_REGS_NAME, apb_soc_regs_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) static int sta2x11_mfd_suspend(struct pci_dev *pdev, pm_message_t state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) 	pci_save_state(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) 	pci_disable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) 	pci_set_power_state(pdev, pci_choose_state(pdev, state));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) static int sta2x11_mfd_resume(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) 	pci_set_power_state(pdev, PCI_D0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) 	err = pci_enable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) 	pci_restore_state(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) struct sta2x11_mfd_bar_setup_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) 	struct mfd_cell *cells;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) 	int ncells;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) struct sta2x11_mfd_setup_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) 	struct sta2x11_mfd_bar_setup_data bars[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) #define STA2X11_MFD0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) #define STA2X11_MFD1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) static struct sta2x11_mfd_setup_data mfd_setup_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) 	/* Mfd 0: gpio, sctl, scr, timers / apbregs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) 	[STA2X11_MFD0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) 		.bars = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) 			[0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) 				.cells = sta2x11_mfd0_bar0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) 				.ncells = ARRAY_SIZE(sta2x11_mfd0_bar0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) 			},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) 			[1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) 				.cells = sta2x11_mfd0_bar1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) 				.ncells = ARRAY_SIZE(sta2x11_mfd0_bar1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) 			},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) 	/* Mfd 1: vic / apb-soc-regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) 	[STA2X11_MFD1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) 		.bars = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) 			[0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) 				.cells = sta2x11_mfd1_bar0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) 				.ncells = ARRAY_SIZE(sta2x11_mfd1_bar0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) 			},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) 			[1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) 				.cells = sta2x11_mfd1_bar1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) 				.ncells = ARRAY_SIZE(sta2x11_mfd1_bar1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) 			},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) static void sta2x11_mfd_setup(struct pci_dev *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) 			      struct sta2x11_mfd_setup_data *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) 	int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) 	for (i = 0; i < ARRAY_SIZE(sd->bars); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) 		for (j = 0; j < sd->bars[i].ncells; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) 			sd->bars[i].cells[j].pdata_size = sizeof(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) 			sd->bars[i].cells[j].platform_data = &pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) static int sta2x11_mfd_probe(struct pci_dev *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) 			     const struct pci_device_id *pci_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) 	int err, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) 	struct sta2x11_mfd_setup_data *setup_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) 	dev_info(&pdev->dev, "%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) 	err = pci_enable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) 	if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) 		dev_err(&pdev->dev, "Can't enable device.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) 	err = pci_enable_msi(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) 		dev_info(&pdev->dev, "Enable msi failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) 	setup_data = pci_id->device == PCI_DEVICE_ID_STMICRO_GPIO ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) 		&mfd_setup_data[STA2X11_MFD0] :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) 		&mfd_setup_data[STA2X11_MFD1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) 	/* platform data is the pci device for all of them */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) 	sta2x11_mfd_setup(pdev, setup_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) 	/* Record this pdev before mfd_add_devices: their probe looks for it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) 	if (!sta2x11_mfd_find(pdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) 		sta2x11_mfd_add(pdev, GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) 	/* Just 2 bars for all mfd's at present */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) 	for (i = 0; i < 2; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) 		err = mfd_add_devices(&pdev->dev, -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) 				      setup_data->bars[i].cells,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) 				      setup_data->bars[i].ncells,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) 				      &pdev->resource[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) 				      0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) 		if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) 			dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) 				"mfd_add_devices[%d] failed: %d\n", i, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) 			goto err_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) err_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) 	mfd_remove_devices(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) 	pci_disable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) 	pci_disable_msi(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) 	return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) static const struct pci_device_id sta2x11_mfd_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) 	{PCI_DEVICE(PCI_VENDOR_ID_STMICRO, PCI_DEVICE_ID_STMICRO_GPIO)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) 	{PCI_DEVICE(PCI_VENDOR_ID_STMICRO, PCI_DEVICE_ID_STMICRO_VIC)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) 	{0,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) static struct pci_driver sta2x11_mfd_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) 	.name =		"sta2x11-mfd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) 	.id_table =	sta2x11_mfd_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) 	.probe =	sta2x11_mfd_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) 	.suspend =	sta2x11_mfd_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) 	.resume =	sta2x11_mfd_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) static int __init sta2x11_mfd_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) 	pr_info("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) 	return pci_register_driver(&sta2x11_mfd_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)  * All of this must be ready before "normal" devices like MMCI appear.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)  * But MFD (the pci device) can't be too early. The following choice
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)  * prepares platform drivers very early and probe the PCI device later,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)  * but before other PCI devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) subsys_initcall(sta2x11_drivers_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) rootfs_initcall(sta2x11_mfd_init);