Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /* Copyright (c) 2009-2013, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (c) 2010, Google Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Original authors: Code Aurora Forum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Author: Dima Zavin <dima@android.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *  - Largely rewritten from original to not be an i2c driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #define pr_fmt(fmt) "%s: " fmt, __func__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/ssbi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) /* SSBI 2.0 controller registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define SSBI2_CMD			0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define SSBI2_RD			0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define SSBI2_STATUS			0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define SSBI2_MODE2			0x001C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) /* SSBI_CMD fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define SSBI_CMD_RDWRN			(1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) /* SSBI_STATUS fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define SSBI_STATUS_RD_READY		(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define SSBI_STATUS_READY		(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define SSBI_STATUS_MCHN_BUSY		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) /* SSBI_MODE2 fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define SSBI_MODE2_REG_ADDR_15_8_SHFT	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define SSBI_MODE2_REG_ADDR_15_8_MASK	(0x7f << SSBI_MODE2_REG_ADDR_15_8_SHFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define SET_SSBI_MODE2_REG_ADDR_15_8(MD, AD) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	(((MD) & 0x0F) | ((((AD) >> 8) << SSBI_MODE2_REG_ADDR_15_8_SHFT) & \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	SSBI_MODE2_REG_ADDR_15_8_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) /* SSBI PMIC Arbiter command registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define SSBI_PA_CMD			0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define SSBI_PA_RD_STATUS		0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) /* SSBI_PA_CMD fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define SSBI_PA_CMD_RDWRN		(1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define SSBI_PA_CMD_ADDR_MASK		0x7fff /* REG_ADDR_7_0, REG_ADDR_8_14*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) /* SSBI_PA_RD_STATUS fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define SSBI_PA_RD_STATUS_TRANS_DONE	(1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define SSBI_PA_RD_STATUS_TRANS_DENIED	(1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define SSBI_TIMEOUT_US			100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) enum ssbi_controller_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	MSM_SBI_CTRL_SSBI = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	MSM_SBI_CTRL_SSBI2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	MSM_SBI_CTRL_PMIC_ARBITER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) struct ssbi {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	struct device		*slave;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	void __iomem		*base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	spinlock_t		lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	enum ssbi_controller_type controller_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	int (*read)(struct ssbi *, u16 addr, u8 *buf, int len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	int (*write)(struct ssbi *, u16 addr, const u8 *buf, int len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) static inline u32 ssbi_readl(struct ssbi *ssbi, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	return readl(ssbi->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) static inline void ssbi_writel(struct ssbi *ssbi, u32 val, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	writel(val, ssbi->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86)  * Via private exchange with one of the original authors, the hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87)  * should generally finish a transaction in about 5us.  The worst
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88)  * case, is when using the arbiter and both other CPUs have just
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89)  * started trying to use the SSBI bus will result in a time of about
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90)  * 20us.  It should never take longer than this.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92)  * As such, this wait merely spins, with a udelay.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) static int ssbi_wait_mask(struct ssbi *ssbi, u32 set_mask, u32 clr_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	u32 timeout = SSBI_TIMEOUT_US;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	while (timeout--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		val = ssbi_readl(ssbi, SSBI2_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		if (((val & set_mask) == set_mask) && ((val & clr_mask) == 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 			return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) ssbi_read_bytes(struct ssbi *ssbi, u16 addr, u8 *buf, int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	u32 cmd = SSBI_CMD_RDWRN | ((addr & 0xff) << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	if (ssbi->controller_type == MSM_SBI_CTRL_SSBI2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		u32 mode2 = ssbi_readl(ssbi, SSBI2_MODE2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		mode2 = SET_SSBI_MODE2_REG_ADDR_15_8(mode2, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		ssbi_writel(ssbi, mode2, SSBI2_MODE2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	while (len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		ret = ssbi_wait_mask(ssbi, SSBI_STATUS_READY, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 			goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		ssbi_writel(ssbi, cmd, SSBI2_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		ret = ssbi_wait_mask(ssbi, SSBI_STATUS_RD_READY, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 			goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		*buf++ = ssbi_readl(ssbi, SSBI2_RD) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		len--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) ssbi_write_bytes(struct ssbi *ssbi, u16 addr, const u8 *buf, int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	if (ssbi->controller_type == MSM_SBI_CTRL_SSBI2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		u32 mode2 = ssbi_readl(ssbi, SSBI2_MODE2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		mode2 = SET_SSBI_MODE2_REG_ADDR_15_8(mode2, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		ssbi_writel(ssbi, mode2, SSBI2_MODE2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	while (len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		ret = ssbi_wait_mask(ssbi, SSBI_STATUS_READY, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 			goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		ssbi_writel(ssbi, ((addr & 0xff) << 16) | *buf, SSBI2_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		ret = ssbi_wait_mask(ssbi, 0, SSBI_STATUS_MCHN_BUSY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 			goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		buf++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		len--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)  * See ssbi_wait_mask for an explanation of the time and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)  * busywait.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static inline int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) ssbi_pa_transfer(struct ssbi *ssbi, u32 cmd, u8 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	u32 timeout = SSBI_TIMEOUT_US;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	u32 rd_status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	ssbi_writel(ssbi, cmd, SSBI_PA_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	while (timeout--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		rd_status = ssbi_readl(ssbi, SSBI_PA_RD_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		if (rd_status & SSBI_PA_RD_STATUS_TRANS_DENIED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 			return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		if (rd_status & SSBI_PA_RD_STATUS_TRANS_DONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 			if (data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 				*data = rd_status & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 			return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) ssbi_pa_read_bytes(struct ssbi *ssbi, u16 addr, u8 *buf, int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	u32 cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	cmd = SSBI_PA_CMD_RDWRN | (addr & SSBI_PA_CMD_ADDR_MASK) << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	while (len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		ret = ssbi_pa_transfer(ssbi, cmd, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 			goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		buf++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		len--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) ssbi_pa_write_bytes(struct ssbi *ssbi, u16 addr, const u8 *buf, int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	u32 cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	while (len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		cmd = (addr & SSBI_PA_CMD_ADDR_MASK) << 8 | *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		ret = ssbi_pa_transfer(ssbi, cmd, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 			goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		buf++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		len--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) int ssbi_read(struct device *dev, u16 addr, u8 *buf, int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	struct ssbi *ssbi = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	spin_lock_irqsave(&ssbi->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	ret = ssbi->read(ssbi, addr, buf, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	spin_unlock_irqrestore(&ssbi->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) EXPORT_SYMBOL_GPL(ssbi_read);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) int ssbi_write(struct device *dev, u16 addr, const u8 *buf, int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	struct ssbi *ssbi = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	spin_lock_irqsave(&ssbi->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	ret = ssbi->write(ssbi, addr, buf, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	spin_unlock_irqrestore(&ssbi->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) EXPORT_SYMBOL_GPL(ssbi_write);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static int ssbi_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	struct resource *mem_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	struct ssbi *ssbi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	const char *type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	ssbi = devm_kzalloc(&pdev->dev, sizeof(*ssbi), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	if (!ssbi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	ssbi->base = devm_ioremap_resource(&pdev->dev, mem_res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	if (IS_ERR(ssbi->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		return PTR_ERR(ssbi->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	platform_set_drvdata(pdev, ssbi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	type = of_get_property(np, "qcom,controller-type", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	if (type == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		dev_err(&pdev->dev, "Missing qcom,controller-type property\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	dev_info(&pdev->dev, "SSBI controller type: '%s'\n", type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	if (strcmp(type, "ssbi") == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		ssbi->controller_type = MSM_SBI_CTRL_SSBI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	else if (strcmp(type, "ssbi2") == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		ssbi->controller_type = MSM_SBI_CTRL_SSBI2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	else if (strcmp(type, "pmic-arbiter") == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 		ssbi->controller_type = MSM_SBI_CTRL_PMIC_ARBITER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 		dev_err(&pdev->dev, "Unknown qcom,controller-type\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	if (ssbi->controller_type == MSM_SBI_CTRL_PMIC_ARBITER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 		ssbi->read = ssbi_pa_read_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 		ssbi->write = ssbi_pa_write_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 		ssbi->read = ssbi_read_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 		ssbi->write = ssbi_write_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	spin_lock_init(&ssbi->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	return devm_of_platform_populate(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static const struct of_device_id ssbi_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	{ .compatible = "qcom,ssbi" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	{}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) MODULE_DEVICE_TABLE(of, ssbi_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static struct platform_driver ssbi_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	.probe		= ssbi_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	.driver		= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 		.name	= "ssbi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 		.of_match_table = ssbi_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) module_platform_driver(ssbi_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) MODULE_VERSION("1.0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) MODULE_ALIAS("platform:ssbi");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) MODULE_AUTHOR("Dima Zavin <dima@android.com>");