^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2017 Spreadtrum Communications Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/mfd/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/mfd/sc27xx-pmic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <uapi/linux/usb/charger.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define SPRD_PMIC_INT_MASK_STATUS 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define SPRD_PMIC_INT_RAW_STATUS 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define SPRD_PMIC_INT_EN 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define SPRD_SC2731_IRQ_BASE 0x140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SPRD_SC2731_IRQ_NUMS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SPRD_SC2731_CHG_DET 0xedc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* PMIC charger detection definition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SPRD_PMIC_CHG_DET_DELAY_US 200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SPRD_PMIC_CHG_DET_TIMEOUT 2000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SPRD_PMIC_CHG_DET_DONE BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SPRD_PMIC_SDP_TYPE BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SPRD_PMIC_DCP_TYPE BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SPRD_PMIC_CDP_TYPE BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SPRD_PMIC_CHG_TYPE_MASK GENMASK(7, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct sprd_pmic {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct regmap_irq *irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct regmap_irq_chip irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct regmap_irq_chip_data *irq_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) const struct sprd_pmic_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct sprd_pmic_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) u32 irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) u32 num_irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) u32 charger_det;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * Since different PMICs of SC27xx series can have different interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * base address and irq number, we should save irq number and irq base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * in the device data structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static const struct sprd_pmic_data sc2731_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) .irq_base = SPRD_SC2731_IRQ_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .num_irqs = SPRD_SC2731_IRQ_NUMS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .charger_det = SPRD_SC2731_CHG_DET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) enum usb_charger_type sprd_pmic_detect_charger_type(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct spi_device *spi = to_spi_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct sprd_pmic *ddata = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) const struct sprd_pmic_data *pdata = ddata->pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) enum usb_charger_type type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) ret = regmap_read_poll_timeout(ddata->regmap, pdata->charger_det, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) (val & SPRD_PMIC_CHG_DET_DONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) SPRD_PMIC_CHG_DET_DELAY_US,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) SPRD_PMIC_CHG_DET_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) dev_err(&spi->dev, "failed to detect charger type\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) return UNKNOWN_TYPE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) switch (val & SPRD_PMIC_CHG_TYPE_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) case SPRD_PMIC_CDP_TYPE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) type = CDP_TYPE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) case SPRD_PMIC_DCP_TYPE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) type = DCP_TYPE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) case SPRD_PMIC_SDP_TYPE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) type = SDP_TYPE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) type = UNKNOWN_TYPE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) return type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) EXPORT_SYMBOL_GPL(sprd_pmic_detect_charger_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static int sprd_pmic_spi_write(void *context, const void *data, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct device *dev = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct spi_device *spi = to_spi_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) return spi_write(spi, data, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static int sprd_pmic_spi_read(void *context,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) const void *reg, size_t reg_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) void *val, size_t val_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct device *dev = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct spi_device *spi = to_spi_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u32 rx_buf[2] = { 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* Now we only support one PMIC register to read every time. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) if (reg_size != sizeof(u32) || val_size != sizeof(u32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* Copy address to read from into first element of SPI buffer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) memcpy(rx_buf, reg, sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) ret = spi_read(spi, rx_buf, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) memcpy(val, rx_buf, val_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static struct regmap_bus sprd_pmic_regmap = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .write = sprd_pmic_spi_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .read = sprd_pmic_spi_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .reg_format_endian_default = REGMAP_ENDIAN_NATIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .val_format_endian_default = REGMAP_ENDIAN_NATIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static const struct regmap_config sprd_pmic_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .max_register = 0xffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static int sprd_pmic_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct sprd_pmic *ddata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) const struct sprd_pmic_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) pdata = of_device_get_match_data(&spi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) if (!pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) dev_err(&spi->dev, "No matching driver data found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) ddata = devm_kzalloc(&spi->dev, sizeof(*ddata), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) if (!ddata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) ddata->regmap = devm_regmap_init(&spi->dev, &sprd_pmic_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) &spi->dev, &sprd_pmic_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) if (IS_ERR(ddata->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) ret = PTR_ERR(ddata->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) dev_err(&spi->dev, "Failed to allocate register map %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) spi_set_drvdata(spi, ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) ddata->dev = &spi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) ddata->irq = spi->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) ddata->pdata = pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) ddata->irq_chip.name = dev_name(&spi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) ddata->irq_chip.status_base =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) pdata->irq_base + SPRD_PMIC_INT_MASK_STATUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) ddata->irq_chip.mask_base = pdata->irq_base + SPRD_PMIC_INT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) ddata->irq_chip.ack_base = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) ddata->irq_chip.num_regs = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) ddata->irq_chip.num_irqs = pdata->num_irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) ddata->irq_chip.mask_invert = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) ddata->irqs = devm_kcalloc(&spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) pdata->num_irqs, sizeof(struct regmap_irq),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (!ddata->irqs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) ddata->irq_chip.irqs = ddata->irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) for (i = 0; i < pdata->num_irqs; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) ddata->irqs[i].mask = BIT(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) ret = devm_regmap_add_irq_chip(&spi->dev, ddata->regmap, ddata->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) IRQF_ONESHOT, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) &ddata->irq_chip, &ddata->irq_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) dev_err(&spi->dev, "Failed to add PMIC irq chip %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) ret = devm_of_platform_populate(&spi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) dev_err(&spi->dev, "Failed to populate sub-devices %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) device_init_wakeup(&spi->dev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static int sprd_pmic_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) struct sprd_pmic *ddata = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) if (device_may_wakeup(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) enable_irq_wake(ddata->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static int sprd_pmic_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) struct sprd_pmic *ddata = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (device_may_wakeup(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) disable_irq_wake(ddata->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static SIMPLE_DEV_PM_OPS(sprd_pmic_pm_ops, sprd_pmic_suspend, sprd_pmic_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static const struct of_device_id sprd_pmic_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) { .compatible = "sprd,sc2731", .data = &sc2731_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) MODULE_DEVICE_TABLE(of, sprd_pmic_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static struct spi_driver sprd_pmic_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .name = "sc27xx-pmic",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .of_match_table = sprd_pmic_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .pm = &sprd_pmic_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .probe = sprd_pmic_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static int __init sprd_pmic_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) return spi_register_driver(&sprd_pmic_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) subsys_initcall(sprd_pmic_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) static void __exit sprd_pmic_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) spi_unregister_driver(&sprd_pmic_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) module_exit(sprd_pmic_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) MODULE_DESCRIPTION("Spreadtrum SC27xx PMICs driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) MODULE_AUTHOR("Baolin Wang <baolin.wang@spreadtrum.com>");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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