Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) // Copyright (c) 2011-2014 Samsung Electronics Co., Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) //              http://www.samsung.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/mfd/samsung/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/mfd/samsung/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/mfd/samsung/s2mps11.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/mfd/samsung/s2mps14.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/mfd/samsung/s2mpu02.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/mfd/samsung/s5m8763.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/mfd/samsung/s5m8767.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) static const struct regmap_irq s2mps11_irqs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 	[S2MPS11_IRQ_PWRONF] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 		.reg_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 		.mask = S2MPS11_IRQ_PWRONF_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	[S2MPS11_IRQ_PWRONR] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 		.reg_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 		.mask = S2MPS11_IRQ_PWRONR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	[S2MPS11_IRQ_JIGONBF] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 		.reg_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 		.mask = S2MPS11_IRQ_JIGONBF_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	[S2MPS11_IRQ_JIGONBR] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 		.reg_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 		.mask = S2MPS11_IRQ_JIGONBR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	[S2MPS11_IRQ_ACOKBF] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 		.reg_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 		.mask = S2MPS11_IRQ_ACOKBF_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	[S2MPS11_IRQ_ACOKBR] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 		.reg_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 		.mask = S2MPS11_IRQ_ACOKBR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	[S2MPS11_IRQ_PWRON1S] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 		.reg_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 		.mask = S2MPS11_IRQ_PWRON1S_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	[S2MPS11_IRQ_MRB] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 		.reg_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 		.mask = S2MPS11_IRQ_MRB_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	[S2MPS11_IRQ_RTC60S] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 		.reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 		.mask = S2MPS11_IRQ_RTC60S_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	[S2MPS11_IRQ_RTCA1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 		.reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 		.mask = S2MPS11_IRQ_RTCA1_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	[S2MPS11_IRQ_RTCA0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 		.reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 		.mask = S2MPS11_IRQ_RTCA0_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	[S2MPS11_IRQ_SMPL] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 		.reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 		.mask = S2MPS11_IRQ_SMPL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	[S2MPS11_IRQ_RTC1S] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 		.reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 		.mask = S2MPS11_IRQ_RTC1S_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	[S2MPS11_IRQ_WTSR] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		.reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		.mask = S2MPS11_IRQ_WTSR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	[S2MPS11_IRQ_INT120C] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 		.reg_offset = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 		.mask = S2MPS11_IRQ_INT120C_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	[S2MPS11_IRQ_INT140C] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		.reg_offset = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		.mask = S2MPS11_IRQ_INT140C_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) static const struct regmap_irq s2mps14_irqs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	[S2MPS14_IRQ_PWRONF] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		.reg_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		.mask = S2MPS11_IRQ_PWRONF_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	[S2MPS14_IRQ_PWRONR] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		.reg_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		.mask = S2MPS11_IRQ_PWRONR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	[S2MPS14_IRQ_JIGONBF] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		.reg_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		.mask = S2MPS11_IRQ_JIGONBF_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	[S2MPS14_IRQ_JIGONBR] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		.reg_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		.mask = S2MPS11_IRQ_JIGONBR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	[S2MPS14_IRQ_ACOKBF] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		.reg_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		.mask = S2MPS11_IRQ_ACOKBF_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	[S2MPS14_IRQ_ACOKBR] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		.reg_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		.mask = S2MPS11_IRQ_ACOKBR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	[S2MPS14_IRQ_PWRON1S] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 		.reg_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		.mask = S2MPS11_IRQ_PWRON1S_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	[S2MPS14_IRQ_MRB] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		.reg_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		.mask = S2MPS11_IRQ_MRB_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	[S2MPS14_IRQ_RTC60S] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		.reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		.mask = S2MPS11_IRQ_RTC60S_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	[S2MPS14_IRQ_RTCA1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		.reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		.mask = S2MPS11_IRQ_RTCA1_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	[S2MPS14_IRQ_RTCA0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		.reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		.mask = S2MPS11_IRQ_RTCA0_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	[S2MPS14_IRQ_SMPL] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		.reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		.mask = S2MPS11_IRQ_SMPL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	[S2MPS14_IRQ_RTC1S] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		.reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		.mask = S2MPS11_IRQ_RTC1S_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	[S2MPS14_IRQ_WTSR] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		.reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		.mask = S2MPS11_IRQ_WTSR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	[S2MPS14_IRQ_INT120C] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		.reg_offset = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		.mask = S2MPS11_IRQ_INT120C_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	[S2MPS14_IRQ_INT140C] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		.reg_offset = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		.mask = S2MPS11_IRQ_INT140C_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	[S2MPS14_IRQ_TSD] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		.reg_offset = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		.mask = S2MPS14_IRQ_TSD_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static const struct regmap_irq s2mpu02_irqs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	[S2MPU02_IRQ_PWRONF] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		.reg_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		.mask = S2MPS11_IRQ_PWRONF_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	[S2MPU02_IRQ_PWRONR] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		.reg_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		.mask = S2MPS11_IRQ_PWRONR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	[S2MPU02_IRQ_JIGONBF] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		.reg_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		.mask = S2MPS11_IRQ_JIGONBF_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	[S2MPU02_IRQ_JIGONBR] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		.reg_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		.mask = S2MPS11_IRQ_JIGONBR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	[S2MPU02_IRQ_ACOKBF] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		.reg_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		.mask = S2MPS11_IRQ_ACOKBF_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	[S2MPU02_IRQ_ACOKBR] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		.reg_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		.mask = S2MPS11_IRQ_ACOKBR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	[S2MPU02_IRQ_PWRON1S] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		.reg_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		.mask = S2MPS11_IRQ_PWRON1S_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	[S2MPU02_IRQ_MRB] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		.reg_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		.mask = S2MPS11_IRQ_MRB_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	[S2MPU02_IRQ_RTC60S] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		.reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		.mask = S2MPS11_IRQ_RTC60S_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	[S2MPU02_IRQ_RTCA1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		.reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		.mask = S2MPS11_IRQ_RTCA1_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	[S2MPU02_IRQ_RTCA0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		.reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		.mask = S2MPS11_IRQ_RTCA0_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	[S2MPU02_IRQ_SMPL] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		.reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		.mask = S2MPS11_IRQ_SMPL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	[S2MPU02_IRQ_RTC1S] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		.reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		.mask = S2MPS11_IRQ_RTC1S_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	[S2MPU02_IRQ_WTSR] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		.reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		.mask = S2MPS11_IRQ_WTSR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	[S2MPU02_IRQ_INT120C] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		.reg_offset = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		.mask = S2MPS11_IRQ_INT120C_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	[S2MPU02_IRQ_INT140C] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		.reg_offset = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		.mask = S2MPS11_IRQ_INT140C_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	[S2MPU02_IRQ_TSD] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		.reg_offset = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		.mask = S2MPS14_IRQ_TSD_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static const struct regmap_irq s5m8767_irqs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	[S5M8767_IRQ_PWRR] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		.reg_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		.mask = S5M8767_IRQ_PWRR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	[S5M8767_IRQ_PWRF] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		.reg_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		.mask = S5M8767_IRQ_PWRF_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	[S5M8767_IRQ_PWR1S] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		.reg_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		.mask = S5M8767_IRQ_PWR1S_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	[S5M8767_IRQ_JIGR] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 		.reg_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		.mask = S5M8767_IRQ_JIGR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	[S5M8767_IRQ_JIGF] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		.reg_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		.mask = S5M8767_IRQ_JIGF_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	[S5M8767_IRQ_LOWBAT2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		.reg_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		.mask = S5M8767_IRQ_LOWBAT2_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	[S5M8767_IRQ_LOWBAT1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		.reg_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		.mask = S5M8767_IRQ_LOWBAT1_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	[S5M8767_IRQ_MRB] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		.reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		.mask = S5M8767_IRQ_MRB_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	[S5M8767_IRQ_DVSOK2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		.reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		.mask = S5M8767_IRQ_DVSOK2_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	[S5M8767_IRQ_DVSOK3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		.reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		.mask = S5M8767_IRQ_DVSOK3_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	[S5M8767_IRQ_DVSOK4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		.reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		.mask = S5M8767_IRQ_DVSOK4_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	[S5M8767_IRQ_RTC60S] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		.reg_offset = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		.mask = S5M8767_IRQ_RTC60S_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	[S5M8767_IRQ_RTCA1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		.reg_offset = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 		.mask = S5M8767_IRQ_RTCA1_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	[S5M8767_IRQ_RTCA2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		.reg_offset = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		.mask = S5M8767_IRQ_RTCA2_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	[S5M8767_IRQ_SMPL] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		.reg_offset = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		.mask = S5M8767_IRQ_SMPL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	[S5M8767_IRQ_RTC1S] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 		.reg_offset = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		.mask = S5M8767_IRQ_RTC1S_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	[S5M8767_IRQ_WTSR] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 		.reg_offset = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 		.mask = S5M8767_IRQ_WTSR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static const struct regmap_irq s5m8763_irqs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	[S5M8763_IRQ_DCINF] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 		.reg_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 		.mask = S5M8763_IRQ_DCINF_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	[S5M8763_IRQ_DCINR] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 		.reg_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 		.mask = S5M8763_IRQ_DCINR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	[S5M8763_IRQ_JIGF] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 		.reg_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 		.mask = S5M8763_IRQ_JIGF_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	[S5M8763_IRQ_JIGR] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 		.reg_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 		.mask = S5M8763_IRQ_JIGR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	[S5M8763_IRQ_PWRONF] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 		.reg_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 		.mask = S5M8763_IRQ_PWRONF_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	[S5M8763_IRQ_PWRONR] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 		.reg_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 		.mask = S5M8763_IRQ_PWRONR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	[S5M8763_IRQ_WTSREVNT] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 		.reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 		.mask = S5M8763_IRQ_WTSREVNT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	[S5M8763_IRQ_SMPLEVNT] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 		.reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 		.mask = S5M8763_IRQ_SMPLEVNT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	[S5M8763_IRQ_ALARM1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 		.reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 		.mask = S5M8763_IRQ_ALARM1_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	[S5M8763_IRQ_ALARM0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 		.reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 		.mask = S5M8763_IRQ_ALARM0_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	[S5M8763_IRQ_ONKEY1S] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 		.reg_offset = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 		.mask = S5M8763_IRQ_ONKEY1S_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	[S5M8763_IRQ_TOPOFFR] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 		.reg_offset = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 		.mask = S5M8763_IRQ_TOPOFFR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	[S5M8763_IRQ_DCINOVPR] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 		.reg_offset = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 		.mask = S5M8763_IRQ_DCINOVPR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	[S5M8763_IRQ_CHGRSTF] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 		.reg_offset = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 		.mask = S5M8763_IRQ_CHGRSTF_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	[S5M8763_IRQ_DONER] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 		.reg_offset = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 		.mask = S5M8763_IRQ_DONER_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	[S5M8763_IRQ_CHGFAULT] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 		.reg_offset = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 		.mask = S5M8763_IRQ_CHGFAULT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	[S5M8763_IRQ_LOBAT1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 		.reg_offset = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 		.mask = S5M8763_IRQ_LOBAT1_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	[S5M8763_IRQ_LOBAT2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 		.reg_offset = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 		.mask = S5M8763_IRQ_LOBAT2_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) static const struct regmap_irq_chip s2mps11_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	.name = "s2mps11",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	.irqs = s2mps11_irqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	.num_irqs = ARRAY_SIZE(s2mps11_irqs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	.num_regs = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	.status_base = S2MPS11_REG_INT1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	.mask_base = S2MPS11_REG_INT1M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	.ack_base = S2MPS11_REG_INT1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define S2MPS1X_IRQ_CHIP_COMMON_DATA		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	.irqs = s2mps14_irqs,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	.num_irqs = ARRAY_SIZE(s2mps14_irqs),	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	.num_regs = 3,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	.status_base = S2MPS14_REG_INT1,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	.mask_base = S2MPS14_REG_INT1M,		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	.ack_base = S2MPS14_REG_INT1		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) static const struct regmap_irq_chip s2mps13_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	.name = "s2mps13",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	S2MPS1X_IRQ_CHIP_COMMON_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) static const struct regmap_irq_chip s2mps14_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	.name = "s2mps14",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	S2MPS1X_IRQ_CHIP_COMMON_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) static const struct regmap_irq_chip s2mps15_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	.name = "s2mps15",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	S2MPS1X_IRQ_CHIP_COMMON_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) static const struct regmap_irq_chip s2mpu02_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	.name = "s2mpu02",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	.irqs = s2mpu02_irqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	.num_irqs = ARRAY_SIZE(s2mpu02_irqs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	.num_regs = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	.status_base = S2MPU02_REG_INT1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	.mask_base = S2MPU02_REG_INT1M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 	.ack_base = S2MPU02_REG_INT1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) static const struct regmap_irq_chip s5m8767_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 	.name = "s5m8767",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 	.irqs = s5m8767_irqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 	.num_irqs = ARRAY_SIZE(s5m8767_irqs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	.num_regs = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 	.status_base = S5M8767_REG_INT1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 	.mask_base = S5M8767_REG_INT1M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 	.ack_base = S5M8767_REG_INT1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) static const struct regmap_irq_chip s5m8763_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 	.name = "s5m8763",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 	.irqs = s5m8763_irqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 	.num_irqs = ARRAY_SIZE(s5m8763_irqs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 	.num_regs = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 	.status_base = S5M8763_REG_IRQ1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 	.mask_base = S5M8763_REG_IRQM1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 	.ack_base = S5M8763_REG_IRQ1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) int sec_irq_init(struct sec_pmic_dev *sec_pmic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 	int type = sec_pmic->device_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 	const struct regmap_irq_chip *sec_irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 	if (!sec_pmic->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 		dev_warn(sec_pmic->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 			 "No interrupt specified, no interrupts\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 		sec_pmic->irq_base = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 	switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 	case S5M8763X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 		sec_irq_chip = &s5m8763_irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 	case S5M8767X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 		sec_irq_chip = &s5m8767_irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 	case S2MPA01:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 		sec_irq_chip = &s2mps14_irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 	case S2MPS11X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 		sec_irq_chip = &s2mps11_irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 	case S2MPS13X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 		sec_irq_chip = &s2mps13_irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 	case S2MPS14X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 		sec_irq_chip = &s2mps14_irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 	case S2MPS15X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 		sec_irq_chip = &s2mps15_irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 	case S2MPU02:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 		sec_irq_chip = &s2mpu02_irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 		dev_err(sec_pmic->dev, "Unknown device type %lu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 			sec_pmic->device_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 	ret = devm_regmap_add_irq_chip(sec_pmic->dev, sec_pmic->regmap_pmic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 				       sec_pmic->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 				       IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 				       sec_pmic->irq_base, sec_irq_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 				       &sec_pmic->irq_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 	if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 		dev_err(sec_pmic->dev, "Failed to register IRQ chip: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 	 * The rtc-s5m driver requests S2MPS14_IRQ_RTCA0 also for S2MPS11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) 	 * so the interrupt number must be consistent.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) 	BUILD_BUG_ON(((enum s2mps14_irq)S2MPS11_IRQ_RTCA0) != S2MPS14_IRQ_RTCA0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) EXPORT_SYMBOL_GPL(sec_irq_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) MODULE_AUTHOR("Sangbeom Kim <sbkim73@samsung.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) MODULE_AUTHOR("Chanwoo Choi <cw00.choi@samsung.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) MODULE_AUTHOR("Krzysztof Kozlowski <krzk@kernel.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) MODULE_DESCRIPTION("Interrupt support for the S5M MFD");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) MODULE_LICENSE("GPL");