^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // Copyright (C) 2019 ROHM Semiconductors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) // ROHM BD71828 PMIC driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/gpio_keys.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/input.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/mfd/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/mfd/rohm-bd71828.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) static struct gpio_keys_button button = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) .code = KEY_POWER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) .gpio = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) .type = EV_KEY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) static struct gpio_keys_platform_data bd71828_powerkey_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) .buttons = &button,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) .nbuttons = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) .name = "bd71828-pwrkey",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static const struct resource rtc_irqs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) DEFINE_RES_IRQ_NAMED(BD71828_INT_RTC0, "bd71828-rtc-alm-0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) DEFINE_RES_IRQ_NAMED(BD71828_INT_RTC1, "bd71828-rtc-alm-1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) DEFINE_RES_IRQ_NAMED(BD71828_INT_RTC2, "bd71828-rtc-alm-2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static struct mfd_cell bd71828_mfd_cells[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) { .name = "bd71828-pmic", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) { .name = "bd71828-gpio", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) { .name = "bd71828-led", .of_compatible = "rohm,bd71828-leds" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * We use BD71837 driver to drive the clock block. Only differences to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * BD70528 clock gate are the register address and mask.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) { .name = "bd71828-clk", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) { .name = "bd71827-power", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) .name = "bd71828-rtc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) .resources = rtc_irqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .num_resources = ARRAY_SIZE(rtc_irqs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) .name = "gpio-keys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .platform_data = &bd71828_powerkey_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) .pdata_size = sizeof(bd71828_powerkey_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static const struct regmap_range volatile_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .range_min = BD71828_REG_PS_CTRL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .range_max = BD71828_REG_PS_CTRL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) .range_min = BD71828_REG_PS_CTRL_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .range_max = BD71828_REG_PS_CTRL_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .range_min = BD71828_REG_RTC_SEC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .range_max = BD71828_REG_RTC_YEAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * For now make all charger registers volatile because many
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * needs to be and because the charger block is not that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * performance critical.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .range_min = BD71828_REG_CHG_STATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .range_max = BD71828_REG_CHG_FULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .range_min = BD71828_REG_INT_MAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) .range_max = BD71828_REG_IO_STAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static const struct regmap_access_table volatile_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .yes_ranges = &volatile_ranges[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .n_yes_ranges = ARRAY_SIZE(volatile_ranges),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static struct regmap_config bd71828_regmap = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .volatile_table = &volatile_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .max_register = BD71828_MAX_REGISTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .cache_type = REGCACHE_RBTREE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * Mapping of main IRQ register bits to sub-IRQ register offsets so that we can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * access corect sub-IRQ registers based on bits that are set in main IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static unsigned int bit0_offsets[] = {11}; /* RTC IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static unsigned int bit1_offsets[] = {10}; /* TEMP IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static unsigned int bit2_offsets[] = {6, 7, 8, 9}; /* BAT MON IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static unsigned int bit3_offsets[] = {5}; /* BAT IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static unsigned int bit4_offsets[] = {4}; /* CHG IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static unsigned int bit5_offsets[] = {3}; /* VSYS IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static unsigned int bit6_offsets[] = {1, 2}; /* DCIN IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static unsigned int bit7_offsets[] = {0}; /* BUCK IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static struct regmap_irq_sub_irq_map bd71828_sub_irq_offsets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) REGMAP_IRQ_MAIN_REG_OFFSET(bit0_offsets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) REGMAP_IRQ_MAIN_REG_OFFSET(bit1_offsets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) REGMAP_IRQ_MAIN_REG_OFFSET(bit2_offsets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) REGMAP_IRQ_MAIN_REG_OFFSET(bit3_offsets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) REGMAP_IRQ_MAIN_REG_OFFSET(bit4_offsets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) REGMAP_IRQ_MAIN_REG_OFFSET(bit5_offsets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) REGMAP_IRQ_MAIN_REG_OFFSET(bit6_offsets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) REGMAP_IRQ_MAIN_REG_OFFSET(bit7_offsets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static struct regmap_irq bd71828_irqs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) REGMAP_IRQ_REG(BD71828_INT_BUCK1_OCP, 0, BD71828_INT_BUCK1_OCP_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) REGMAP_IRQ_REG(BD71828_INT_BUCK2_OCP, 0, BD71828_INT_BUCK2_OCP_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) REGMAP_IRQ_REG(BD71828_INT_BUCK3_OCP, 0, BD71828_INT_BUCK3_OCP_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) REGMAP_IRQ_REG(BD71828_INT_BUCK4_OCP, 0, BD71828_INT_BUCK4_OCP_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) REGMAP_IRQ_REG(BD71828_INT_BUCK5_OCP, 0, BD71828_INT_BUCK5_OCP_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) REGMAP_IRQ_REG(BD71828_INT_BUCK6_OCP, 0, BD71828_INT_BUCK6_OCP_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) REGMAP_IRQ_REG(BD71828_INT_BUCK7_OCP, 0, BD71828_INT_BUCK7_OCP_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) REGMAP_IRQ_REG(BD71828_INT_PGFAULT, 0, BD71828_INT_PGFAULT_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* DCIN1 interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) REGMAP_IRQ_REG(BD71828_INT_DCIN_DET, 1, BD71828_INT_DCIN_DET_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) REGMAP_IRQ_REG(BD71828_INT_DCIN_RMV, 1, BD71828_INT_DCIN_RMV_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) REGMAP_IRQ_REG(BD71828_INT_CLPS_OUT, 1, BD71828_INT_CLPS_OUT_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) REGMAP_IRQ_REG(BD71828_INT_CLPS_IN, 1, BD71828_INT_CLPS_IN_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* DCIN2 interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) REGMAP_IRQ_REG(BD71828_INT_DCIN_MON_RES, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) BD71828_INT_DCIN_MON_RES_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) REGMAP_IRQ_REG(BD71828_INT_DCIN_MON_DET, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) BD71828_INT_DCIN_MON_DET_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) REGMAP_IRQ_REG(BD71828_INT_LONGPUSH, 2, BD71828_INT_LONGPUSH_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) REGMAP_IRQ_REG(BD71828_INT_MIDPUSH, 2, BD71828_INT_MIDPUSH_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) REGMAP_IRQ_REG(BD71828_INT_SHORTPUSH, 2, BD71828_INT_SHORTPUSH_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) REGMAP_IRQ_REG(BD71828_INT_PUSH, 2, BD71828_INT_PUSH_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) REGMAP_IRQ_REG(BD71828_INT_WDOG, 2, BD71828_INT_WDOG_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) REGMAP_IRQ_REG(BD71828_INT_SWRESET, 2, BD71828_INT_SWRESET_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* Vsys */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) REGMAP_IRQ_REG(BD71828_INT_VSYS_UV_RES, 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) BD71828_INT_VSYS_UV_RES_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) REGMAP_IRQ_REG(BD71828_INT_VSYS_UV_DET, 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) BD71828_INT_VSYS_UV_DET_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) REGMAP_IRQ_REG(BD71828_INT_VSYS_LOW_RES, 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) BD71828_INT_VSYS_LOW_RES_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) REGMAP_IRQ_REG(BD71828_INT_VSYS_LOW_DET, 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) BD71828_INT_VSYS_LOW_DET_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) REGMAP_IRQ_REG(BD71828_INT_VSYS_HALL_IN, 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) BD71828_INT_VSYS_HALL_IN_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) REGMAP_IRQ_REG(BD71828_INT_VSYS_HALL_TOGGLE, 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) BD71828_INT_VSYS_HALL_TOGGLE_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) REGMAP_IRQ_REG(BD71828_INT_VSYS_MON_RES, 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) BD71828_INT_VSYS_MON_RES_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) REGMAP_IRQ_REG(BD71828_INT_VSYS_MON_DET, 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) BD71828_INT_VSYS_MON_DET_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /* Charger */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) REGMAP_IRQ_REG(BD71828_INT_CHG_DCIN_ILIM, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) BD71828_INT_CHG_DCIN_ILIM_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) REGMAP_IRQ_REG(BD71828_INT_CHG_TOPOFF_TO_DONE, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) BD71828_INT_CHG_TOPOFF_TO_DONE_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) REGMAP_IRQ_REG(BD71828_INT_CHG_WDG_TEMP, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) BD71828_INT_CHG_WDG_TEMP_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) REGMAP_IRQ_REG(BD71828_INT_CHG_WDG_TIME, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) BD71828_INT_CHG_WDG_TIME_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) REGMAP_IRQ_REG(BD71828_INT_CHG_RECHARGE_RES, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) BD71828_INT_CHG_RECHARGE_RES_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) REGMAP_IRQ_REG(BD71828_INT_CHG_RECHARGE_DET, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) BD71828_INT_CHG_RECHARGE_DET_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) REGMAP_IRQ_REG(BD71828_INT_CHG_RANGED_TEMP_TRANSITION, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) BD71828_INT_CHG_RANGED_TEMP_TRANSITION_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) REGMAP_IRQ_REG(BD71828_INT_CHG_STATE_TRANSITION, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) BD71828_INT_CHG_STATE_TRANSITION_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /* Battery */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) REGMAP_IRQ_REG(BD71828_INT_BAT_TEMP_NORMAL, 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) BD71828_INT_BAT_TEMP_NORMAL_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) REGMAP_IRQ_REG(BD71828_INT_BAT_TEMP_ERANGE, 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) BD71828_INT_BAT_TEMP_ERANGE_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) REGMAP_IRQ_REG(BD71828_INT_BAT_TEMP_WARN, 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) BD71828_INT_BAT_TEMP_WARN_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) REGMAP_IRQ_REG(BD71828_INT_BAT_REMOVED, 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) BD71828_INT_BAT_REMOVED_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) REGMAP_IRQ_REG(BD71828_INT_BAT_DETECTED, 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) BD71828_INT_BAT_DETECTED_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) REGMAP_IRQ_REG(BD71828_INT_THERM_REMOVED, 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) BD71828_INT_THERM_REMOVED_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) REGMAP_IRQ_REG(BD71828_INT_THERM_DETECTED, 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) BD71828_INT_THERM_DETECTED_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /* Battery Mon 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) REGMAP_IRQ_REG(BD71828_INT_BAT_DEAD, 6, BD71828_INT_BAT_DEAD_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) REGMAP_IRQ_REG(BD71828_INT_BAT_SHORTC_RES, 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) BD71828_INT_BAT_SHORTC_RES_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) REGMAP_IRQ_REG(BD71828_INT_BAT_SHORTC_DET, 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) BD71828_INT_BAT_SHORTC_DET_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) REGMAP_IRQ_REG(BD71828_INT_BAT_LOW_VOLT_RES, 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) BD71828_INT_BAT_LOW_VOLT_RES_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) REGMAP_IRQ_REG(BD71828_INT_BAT_LOW_VOLT_DET, 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) BD71828_INT_BAT_LOW_VOLT_DET_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_VOLT_RES, 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) BD71828_INT_BAT_OVER_VOLT_RES_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_VOLT_DET, 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) BD71828_INT_BAT_OVER_VOLT_DET_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /* Battery Mon 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) REGMAP_IRQ_REG(BD71828_INT_BAT_MON_RES, 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) BD71828_INT_BAT_MON_RES_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) REGMAP_IRQ_REG(BD71828_INT_BAT_MON_DET, 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) BD71828_INT_BAT_MON_DET_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /* Battery Mon 3 (Coulomb counter) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) REGMAP_IRQ_REG(BD71828_INT_BAT_CC_MON1, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) BD71828_INT_BAT_CC_MON1_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) REGMAP_IRQ_REG(BD71828_INT_BAT_CC_MON2, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) BD71828_INT_BAT_CC_MON2_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) REGMAP_IRQ_REG(BD71828_INT_BAT_CC_MON3, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) BD71828_INT_BAT_CC_MON3_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /* Battery Mon 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_CURR_1_RES, 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) BD71828_INT_BAT_OVER_CURR_1_RES_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_CURR_1_DET, 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) BD71828_INT_BAT_OVER_CURR_1_DET_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_CURR_2_RES, 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) BD71828_INT_BAT_OVER_CURR_2_RES_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_CURR_2_DET, 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) BD71828_INT_BAT_OVER_CURR_2_DET_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_CURR_3_RES, 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) BD71828_INT_BAT_OVER_CURR_3_RES_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_CURR_3_DET, 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) BD71828_INT_BAT_OVER_CURR_3_DET_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /* Temperature */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) REGMAP_IRQ_REG(BD71828_INT_TEMP_BAT_LOW_RES, 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) BD71828_INT_TEMP_BAT_LOW_RES_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) REGMAP_IRQ_REG(BD71828_INT_TEMP_BAT_LOW_DET, 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) BD71828_INT_TEMP_BAT_LOW_DET_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) REGMAP_IRQ_REG(BD71828_INT_TEMP_BAT_HI_RES, 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) BD71828_INT_TEMP_BAT_HI_RES_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) REGMAP_IRQ_REG(BD71828_INT_TEMP_BAT_HI_DET, 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) BD71828_INT_TEMP_BAT_HI_DET_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) REGMAP_IRQ_REG(BD71828_INT_TEMP_CHIP_OVER_125_RES, 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) BD71828_INT_TEMP_CHIP_OVER_125_RES_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) REGMAP_IRQ_REG(BD71828_INT_TEMP_CHIP_OVER_125_DET, 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) BD71828_INT_TEMP_CHIP_OVER_125_DET_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) REGMAP_IRQ_REG(BD71828_INT_TEMP_CHIP_OVER_VF_DET, 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) BD71828_INT_TEMP_CHIP_OVER_VF_DET_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) REGMAP_IRQ_REG(BD71828_INT_TEMP_CHIP_OVER_VF_RES, 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) BD71828_INT_TEMP_CHIP_OVER_VF_RES_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /* RTC Alarm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) REGMAP_IRQ_REG(BD71828_INT_RTC0, 11, BD71828_INT_RTC0_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) REGMAP_IRQ_REG(BD71828_INT_RTC1, 11, BD71828_INT_RTC1_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) REGMAP_IRQ_REG(BD71828_INT_RTC2, 11, BD71828_INT_RTC2_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static struct regmap_irq_chip bd71828_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .name = "bd71828_irq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .main_status = BD71828_REG_INT_MAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .irqs = &bd71828_irqs[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .num_irqs = ARRAY_SIZE(bd71828_irqs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .status_base = BD71828_REG_INT_BUCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .mask_base = BD71828_REG_INT_MASK_BUCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .ack_base = BD71828_REG_INT_BUCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .mask_invert = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .init_ack_masked = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .num_regs = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .num_main_regs = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .sub_reg_offsets = &bd71828_sub_irq_offsets[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .num_main_status_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .irq_reg_stride = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static int bd71828_i2c_probe(struct i2c_client *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) struct rohm_regmap_dev *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) struct regmap_irq_chip_data *irq_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) if (!i2c->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) dev_err(&i2c->dev, "No IRQ configured\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) chip = devm_kzalloc(&i2c->dev, sizeof(*chip), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) if (!chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) dev_set_drvdata(&i2c->dev, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) chip->regmap = devm_regmap_init_i2c(i2c, &bd71828_regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) if (IS_ERR(chip->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) dev_err(&i2c->dev, "Failed to initialize Regmap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) return PTR_ERR(chip->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) ret = devm_regmap_add_irq_chip(&i2c->dev, chip->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) i2c->irq, IRQF_ONESHOT, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) &bd71828_irq_chip, &irq_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) dev_err(&i2c->dev, "Failed to add IRQ chip\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) dev_dbg(&i2c->dev, "Registered %d IRQs for chip\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) bd71828_irq_chip.num_irqs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) ret = regmap_irq_get_virq(irq_data, BD71828_INT_SHORTPUSH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) dev_err(&i2c->dev, "Failed to get the power-key IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) button.irq = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) ret = devm_mfd_add_devices(&i2c->dev, PLATFORM_DEVID_AUTO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) bd71828_mfd_cells,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) ARRAY_SIZE(bd71828_mfd_cells), NULL, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) regmap_irq_get_domain(irq_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) dev_err(&i2c->dev, "Failed to create subdevices\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static const struct of_device_id bd71828_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) { .compatible = "rohm,bd71828", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) MODULE_DEVICE_TABLE(of, bd71828_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static struct i2c_driver bd71828_drv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) .name = "rohm-bd71828",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .of_match_table = bd71828_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .probe_new = &bd71828_i2c_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) module_i2c_driver(bd71828_drv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) MODULE_AUTHOR("Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) MODULE_DESCRIPTION("ROHM BD71828 Power Management IC driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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