^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // Copyright (C) 2019 ROHM Semiconductors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) // ROHM BD70528 PMIC driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/mfd/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/mfd/rohm-bd70528.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define BD70528_NUM_OF_GPIOS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) static const struct resource rtc_irqs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) DEFINE_RES_IRQ_NAMED(BD70528_INT_RTC_ALARM, "bd70528-rtc-alm"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) DEFINE_RES_IRQ_NAMED(BD70528_INT_ELPS_TIM, "bd70528-elapsed-timer"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) static const struct resource charger_irqs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) DEFINE_RES_IRQ_NAMED(BD70528_INT_BAT_OV_RES, "bd70528-bat-ov-res"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) DEFINE_RES_IRQ_NAMED(BD70528_INT_BAT_OV_DET, "bd70528-bat-ov-det"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) DEFINE_RES_IRQ_NAMED(BD70528_INT_DBAT_DET, "bd70528-bat-dead"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) DEFINE_RES_IRQ_NAMED(BD70528_INT_BATTSD_COLD_RES, "bd70528-bat-warmed"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) DEFINE_RES_IRQ_NAMED(BD70528_INT_BATTSD_COLD_DET, "bd70528-bat-cold"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) DEFINE_RES_IRQ_NAMED(BD70528_INT_BATTSD_HOT_RES, "bd70528-bat-cooled"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) DEFINE_RES_IRQ_NAMED(BD70528_INT_BATTSD_HOT_DET, "bd70528-bat-hot"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) DEFINE_RES_IRQ_NAMED(BD70528_INT_CHG_TSD, "bd70528-chg-tshd"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) DEFINE_RES_IRQ_NAMED(BD70528_INT_BAT_RMV, "bd70528-bat-removed"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) DEFINE_RES_IRQ_NAMED(BD70528_INT_BAT_DET, "bd70528-bat-detected"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) DEFINE_RES_IRQ_NAMED(BD70528_INT_DCIN2_OV_RES, "bd70528-dcin2-ov-res"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) DEFINE_RES_IRQ_NAMED(BD70528_INT_DCIN2_OV_DET, "bd70528-dcin2-ov-det"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) DEFINE_RES_IRQ_NAMED(BD70528_INT_DCIN2_RMV, "bd70528-dcin2-removed"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) DEFINE_RES_IRQ_NAMED(BD70528_INT_DCIN2_DET, "bd70528-dcin2-detected"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) DEFINE_RES_IRQ_NAMED(BD70528_INT_DCIN1_RMV, "bd70528-dcin1-removed"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) DEFINE_RES_IRQ_NAMED(BD70528_INT_DCIN1_DET, "bd70528-dcin1-detected"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static struct mfd_cell bd70528_mfd_cells[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) { .name = "bd70528-pmic", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) { .name = "bd70528-gpio", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * We use BD71837 driver to drive the clock block. Only differences to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * BD70528 clock gate are the register address and mask.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) { .name = "bd70528-clk", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) { .name = "bd70528-wdt", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .name = "bd70528-power",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) .resources = charger_irqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) .num_resources = ARRAY_SIZE(charger_irqs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .name = "bd70528-rtc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .resources = rtc_irqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .num_resources = ARRAY_SIZE(rtc_irqs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static const struct regmap_range volatile_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .range_min = BD70528_REG_INT_MAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .range_max = BD70528_REG_INT_OP_FAIL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) .range_min = BD70528_REG_RTC_COUNT_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) .range_max = BD70528_REG_RTC_ALM_REPEAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * WDT control reg is special. Magic values must be written to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * it in order to change the control. Should not be cached.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .range_min = BD70528_REG_WDT_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .range_max = BD70528_REG_WDT_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * BD70528 also contains a few other registers which require
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * magic sequences to be written in order to update the value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * At least SHIPMODE, HWRESET, WARMRESET,and STANDBY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .range_min = BD70528_REG_SHIPMODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .range_max = BD70528_REG_STANDBY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static const struct regmap_access_table volatile_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .yes_ranges = &volatile_ranges[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .n_yes_ranges = ARRAY_SIZE(volatile_ranges),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static struct regmap_config bd70528_regmap = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .volatile_table = &volatile_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .max_register = BD70528_MAX_REGISTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .cache_type = REGCACHE_RBTREE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * Mapping of main IRQ register bits to sub-IRQ register offsets so that we can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * access corect sub-IRQ registers based on bits that are set in main IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static unsigned int bit0_offsets[] = {0}; /* Shutdown */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static unsigned int bit1_offsets[] = {1}; /* Power failure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static unsigned int bit2_offsets[] = {2}; /* VR FAULT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static unsigned int bit3_offsets[] = {3}; /* PMU interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static unsigned int bit4_offsets[] = {4, 5}; /* Charger 1 and Charger 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static unsigned int bit5_offsets[] = {6}; /* RTC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static unsigned int bit6_offsets[] = {7}; /* GPIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static unsigned int bit7_offsets[] = {8}; /* Invalid operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static struct regmap_irq_sub_irq_map bd70528_sub_irq_offsets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) REGMAP_IRQ_MAIN_REG_OFFSET(bit0_offsets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) REGMAP_IRQ_MAIN_REG_OFFSET(bit1_offsets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) REGMAP_IRQ_MAIN_REG_OFFSET(bit2_offsets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) REGMAP_IRQ_MAIN_REG_OFFSET(bit3_offsets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) REGMAP_IRQ_MAIN_REG_OFFSET(bit4_offsets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) REGMAP_IRQ_MAIN_REG_OFFSET(bit5_offsets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) REGMAP_IRQ_MAIN_REG_OFFSET(bit6_offsets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) REGMAP_IRQ_MAIN_REG_OFFSET(bit7_offsets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static struct regmap_irq bd70528_irqs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) REGMAP_IRQ_REG(BD70528_INT_LONGPUSH, 0, BD70528_INT_LONGPUSH_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) REGMAP_IRQ_REG(BD70528_INT_WDT, 0, BD70528_INT_WDT_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) REGMAP_IRQ_REG(BD70528_INT_HWRESET, 0, BD70528_INT_HWRESET_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) REGMAP_IRQ_REG(BD70528_INT_RSTB_FAULT, 0, BD70528_INT_RSTB_FAULT_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) REGMAP_IRQ_REG(BD70528_INT_VBAT_UVLO, 0, BD70528_INT_VBAT_UVLO_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) REGMAP_IRQ_REG(BD70528_INT_TSD, 0, BD70528_INT_TSD_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) REGMAP_IRQ_REG(BD70528_INT_RSTIN, 0, BD70528_INT_RSTIN_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) REGMAP_IRQ_REG(BD70528_INT_BUCK1_FAULT, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) BD70528_INT_BUCK1_FAULT_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) REGMAP_IRQ_REG(BD70528_INT_BUCK2_FAULT, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) BD70528_INT_BUCK2_FAULT_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) REGMAP_IRQ_REG(BD70528_INT_BUCK3_FAULT, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) BD70528_INT_BUCK3_FAULT_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) REGMAP_IRQ_REG(BD70528_INT_LDO1_FAULT, 1, BD70528_INT_LDO1_FAULT_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) REGMAP_IRQ_REG(BD70528_INT_LDO2_FAULT, 1, BD70528_INT_LDO2_FAULT_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) REGMAP_IRQ_REG(BD70528_INT_LDO3_FAULT, 1, BD70528_INT_LDO3_FAULT_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) REGMAP_IRQ_REG(BD70528_INT_LED1_FAULT, 1, BD70528_INT_LED1_FAULT_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) REGMAP_IRQ_REG(BD70528_INT_LED2_FAULT, 1, BD70528_INT_LED2_FAULT_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) REGMAP_IRQ_REG(BD70528_INT_BUCK1_OCP, 2, BD70528_INT_BUCK1_OCP_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) REGMAP_IRQ_REG(BD70528_INT_BUCK2_OCP, 2, BD70528_INT_BUCK2_OCP_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) REGMAP_IRQ_REG(BD70528_INT_BUCK3_OCP, 2, BD70528_INT_BUCK3_OCP_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) REGMAP_IRQ_REG(BD70528_INT_LED1_OCP, 2, BD70528_INT_LED1_OCP_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) REGMAP_IRQ_REG(BD70528_INT_LED2_OCP, 2, BD70528_INT_LED2_OCP_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) REGMAP_IRQ_REG(BD70528_INT_BUCK1_FULLON, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) BD70528_INT_BUCK1_FULLON_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) REGMAP_IRQ_REG(BD70528_INT_BUCK2_FULLON, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) BD70528_INT_BUCK2_FULLON_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) REGMAP_IRQ_REG(BD70528_INT_SHORTPUSH, 3, BD70528_INT_SHORTPUSH_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) REGMAP_IRQ_REG(BD70528_INT_AUTO_WAKEUP, 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) BD70528_INT_AUTO_WAKEUP_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) REGMAP_IRQ_REG(BD70528_INT_STATE_CHANGE, 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) BD70528_INT_STATE_CHANGE_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) REGMAP_IRQ_REG(BD70528_INT_BAT_OV_RES, 4, BD70528_INT_BAT_OV_RES_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) REGMAP_IRQ_REG(BD70528_INT_BAT_OV_DET, 4, BD70528_INT_BAT_OV_DET_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) REGMAP_IRQ_REG(BD70528_INT_DBAT_DET, 4, BD70528_INT_DBAT_DET_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) REGMAP_IRQ_REG(BD70528_INT_BATTSD_COLD_RES, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) BD70528_INT_BATTSD_COLD_RES_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) REGMAP_IRQ_REG(BD70528_INT_BATTSD_COLD_DET, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) BD70528_INT_BATTSD_COLD_DET_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) REGMAP_IRQ_REG(BD70528_INT_BATTSD_HOT_RES, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) BD70528_INT_BATTSD_HOT_RES_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) REGMAP_IRQ_REG(BD70528_INT_BATTSD_HOT_DET, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) BD70528_INT_BATTSD_HOT_DET_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) REGMAP_IRQ_REG(BD70528_INT_CHG_TSD, 4, BD70528_INT_CHG_TSD_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) REGMAP_IRQ_REG(BD70528_INT_BAT_RMV, 5, BD70528_INT_BAT_RMV_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) REGMAP_IRQ_REG(BD70528_INT_BAT_DET, 5, BD70528_INT_BAT_DET_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) REGMAP_IRQ_REG(BD70528_INT_DCIN2_OV_RES, 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) BD70528_INT_DCIN2_OV_RES_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) REGMAP_IRQ_REG(BD70528_INT_DCIN2_OV_DET, 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) BD70528_INT_DCIN2_OV_DET_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) REGMAP_IRQ_REG(BD70528_INT_DCIN2_RMV, 5, BD70528_INT_DCIN2_RMV_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) REGMAP_IRQ_REG(BD70528_INT_DCIN2_DET, 5, BD70528_INT_DCIN2_DET_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) REGMAP_IRQ_REG(BD70528_INT_DCIN1_RMV, 5, BD70528_INT_DCIN1_RMV_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) REGMAP_IRQ_REG(BD70528_INT_DCIN1_DET, 5, BD70528_INT_DCIN1_DET_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) REGMAP_IRQ_REG(BD70528_INT_RTC_ALARM, 6, BD70528_INT_RTC_ALARM_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) REGMAP_IRQ_REG(BD70528_INT_ELPS_TIM, 6, BD70528_INT_ELPS_TIM_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) REGMAP_IRQ_REG(BD70528_INT_GPIO0, 7, BD70528_INT_GPIO0_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) REGMAP_IRQ_REG(BD70528_INT_GPIO1, 7, BD70528_INT_GPIO1_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) REGMAP_IRQ_REG(BD70528_INT_GPIO2, 7, BD70528_INT_GPIO2_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) REGMAP_IRQ_REG(BD70528_INT_GPIO3, 7, BD70528_INT_GPIO3_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) REGMAP_IRQ_REG(BD70528_INT_BUCK1_DVS_OPFAIL, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) BD70528_INT_BUCK1_DVS_OPFAIL_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) REGMAP_IRQ_REG(BD70528_INT_BUCK2_DVS_OPFAIL, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) BD70528_INT_BUCK2_DVS_OPFAIL_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) REGMAP_IRQ_REG(BD70528_INT_BUCK3_DVS_OPFAIL, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) BD70528_INT_BUCK3_DVS_OPFAIL_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) REGMAP_IRQ_REG(BD70528_INT_LED1_VOLT_OPFAIL, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) BD70528_INT_LED1_VOLT_OPFAIL_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) REGMAP_IRQ_REG(BD70528_INT_LED2_VOLT_OPFAIL, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) BD70528_INT_LED2_VOLT_OPFAIL_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static struct regmap_irq_chip bd70528_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .name = "bd70528_irq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .main_status = BD70528_REG_INT_MAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .irqs = &bd70528_irqs[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .num_irqs = ARRAY_SIZE(bd70528_irqs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .status_base = BD70528_REG_INT_SHDN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .mask_base = BD70528_REG_INT_SHDN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .ack_base = BD70528_REG_INT_SHDN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .type_base = BD70528_REG_GPIO1_IN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .init_ack_masked = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .num_regs = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .num_main_regs = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .num_type_reg = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .sub_reg_offsets = &bd70528_sub_irq_offsets[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .num_main_status_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .irq_reg_stride = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static int bd70528_i2c_probe(struct i2c_client *i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) struct bd70528_data *bd70528;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) struct regmap_irq_chip_data *irq_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) if (!i2c->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) dev_err(&i2c->dev, "No IRQ configured\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) bd70528 = devm_kzalloc(&i2c->dev, sizeof(*bd70528), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) if (!bd70528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) mutex_init(&bd70528->rtc_timer_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) dev_set_drvdata(&i2c->dev, &bd70528->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) bd70528->chip.regmap = devm_regmap_init_i2c(i2c, &bd70528_regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) if (IS_ERR(bd70528->chip.regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) dev_err(&i2c->dev, "Failed to initialize Regmap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) return PTR_ERR(bd70528->chip.regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) * Disallow type setting for all IRQs by default as most of them do not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) * support setting type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) for (i = 0; i < ARRAY_SIZE(bd70528_irqs); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) bd70528_irqs[i].type.types_supported = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /* Set IRQ typesetting information for GPIO pins 0 - 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) for (i = 0; i < BD70528_NUM_OF_GPIOS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) struct regmap_irq_type *type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) type = &bd70528_irqs[BD70528_INT_GPIO0 + i].type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) type->type_reg_offset = 2 * i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) type->type_rising_val = 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) type->type_falling_val = 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) type->type_level_high_val = 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) type->type_level_low_val = 0x50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) type->types_supported = (IRQ_TYPE_EDGE_BOTH |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) ret = devm_regmap_add_irq_chip(&i2c->dev, bd70528->chip.regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) i2c->irq, IRQF_ONESHOT, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) &bd70528_irq_chip, &irq_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) dev_err(&i2c->dev, "Failed to add IRQ chip\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) dev_dbg(&i2c->dev, "Registered %d IRQs for chip\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) bd70528_irq_chip.num_irqs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) * BD70528 IRQ controller is not touching the main mask register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) * So enable the GPIO block interrupts at main level. We can just leave
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) * them enabled as the IRQ controller should disable IRQs from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) * sub-registers when IRQ is disabled or freed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) ret = regmap_update_bits(bd70528->chip.regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) BD70528_REG_INT_MAIN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) BD70528_INT_GPIO_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) ret = devm_mfd_add_devices(&i2c->dev, PLATFORM_DEVID_AUTO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) bd70528_mfd_cells,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) ARRAY_SIZE(bd70528_mfd_cells), NULL, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) regmap_irq_get_domain(irq_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) dev_err(&i2c->dev, "Failed to create subdevices\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static const struct of_device_id bd70528_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) { .compatible = "rohm,bd70528", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) MODULE_DEVICE_TABLE(of, bd70528_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static struct i2c_driver bd70528_drv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .name = "rohm-bd70528",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .of_match_table = bd70528_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .probe = &bd70528_i2c_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) module_i2c_driver(bd70528_drv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) MODULE_AUTHOR("Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) MODULE_DESCRIPTION("ROHM BD70528 Power Management IC driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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