^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * MFD core driver for Rockchip RK808/RK818
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2014-2018, Fuzhou Rockchip Electronics Co., Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Chris Zhong <zyw@rock-chips.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Author: Zhang Qing <zhangqing@rock-chips.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Copyright (C) 2016 PHYTEC Messtechnik GmbH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Author: Wadim Egorov <w.egorov@phytec.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/mfd/rk808.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/mfd/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/reboot.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/syscore_ops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/pinctrl/devinfo.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) struct rk808_reg_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) int addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) int mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) int value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static bool rk808_is_volatile_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * Notes:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * - Technically the ROUND_30s bit makes RTC_CTRL_REG volatile, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * we don't use that feature. It's better to cache.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * - It's unlikely we care that RK808_DEVCTRL_REG is volatile since
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * bits are cleared in case when we shutoff anyway, but better safe.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) case RK808_SECONDS_REG ... RK808_WEEKS_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) case RK808_RTC_STATUS_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) case RK808_VB_MON_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) case RK808_THERMAL_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) case RK808_DCDC_UV_STS_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) case RK808_LDO_UV_STS_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) case RK808_DCDC_PG_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) case RK808_LDO_PG_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) case RK808_DEVCTRL_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) case RK808_INT_STS_REG1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) case RK808_INT_STS_REG2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static bool rk817_is_volatile_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * Notes:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * - Technically the ROUND_30s bit makes RTC_CTRL_REG volatile, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * we don't use that feature. It's better to cache.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) case RK817_SECONDS_REG ... RK817_WEEKS_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) case RK817_RTC_STATUS_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) case RK817_ADC_CONFIG0 ... RK817_CURE_ADC_K0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) case RK817_CHRG_STS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) case RK817_CHRG_OUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) case RK817_CHRG_IN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) case RK817_SYS_STS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) case RK817_INT_STS_REG0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) case RK817_INT_STS_REG1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) case RK817_INT_STS_REG2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static bool rk818_is_volatile_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * Notes:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * - Technically the ROUND_30s bit makes RTC_CTRL_REG volatile, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * we don't use that feature. It's better to cache.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * - It's unlikely we care that RK808_DEVCTRL_REG is volatile since
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * bits are cleared in case when we shutoff anyway, but better safe.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) case RK808_SECONDS_REG ... RK808_WEEKS_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) case RK808_RTC_STATUS_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) case RK808_VB_MON_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) case RK808_THERMAL_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) case RK808_DCDC_EN_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) case RK808_LDO_EN_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) case RK808_DCDC_UV_STS_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) case RK808_LDO_UV_STS_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) case RK808_DCDC_PG_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) case RK808_LDO_PG_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) case RK808_DEVCTRL_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) case RK808_INT_STS_REG1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) case RK808_INT_STS_REG2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) case RK808_INT_STS_MSK_REG1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) case RK808_INT_STS_MSK_REG2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) case RK816_INT_STS_REG1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) case RK816_INT_STS_MSK_REG1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) case RK818_SUP_STS_REG ... RK818_SAVE_DATA19:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static const struct regmap_config rk818_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .max_register = RK818_SAVE_DATA19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .cache_type = REGCACHE_RBTREE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .volatile_reg = rk818_is_volatile_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static const struct regmap_config rk805_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .max_register = RK805_OFF_SOURCE_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .cache_type = REGCACHE_RBTREE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .volatile_reg = rk808_is_volatile_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static const struct regmap_config rk808_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .max_register = RK808_IO_POL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .cache_type = REGCACHE_RBTREE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .volatile_reg = rk808_is_volatile_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static const struct regmap_config rk816_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .max_register = RK816_DATA18_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .cache_type = REGCACHE_RBTREE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .volatile_reg = rk818_is_volatile_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static const struct regmap_config rk817_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .max_register = RK817_GPIO_INT_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .num_reg_defaults_raw = RK817_GPIO_INT_CFG + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .cache_type = REGCACHE_RBTREE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .volatile_reg = rk817_is_volatile_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static struct resource rtc_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) DEFINE_RES_IRQ(RK808_IRQ_RTC_ALARM),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static struct resource rk816_rtc_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) DEFINE_RES_IRQ(RK816_IRQ_RTC_ALARM),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static struct resource rk817_rtc_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) DEFINE_RES_IRQ(RK817_IRQ_RTC_ALARM),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static struct resource rk805_key_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) DEFINE_RES_IRQ(RK805_IRQ_PWRON_FALL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) DEFINE_RES_IRQ(RK805_IRQ_PWRON_RISE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static struct resource rk816_pwrkey_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) DEFINE_RES_IRQ(RK816_IRQ_PWRON_FALL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) DEFINE_RES_IRQ(RK816_IRQ_PWRON_RISE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static struct resource rk817_pwrkey_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) DEFINE_RES_IRQ(RK817_IRQ_PWRON_FALL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) DEFINE_RES_IRQ(RK817_IRQ_PWRON_RISE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static const struct mfd_cell rk805s[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) { .name = "rk808-clkout", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) { .name = "rk808-regulator", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) { .name = "rk805-pinctrl", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .name = "rk808-rtc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .num_resources = ARRAY_SIZE(rtc_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .resources = &rtc_resources[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) { .name = "rk805-pwrkey",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .num_resources = ARRAY_SIZE(rk805_key_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .resources = &rk805_key_resources[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static const struct mfd_cell rk808s[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) { .name = "rk808-clkout", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) { .name = "rk808-regulator", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .name = "rk808-rtc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .num_resources = ARRAY_SIZE(rtc_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .resources = rtc_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static const struct mfd_cell rk816s[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) { .name = "rk808-clkout", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) { .name = "rk808-regulator", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) { .name = "rk805-pinctrl", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) { .name = "rk816-battery", .of_compatible = "rk816-battery", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .name = "rk805-pwrkey",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .num_resources = ARRAY_SIZE(rk816_pwrkey_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .resources = &rk816_pwrkey_resources[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .name = "rk808-rtc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .num_resources = ARRAY_SIZE(rk816_rtc_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .resources = &rk816_rtc_resources[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static const struct mfd_cell rk817s[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) { .name = "rk808-clkout",},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) { .name = "rk808-regulator",},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) { .name = "rk817-battery", .of_compatible = "rk817,battery", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) { .name = "rk817-charger", .of_compatible = "rk817,charger", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .name = "rk805-pwrkey",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) .num_resources = ARRAY_SIZE(rk817_pwrkey_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) .resources = &rk817_pwrkey_resources[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .name = "rk808-rtc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .num_resources = ARRAY_SIZE(rk817_rtc_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .resources = &rk817_rtc_resources[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .name = "rk817-codec",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .of_compatible = "rockchip,rk817-codec",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static const struct mfd_cell rk818s[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) { .name = "rk808-clkout", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) { .name = "rk808-regulator", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) { .name = "rk818-battery", .of_compatible = "rk818-battery", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) { .name = "rk818-charger", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .name = "rk808-rtc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .num_resources = ARRAY_SIZE(rtc_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .resources = rtc_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static const struct rk808_reg_data rk805_pre_init_reg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {RK805_BUCK4_CONFIG_REG, BUCK_ILMIN_MASK, BUCK_ILMIN_400MA},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {RK805_GPIO_IO_POL_REG, SLP_SD_MSK, SLEEP_FUN},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {RK805_THERMAL_REG, TEMP_HOTDIE_MSK, TEMP115C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {RK808_RTC_CTRL_REG, RTC_STOP, RTC_STOP},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static struct rk808_reg_data rk805_suspend_reg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {RK805_BUCK3_CONFIG_REG, PWM_MODE_MSK, AUTO_PWM_MODE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static struct rk808_reg_data rk805_resume_reg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {RK805_BUCK3_CONFIG_REG, PWM_MODE_MSK, FPWM_MODE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static const struct rk808_reg_data rk808_pre_init_reg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) { RK808_BUCK3_CONFIG_REG, BUCK_ILMIN_MASK, BUCK_ILMIN_150MA },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) { RK808_BUCK4_CONFIG_REG, BUCK_ILMIN_MASK, BUCK_ILMIN_200MA },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) { RK808_BOOST_CONFIG_REG, BOOST_ILMIN_MASK, BOOST_ILMIN_100MA },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) { RK808_BUCK1_CONFIG_REG, BUCK1_RATE_MASK, BUCK_ILMIN_200MA },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) { RK808_BUCK2_CONFIG_REG, BUCK2_RATE_MASK, BUCK_ILMIN_200MA },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) { RK808_DCDC_UV_ACT_REG, BUCK_UV_ACT_MASK, BUCK_UV_ACT_DISABLE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) { RK808_RTC_CTRL_REG, RTC_STOP, RTC_STOP},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) { RK808_VB_MON_REG, MASK_ALL, VB_LO_ACT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) VB_LO_SEL_3500MV },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static const struct rk808_reg_data rk816_pre_init_reg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) /* buck4 Max ILMIT*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) { RK816_BUCK4_CONFIG_REG, REG_WRITE_MSK, BUCK4_MAX_ILIMIT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /* hotdie temperature: 105c*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) { RK816_THERMAL_REG, REG_WRITE_MSK, TEMP105C },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /* set buck 12.5mv/us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) { RK816_BUCK1_CONFIG_REG, BUCK_RATE_MSK, BUCK_RATE_12_5MV_US },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) { RK816_BUCK2_CONFIG_REG, BUCK_RATE_MSK, BUCK_RATE_12_5MV_US },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /* enable RTC_PERIOD & RTC_ALARM int */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) { RK816_INT_STS_MSK_REG2, REG_WRITE_MSK, RTC_PERIOD_ALARM_INT_EN },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /* set bat 3.0 low and act shutdown */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) { RK816_VB_MON_REG, VBAT_LOW_VOL_MASK | VBAT_LOW_ACT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) RK816_VBAT_LOW_3V0 | EN_VABT_LOW_SHUT_DOWN },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) /* enable PWRON rising/faling int */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) { RK816_INT_STS_MSK_REG1, REG_WRITE_MSK, RK816_PWRON_FALL_RISE_INT_EN },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) /* enable PLUG IN/OUT int */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) { RK816_INT_STS_MSK_REG3, REG_WRITE_MSK, PLUGIN_OUT_INT_EN },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /* clear int flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) { RK816_INT_STS_REG1, REG_WRITE_MSK, ALL_INT_FLAGS_ST },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) { RK816_INT_STS_REG2, REG_WRITE_MSK, ALL_INT_FLAGS_ST },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) { RK816_INT_STS_REG3, REG_WRITE_MSK, ALL_INT_FLAGS_ST },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) { RK816_DCDC_EN_REG2, BOOST_EN_MASK, BOOST_DISABLE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) /* set write mask bit 1, otherwise 'is_enabled()' get wrong status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) { RK816_LDO_EN_REG1, REGS_WMSK, REGS_WMSK },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) { RK816_LDO_EN_REG2, REGS_WMSK, REGS_WMSK },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static const struct rk808_reg_data rk817_pre_init_reg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {RK817_SYS_CFG(3), RK817_SLPPOL_MSK, RK817_SLPPOL_L},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {RK817_RTC_CTRL_REG, RTC_STOP, RTC_STOP},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {RK817_GPIO_INT_CFG, RK817_INT_POL_MSK, RK817_INT_POL_L},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {RK817_SYS_CFG(1), RK817_HOTDIE_TEMP_MSK | RK817_TSD_TEMP_MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) RK817_HOTDIE_105 | RK817_TSD_140},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static const struct rk808_reg_data rk818_pre_init_reg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) /* improve efficiency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) { RK818_BUCK2_CONFIG_REG, BUCK2_RATE_MASK, BUCK_ILMIN_250MA },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) { RK818_BUCK4_CONFIG_REG, BUCK_ILMIN_MASK, BUCK_ILMIN_250MA },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) { RK818_BOOST_CONFIG_REG, BOOST_ILMIN_MASK, BOOST_ILMIN_100MA },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) { RK818_USB_CTRL_REG, RK818_USB_ILIM_SEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) RK818_USB_ILMIN_2000MA },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) /* close charger when usb lower then 3.4V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) { RK818_USB_CTRL_REG, RK818_USB_CHG_SD_VSEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) (0x7 << 4) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) /* no action when vref */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) { RK818_H5V_EN_REG, BIT(1), RK818_REF_RDY_CTRL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) /* enable HDMI 5V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) { RK818_H5V_EN_REG, BIT(0), RK818_H5V_EN },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) { RK808_RTC_CTRL_REG, RTC_STOP, RTC_STOP},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) { RK808_VB_MON_REG, MASK_ALL, VB_LO_ACT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) VB_LO_SEL_3500MV },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {RK808_CLK32OUT_REG, CLK32KOUT2_FUNC_MASK, CLK32KOUT2_FUNC},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static const struct regmap_irq rk805_irqs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) [RK805_IRQ_PWRON_RISE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) .mask = RK805_IRQ_PWRON_RISE_MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) .reg_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) [RK805_IRQ_VB_LOW] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) .mask = RK805_IRQ_VB_LOW_MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) .reg_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) [RK805_IRQ_PWRON] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .mask = RK805_IRQ_PWRON_MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .reg_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) [RK805_IRQ_PWRON_LP] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .mask = RK805_IRQ_PWRON_LP_MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .reg_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) [RK805_IRQ_HOTDIE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .mask = RK805_IRQ_HOTDIE_MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) .reg_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) [RK805_IRQ_RTC_ALARM] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .mask = RK805_IRQ_RTC_ALARM_MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .reg_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) [RK805_IRQ_RTC_PERIOD] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .mask = RK805_IRQ_RTC_PERIOD_MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .reg_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) [RK805_IRQ_PWRON_FALL] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .mask = RK805_IRQ_PWRON_FALL_MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .reg_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static const struct regmap_irq rk808_irqs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) /* INT_STS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) [RK808_IRQ_VOUT_LO] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .mask = RK808_IRQ_VOUT_LO_MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .reg_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) [RK808_IRQ_VB_LO] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .mask = RK808_IRQ_VB_LO_MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .reg_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) [RK808_IRQ_PWRON] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) .mask = RK808_IRQ_PWRON_MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) .reg_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) [RK808_IRQ_PWRON_LP] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .mask = RK808_IRQ_PWRON_LP_MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .reg_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) [RK808_IRQ_HOTDIE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) .mask = RK808_IRQ_HOTDIE_MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) .reg_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) [RK808_IRQ_RTC_ALARM] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .mask = RK808_IRQ_RTC_ALARM_MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) .reg_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) [RK808_IRQ_RTC_PERIOD] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) .mask = RK808_IRQ_RTC_PERIOD_MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) .reg_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) /* INT_STS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) [RK808_IRQ_PLUG_IN_INT] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) .mask = RK808_IRQ_PLUG_IN_INT_MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) .reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) [RK808_IRQ_PLUG_OUT_INT] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) .mask = RK808_IRQ_PLUG_OUT_INT_MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) .reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) static struct rk808_reg_data rk816_suspend_reg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) /* set bat 3.4v low and act irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) { RK816_VB_MON_REG, VBAT_LOW_VOL_MASK | VBAT_LOW_ACT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) RK816_VBAT_LOW_3V4 | EN_VBAT_LOW_IRQ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) static struct rk808_reg_data rk816_resume_reg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) /* set bat 3.0v low and act shutdown */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) { RK816_VB_MON_REG, VBAT_LOW_VOL_MASK | VBAT_LOW_ACT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) RK816_VBAT_LOW_3V0 | EN_VABT_LOW_SHUT_DOWN },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static const struct regmap_irq rk816_irqs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) /* INT_STS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) [RK816_IRQ_PWRON_FALL] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) .mask = RK816_IRQ_PWRON_FALL_MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) .reg_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) [RK816_IRQ_PWRON_RISE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) .mask = RK816_IRQ_PWRON_RISE_MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) .reg_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) [RK816_IRQ_VB_LOW] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) .mask = RK816_IRQ_VB_LOW_MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) .reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) [RK816_IRQ_PWRON] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) .mask = RK816_IRQ_PWRON_MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) .reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) [RK816_IRQ_PWRON_LP] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) .mask = RK816_IRQ_PWRON_LP_MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) .reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) [RK816_IRQ_HOTDIE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) .mask = RK816_IRQ_HOTDIE_MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) .reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) [RK816_IRQ_RTC_ALARM] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) .mask = RK816_IRQ_RTC_ALARM_MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) .reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) [RK816_IRQ_RTC_PERIOD] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) .mask = RK816_IRQ_RTC_PERIOD_MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) .reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) [RK816_IRQ_USB_OV] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) .mask = RK816_IRQ_USB_OV_MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) .reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) static struct rk808_reg_data rk818_suspend_reg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) /* set bat 3.4v low and act irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) { RK808_VB_MON_REG, VBAT_LOW_VOL_MASK | VBAT_LOW_ACT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) RK808_VBAT_LOW_3V4 | EN_VBAT_LOW_IRQ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) static struct rk808_reg_data rk818_resume_reg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) /* set bat 3.0v low and act shutdown */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) { RK808_VB_MON_REG, VBAT_LOW_VOL_MASK | VBAT_LOW_ACT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) RK808_VBAT_LOW_3V0 | EN_VABT_LOW_SHUT_DOWN },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) static const struct regmap_irq rk818_irqs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) /* INT_STS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) [RK818_IRQ_VOUT_LO] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) .mask = RK818_IRQ_VOUT_LO_MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) .reg_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) [RK818_IRQ_VB_LO] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) .mask = RK818_IRQ_VB_LO_MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) .reg_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) [RK818_IRQ_PWRON] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) .mask = RK818_IRQ_PWRON_MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) .reg_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) [RK818_IRQ_PWRON_LP] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) .mask = RK818_IRQ_PWRON_LP_MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) .reg_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) [RK818_IRQ_HOTDIE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) .mask = RK818_IRQ_HOTDIE_MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) .reg_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) [RK818_IRQ_RTC_ALARM] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) .mask = RK818_IRQ_RTC_ALARM_MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) .reg_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) [RK818_IRQ_RTC_PERIOD] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) .mask = RK818_IRQ_RTC_PERIOD_MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) .reg_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) [RK818_IRQ_USB_OV] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) .mask = RK818_IRQ_USB_OV_MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) .reg_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) /* INT_STS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) [RK818_IRQ_PLUG_IN] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) .mask = RK818_IRQ_PLUG_IN_MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) .reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) [RK818_IRQ_PLUG_OUT] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) .mask = RK818_IRQ_PLUG_OUT_MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) .reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) [RK818_IRQ_CHG_OK] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) .mask = RK818_IRQ_CHG_OK_MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) .reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) [RK818_IRQ_CHG_TE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) .mask = RK818_IRQ_CHG_TE_MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) .reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) [RK818_IRQ_CHG_TS1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) .mask = RK818_IRQ_CHG_TS1_MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) .reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) [RK818_IRQ_TS2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) .mask = RK818_IRQ_TS2_MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) .reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) [RK818_IRQ_CHG_CVTLIM] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) .mask = RK818_IRQ_CHG_CVTLIM_MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) .reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) [RK818_IRQ_DISCHG_ILIM] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) .mask = RK818_IRQ_DISCHG_ILIM_MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) .reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) static const struct regmap_irq rk817_irqs[RK817_IRQ_END] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) REGMAP_IRQ_REG_LINE(0, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) REGMAP_IRQ_REG_LINE(1, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) REGMAP_IRQ_REG_LINE(2, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) REGMAP_IRQ_REG_LINE(3, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) REGMAP_IRQ_REG_LINE(4, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) REGMAP_IRQ_REG_LINE(5, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) REGMAP_IRQ_REG_LINE(6, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) REGMAP_IRQ_REG_LINE(7, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) REGMAP_IRQ_REG_LINE(8, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) REGMAP_IRQ_REG_LINE(9, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) REGMAP_IRQ_REG_LINE(10, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) REGMAP_IRQ_REG_LINE(11, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) REGMAP_IRQ_REG_LINE(12, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) REGMAP_IRQ_REG_LINE(13, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) REGMAP_IRQ_REG_LINE(14, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) REGMAP_IRQ_REG_LINE(15, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) REGMAP_IRQ_REG_LINE(16, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) REGMAP_IRQ_REG_LINE(17, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) REGMAP_IRQ_REG_LINE(18, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) REGMAP_IRQ_REG_LINE(19, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) REGMAP_IRQ_REG_LINE(20, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) REGMAP_IRQ_REG_LINE(21, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) REGMAP_IRQ_REG_LINE(22, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) REGMAP_IRQ_REG_LINE(23, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) static struct regmap_irq_chip rk805_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) .name = "rk805",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) .irqs = rk805_irqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) .num_irqs = ARRAY_SIZE(rk805_irqs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) .num_regs = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) .status_base = RK805_INT_STS_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) .mask_base = RK805_INT_STS_MSK_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) .ack_base = RK805_INT_STS_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) .init_ack_masked = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) static const struct regmap_irq_chip rk808_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) .name = "rk808",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) .irqs = rk808_irqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) .num_irqs = ARRAY_SIZE(rk808_irqs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) .num_regs = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) .irq_reg_stride = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) .status_base = RK808_INT_STS_REG1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) .mask_base = RK808_INT_STS_MSK_REG1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) .ack_base = RK808_INT_STS_REG1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) .init_ack_masked = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) static const struct regmap_irq rk816_battery_irqs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) /* INT_STS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) [RK816_IRQ_PLUG_IN] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) .mask = RK816_IRQ_PLUG_IN_MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) .reg_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) [RK816_IRQ_PLUG_OUT] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) .mask = RK816_IRQ_PLUG_OUT_MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) .reg_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) [RK816_IRQ_CHG_OK] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) .mask = RK816_IRQ_CHG_OK_MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) .reg_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) [RK816_IRQ_CHG_TE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) .mask = RK816_IRQ_CHG_TE_MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) .reg_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) [RK816_IRQ_CHG_TS] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) .mask = RK816_IRQ_CHG_TS_MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) .reg_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) [RK816_IRQ_CHG_CVTLIM] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) .mask = RK816_IRQ_CHG_CVTLIM_MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) .reg_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) [RK816_IRQ_DISCHG_ILIM] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) .mask = RK816_IRQ_DISCHG_ILIM_MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) .reg_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) static struct regmap_irq_chip rk816_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) .name = "rk816",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) .irqs = rk816_irqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) .num_irqs = ARRAY_SIZE(rk816_irqs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) .num_regs = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) .irq_reg_stride = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) .status_base = RK816_INT_STS_REG1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) .mask_base = RK816_INT_STS_MSK_REG1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) .ack_base = RK816_INT_STS_REG1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) .init_ack_masked = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) static struct regmap_irq_chip rk816_battery_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) .name = "rk816_battery",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) .irqs = rk816_battery_irqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) .num_irqs = ARRAY_SIZE(rk816_battery_irqs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) .num_regs = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) .status_base = RK816_INT_STS_REG3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) .mask_base = RK816_INT_STS_MSK_REG3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) .ack_base = RK816_INT_STS_REG3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) .init_ack_masked = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) static struct regmap_irq_chip rk817_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) .name = "rk817",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) .irqs = rk817_irqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) .num_irqs = ARRAY_SIZE(rk817_irqs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) .num_regs = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) .irq_reg_stride = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) .status_base = RK817_INT_STS_REG0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) .mask_base = RK817_INT_STS_MSK_REG0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) .ack_base = RK817_INT_STS_REG0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) .init_ack_masked = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) static const struct regmap_irq_chip rk818_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) .name = "rk818",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) .irqs = rk818_irqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) .num_irqs = ARRAY_SIZE(rk818_irqs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) .num_regs = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) .irq_reg_stride = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) .status_base = RK818_INT_STS_REG1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) .mask_base = RK818_INT_STS_MSK_REG1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) .ack_base = RK818_INT_STS_REG1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) .init_ack_masked = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) static struct i2c_client *rk808_i2c_client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) static struct rk808_reg_data *suspend_reg, *resume_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) static int suspend_reg_num, resume_reg_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) static void rk805_device_shutdown_prepare(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) struct rk808 *rk808 = i2c_get_clientdata(rk808_i2c_client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) if (!rk808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) ret = regmap_update_bits(rk808->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) RK805_GPIO_IO_POL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) SLP_SD_MSK, SHUTDOWN_FUN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) dev_err(&rk808_i2c_client->dev, "Failed to shutdown device!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) static void rk817_shutdown_prepare(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) struct rk808 *rk808 = i2c_get_clientdata(rk808_i2c_client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) /* close rtc int when power off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) regmap_update_bits(rk808->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) RK817_INT_STS_MSK_REG0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) (0x3 << 5), (0x3 << 5));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) regmap_update_bits(rk808->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) RK817_RTC_INT_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) (0x3 << 2), (0x0 << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) if (rk808->pins && rk808->pins->p && rk808->pins->power_off) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) ret = regmap_update_bits(rk808->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) RK817_SYS_CFG(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) RK817_SLPPIN_FUNC_MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) SLPPIN_NULL_FUN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) pr_err("shutdown: config SLPPIN_NULL_FUN error!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) ret = regmap_update_bits(rk808->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) RK817_SYS_CFG(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) RK817_SLPPOL_MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) RK817_SLPPOL_H);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) pr_err("shutdown: config RK817_SLPPOL_H error!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) ret = pinctrl_select_state(rk808->pins->p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) rk808->pins->power_off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) pr_info("%s:failed to activate pwroff state\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) /* pmic sleep shutdown function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) ret = regmap_update_bits(rk808->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) RK817_SYS_CFG(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) RK817_SLPPIN_FUNC_MSK, SLPPIN_DN_FUN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) dev_err(&rk808_i2c_client->dev, "Failed to shutdown device!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) /* pmic need the SCL clock to synchronize register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) mdelay(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) static void rk8xx_device_shutdown(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) unsigned int reg, bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) struct rk808 *rk808 = i2c_get_clientdata(rk808_i2c_client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) switch (rk808->variant) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) case RK805_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) reg = RK805_DEV_CTRL_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) bit = DEV_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) case RK808_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) reg = RK808_DEVCTRL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) bit = DEV_OFF_RST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) case RK816_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) reg = RK816_DEV_CTRL_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) bit = DEV_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) case RK818_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) reg = RK818_DEVCTRL_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) bit = DEV_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) ret = regmap_update_bits(rk808->regmap, reg, bit, bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) dev_err(&rk808_i2c_client->dev, "Failed to shutdown device!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) /* Called in syscore shutdown */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) static void (*pm_shutdown)(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) static void rk8xx_syscore_shutdown(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) struct rk808 *rk808 = i2c_get_clientdata(rk808_i2c_client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) if (!rk808) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) dev_warn(&rk808_i2c_client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) "have no rk808, so do nothing here\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) /* close rtc int when power off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) regmap_update_bits(rk808->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) RK808_INT_STS_MSK_REG1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) (0x3 << 5), (0x3 << 5));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) regmap_update_bits(rk808->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) RK808_RTC_INT_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) (0x3 << 2), (0x0 << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) * For PMIC that power off supplies by write register via i2c bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) * it's better to do power off at syscore shutdown here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) * Because when run to kernel's "pm_power_off" call, i2c may has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) * been stopped or PMIC may not be able to get i2c transfer while
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) * there are too many devices are competiting.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) if (system_state == SYSTEM_POWER_OFF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) if (rk808->variant == RK809_ID || rk808->variant == RK817_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) ret = regmap_update_bits(rk808->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) RK817_SYS_CFG(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) RK817_SLPPIN_FUNC_MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) SLPPIN_DN_FUN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) dev_warn(&rk808_i2c_client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) "Cannot switch to power down function\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) if (pm_shutdown) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) dev_info(&rk808_i2c_client->dev, "System power off\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) pm_shutdown();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) mdelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) dev_info(&rk808_i2c_client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) "Power off failed !\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) while (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) static struct syscore_ops rk808_syscore_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) .shutdown = rk8xx_syscore_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) * RK8xx PMICs would do real power off in syscore shutdown, if "pm_power_off"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) * is not assigned(e.g. PSCI is not enabled), we have to provide a dummy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) * callback for it, otherwise there comes a halt in Reboot system call:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) * if ((cmd == LINUX_REBOOT_CMD_POWER_OFF) && !pm_power_off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) * cmd = LINUX_REBOOT_CMD_HALT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) static void rk808_pm_power_off_dummy(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) pr_info("Dummy power off for RK8xx PMICs, should never reach here!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) while (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) static ssize_t rk8xx_dbg_store(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) char cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) u32 input[2], addr, data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) struct rk808 *rk808 = i2c_get_clientdata(rk808_i2c_client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) ret = sscanf(buf, "%c ", &cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) if (ret != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) pr_err("Unknown command\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) case 'w':
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) ret = sscanf(buf, "%c %x %x ", &cmd, &input[0], &input[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) if (ret != 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) pr_err("error! cmd format: echo w [addr] [value]\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) addr = input[0] & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) data = input[1] & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) pr_info("cmd : %c %x %x\n\n", cmd, input[0], input[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) regmap_write(rk808->regmap, addr, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) regmap_read(rk808->regmap, addr, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) pr_info("new: %x %x\n", addr, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) case 'r':
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) ret = sscanf(buf, "%c %x ", &cmd, &input[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) if (ret != 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) pr_err("error! cmd format: echo r [addr]\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) pr_info("cmd : %c %x\n\n", cmd, input[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) addr = input[0] & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) regmap_read(rk808->regmap, addr, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) pr_info("%x %x\n", input[0], data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) pr_err("Unknown command\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) static int rk817_pinctrl_init(struct device *dev, struct rk808 *rk808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) struct platform_device *pinctrl_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) struct pinctrl_state *default_st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) pinctrl_dev = platform_device_alloc("rk805-pinctrl", -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) if (!pinctrl_dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) dev_err(dev, "Alloc pinctrl dev failed!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) pinctrl_dev->dev.parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) ret = platform_device_add(pinctrl_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) platform_device_put(pinctrl_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) dev_err(dev, "Add rk805-pinctrl dev failed!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) if (dev->pins && !IS_ERR(dev->pins->p)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) dev_info(dev, "had get a pinctrl!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) rk808->pins = devm_kzalloc(dev, sizeof(struct rk808_pin_info),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) if (!rk808->pins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) rk808->pins->p = devm_pinctrl_get(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) if (IS_ERR(rk808->pins->p)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) rk808->pins->p = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) dev_err(dev, "no pinctrl handle\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) default_st = pinctrl_lookup_state(rk808->pins->p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) PINCTRL_STATE_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) if (IS_ERR(default_st)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) dev_dbg(dev, "no default pinctrl state\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) ret = pinctrl_select_state(rk808->pins->p, default_st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) dev_dbg(dev, "failed to activate default pinctrl state\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) rk808->pins->power_off = pinctrl_lookup_state(rk808->pins->p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) "pmic-power-off");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) if (IS_ERR(rk808->pins->power_off)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) rk808->pins->power_off = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) dev_dbg(dev, "no power-off pinctrl state\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) rk808->pins->sleep = pinctrl_lookup_state(rk808->pins->p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) "pmic-sleep");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) if (IS_ERR(rk808->pins->sleep)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) rk808->pins->sleep = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) dev_dbg(dev, "no sleep-setting state\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) rk808->pins->reset = pinctrl_lookup_state(rk808->pins->p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) "pmic-reset");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) if (IS_ERR(rk808->pins->reset)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) rk808->pins->reset = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) dev_dbg(dev, "no reset-setting pinctrl state\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) ret = pinctrl_select_state(rk808->pins->p, rk808->pins->reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) dev_dbg(dev, "failed to activate reset-setting pinctrl state\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) struct rk817_reboot_data_t {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) struct rk808 *rk808;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) struct notifier_block reboot_notifier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) static struct rk817_reboot_data_t rk817_reboot_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) static int rk817_reboot_notifier_handler(struct notifier_block *nb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) unsigned long action, void *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) struct rk817_reboot_data_t *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) int value, power_en_active0, power_en_active1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) static const char * const pmic_rst_reg_only_cmd[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) "loader", "bootloader", "fastboot", "recovery",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) "ums", "panic", "watchdog", "charge",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) data = container_of(nb, struct rk817_reboot_data_t, reboot_notifier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) dev = &data->rk808->i2c->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) regmap_read(data->rk808->regmap, RK817_POWER_EN_SAVE0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) &power_en_active0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) if (power_en_active0 != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) regmap_read(data->rk808->regmap, RK817_POWER_EN_SAVE1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) &power_en_active1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) value = power_en_active0 & 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) regmap_write(data->rk808->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) RK817_POWER_EN_REG(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) value | 0xf0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) value = (power_en_active0 & 0xf0) >> 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) regmap_write(data->rk808->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) RK817_POWER_EN_REG(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) value | 0xf0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) value = power_en_active1 & 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) regmap_write(data->rk808->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) RK817_POWER_EN_REG(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) value | 0xf0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) value = (power_en_active1 & 0xf0) >> 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) regmap_write(data->rk808->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) RK817_POWER_EN_REG(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) value | 0xf0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) dev_info(dev, "reboot: not restore POWER_EN\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) if (action != SYS_RESTART || !cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) return NOTIFY_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) * When system restart, there are two rst actions of PMIC sleep if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) * board hardware support:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) * 0b'00: reset the PMIC itself completely.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) * 0b'01: reset the 'RST' related register only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) * In the case of 0b'00, PMIC reset itself which triggers SoC NPOR-reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) * at the same time, so the command: reboot load/bootload/recovery, etc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) * is not effect any more.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) * Here we check if this reboot cmd is what we expect for 0b'01.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) for (i = 0; i < ARRAY_SIZE(pmic_rst_reg_only_cmd); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) if (!strcmp(cmd, pmic_rst_reg_only_cmd[i])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) ret = regmap_update_bits(data->rk808->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) RK817_SYS_CFG(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) RK817_RST_FUNC_MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) RK817_RST_FUNC_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) dev_err(dev, "reboot: force RK817_RST_FUNC_REG error!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) dev_info(dev, "reboot: force RK817_RST_FUNC_REG ok!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) return NOTIFY_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) static void rk817_of_property_prepare(struct rk808 *rk808, struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) u32 inner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) int ret, func, msk, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) ret = of_property_read_u32_index(np, "fb-inner-reg-idxs", 0, &inner);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) if (!ret && inner == RK817_ID_DCDC3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) regmap_update_bits(rk808->regmap, RK817_POWER_CONFIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) RK817_BUCK3_FB_RES_MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) RK817_BUCK3_FB_RES_INTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) regmap_update_bits(rk808->regmap, RK817_POWER_CONFIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) RK817_BUCK3_FB_RES_MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) RK817_BUCK3_FB_RES_EXT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) dev_info(dev, "support dcdc3 fb mode:%d, %d\n", ret, inner);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) ret = of_property_read_u32(np, "pmic-reset-func", &func);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) msk = RK817_SLPPIN_FUNC_MSK | RK817_RST_FUNC_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) val = SLPPIN_NULL_FUN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) if (!ret && func < RK817_RST_FUNC_CNT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) val |= RK817_RST_FUNC_MSK &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) (func << RK817_RST_FUNC_SFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) val |= RK817_RST_FUNC_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) regmap_update_bits(rk808->regmap, RK817_SYS_CFG(3), msk, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) dev_info(dev, "support pmic reset mode:%d,%d\n", ret, func);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) rk817_reboot_data.rk808 = rk808;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) rk817_reboot_data.reboot_notifier.notifier_call =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) rk817_reboot_notifier_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) ret = register_reboot_notifier(&rk817_reboot_data.reboot_notifier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) dev_err(dev, "failed to register reboot nb\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) static struct kobject *rk8xx_kobj;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) static struct device_attribute rk8xx_attrs =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) __ATTR(rk8xx_dbg, 0200, NULL, rk8xx_dbg_store);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) static const struct of_device_id rk808_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) { .compatible = "rockchip,rk805" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) { .compatible = "rockchip,rk808" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) { .compatible = "rockchip,rk809" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) { .compatible = "rockchip,rk816" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) { .compatible = "rockchip,rk817" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) { .compatible = "rockchip,rk818" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) MODULE_DEVICE_TABLE(of, rk808_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) static int rk808_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) struct device_node *np = client->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) struct rk808 *rk808;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) const struct rk808_reg_data *pre_init_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) const struct regmap_irq_chip *battery_irq_chip = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) const struct mfd_cell *cells;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) unsigned char pmic_id_msb, pmic_id_lsb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) u8 on_source = 0, off_source = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) unsigned int on, off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) int pm_off = 0, msb, lsb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) int nr_pre_init_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) int nr_cells;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) void (*of_property_prepare_fn)(struct rk808 *rk808,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) struct device *dev) = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) int (*pinctrl_init)(struct device *dev, struct rk808 *rk808) = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) void (*device_shutdown_fn)(void) = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) rk808 = devm_kzalloc(&client->dev, sizeof(*rk808), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) if (!rk808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) if (of_device_is_compatible(np, "rockchip,rk817") ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) of_device_is_compatible(np, "rockchip,rk809")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) pmic_id_msb = RK817_ID_MSB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) pmic_id_lsb = RK817_ID_LSB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) pmic_id_msb = RK808_ID_MSB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) pmic_id_lsb = RK808_ID_LSB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) /* Read chip variant */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) msb = i2c_smbus_read_byte_data(client, pmic_id_msb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) if (msb < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) dev_err(&client->dev, "failed to read the chip id at 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) RK808_ID_MSB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) return msb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) lsb = i2c_smbus_read_byte_data(client, pmic_id_lsb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) if (lsb < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) dev_err(&client->dev, "failed to read the chip id at 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) RK808_ID_LSB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) return lsb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) rk808->variant = ((msb << 8) | lsb) & RK8XX_ID_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) dev_info(&client->dev, "chip id: 0x%x\n", (unsigned int)rk808->variant);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) switch (rk808->variant) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) case RK805_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) rk808->regmap_cfg = &rk805_regmap_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) rk808->regmap_irq_chip = &rk805_irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) pre_init_reg = rk805_pre_init_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) nr_pre_init_regs = ARRAY_SIZE(rk805_pre_init_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) cells = rk805s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) nr_cells = ARRAY_SIZE(rk805s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) on_source = RK805_ON_SOURCE_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) off_source = RK805_OFF_SOURCE_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) suspend_reg = rk805_suspend_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) suspend_reg_num = ARRAY_SIZE(rk805_suspend_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) resume_reg = rk805_resume_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) resume_reg_num = ARRAY_SIZE(rk805_resume_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) device_shutdown_fn = rk8xx_device_shutdown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) rk808->pm_pwroff_prep_fn = rk805_device_shutdown_prepare;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) case RK808_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) rk808->regmap_cfg = &rk808_regmap_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) rk808->regmap_irq_chip = &rk808_irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) pre_init_reg = rk808_pre_init_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) nr_pre_init_regs = ARRAY_SIZE(rk808_pre_init_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) cells = rk808s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) nr_cells = ARRAY_SIZE(rk808s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) device_shutdown_fn = rk8xx_device_shutdown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) case RK816_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) rk808->regmap_cfg = &rk816_regmap_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) rk808->regmap_irq_chip = &rk816_irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) battery_irq_chip = &rk816_battery_irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) pre_init_reg = rk816_pre_init_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) nr_pre_init_regs = ARRAY_SIZE(rk816_pre_init_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) cells = rk816s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) nr_cells = ARRAY_SIZE(rk816s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) on_source = RK816_ON_SOURCE_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) off_source = RK816_OFF_SOURCE_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) suspend_reg = rk816_suspend_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) suspend_reg_num = ARRAY_SIZE(rk816_suspend_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) resume_reg = rk816_resume_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) resume_reg_num = ARRAY_SIZE(rk816_resume_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) device_shutdown_fn = rk8xx_device_shutdown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) case RK818_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) rk808->regmap_cfg = &rk818_regmap_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) rk808->regmap_irq_chip = &rk818_irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) pre_init_reg = rk818_pre_init_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) nr_pre_init_regs = ARRAY_SIZE(rk818_pre_init_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) cells = rk818s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) nr_cells = ARRAY_SIZE(rk818s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) on_source = RK818_ON_SOURCE_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) off_source = RK818_OFF_SOURCE_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) suspend_reg = rk818_suspend_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) suspend_reg_num = ARRAY_SIZE(rk818_suspend_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) resume_reg = rk818_resume_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) resume_reg_num = ARRAY_SIZE(rk818_resume_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) device_shutdown_fn = rk8xx_device_shutdown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) case RK809_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) case RK817_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) rk808->regmap_cfg = &rk817_regmap_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) rk808->regmap_irq_chip = &rk817_irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) pre_init_reg = rk817_pre_init_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) nr_pre_init_regs = ARRAY_SIZE(rk817_pre_init_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) cells = rk817s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) nr_cells = ARRAY_SIZE(rk817s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) on_source = RK817_ON_SOURCE_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) off_source = RK817_OFF_SOURCE_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) rk808->pm_pwroff_prep_fn = rk817_shutdown_prepare;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) of_property_prepare_fn = rk817_of_property_prepare;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) pinctrl_init = rk817_pinctrl_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) dev_err(&client->dev, "Unsupported RK8XX ID %lu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) rk808->variant);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) rk808->i2c = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) rk808_i2c_client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) i2c_set_clientdata(client, rk808);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) rk808->regmap = devm_regmap_init_i2c(client, rk808->regmap_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) if (IS_ERR(rk808->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) dev_err(&client->dev, "regmap initialization failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) return PTR_ERR(rk808->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) if (on_source && off_source) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) ret = regmap_read(rk808->regmap, on_source, &on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) dev_err(&client->dev, "read 0x%x failed\n", on_source);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) ret = regmap_read(rk808->regmap, off_source, &off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) dev_err(&client->dev, "read 0x%x failed\n", off_source);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) dev_info(&client->dev, "source: on=0x%02x, off=0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) on, off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) if (!client->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) dev_err(&client->dev, "No interrupt support, no core IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) if (of_property_prepare_fn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) of_property_prepare_fn(rk808, &client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) for (i = 0; i < nr_pre_init_regs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) ret = regmap_update_bits(rk808->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) pre_init_reg[i].addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) pre_init_reg[i].mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) pre_init_reg[i].value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) "0x%x write err\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) pre_init_reg[i].addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) if (pinctrl_init) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) ret = pinctrl_init(&client->dev, rk808);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) ret = regmap_add_irq_chip(rk808->regmap, client->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) IRQF_ONESHOT | IRQF_SHARED, -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) rk808->regmap_irq_chip, &rk808->irq_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) dev_err(&client->dev, "Failed to add irq_chip %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) if (battery_irq_chip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) ret = regmap_add_irq_chip(rk808->regmap, client->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) IRQF_ONESHOT | IRQF_SHARED, -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) battery_irq_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) &rk808->battery_irq_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) "Failed to add batterry irq_chip %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) regmap_del_irq_chip(client->irq, rk808->irq_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) ret = devm_mfd_add_devices(&client->dev, PLATFORM_DEVID_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) cells, nr_cells, NULL, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) regmap_irq_get_domain(rk808->irq_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) dev_err(&client->dev, "failed to add MFD devices %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) goto err_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) pm_off = of_property_read_bool(np, "rockchip,system-power-controller");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) if (pm_off) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) if (!pm_power_off_prepare)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) pm_power_off_prepare = rk808->pm_pwroff_prep_fn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) if (device_shutdown_fn) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) register_syscore_ops(&rk808_syscore_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) /* power off system in the syscore shutdown ! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) pm_shutdown = device_shutdown_fn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) rk8xx_kobj = kobject_create_and_add("rk8xx", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) if (rk8xx_kobj) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) ret = sysfs_create_file(rk8xx_kobj, &rk8xx_attrs.attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) dev_err(&client->dev, "create rk8xx sysfs error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) if (!pm_power_off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) pm_power_off = rk808_pm_power_off_dummy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) err_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) regmap_del_irq_chip(client->irq, rk808->irq_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) if (battery_irq_chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) regmap_del_irq_chip(client->irq, rk808->battery_irq_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) static int rk808_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) struct rk808 *rk808 = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) regmap_del_irq_chip(client->irq, rk808->irq_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) mfd_remove_devices(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) * pm_power_off may points to a function from another module.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) * Check if the pointer is set by us and only then overwrite it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) if (pm_power_off == rk808_pm_power_off_dummy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) pm_power_off = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) * As above, check if the pointer is set by us before overwrite.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) if (rk808->pm_pwroff_prep_fn &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) pm_power_off_prepare == rk808->pm_pwroff_prep_fn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) pm_power_off_prepare = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) if (pm_shutdown)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) unregister_syscore_ops(&rk808_syscore_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) static int __maybe_unused rk8xx_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) struct rk808 *rk808 = i2c_get_clientdata(rk808_i2c_client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) int i, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) int value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) for (i = 0; i < suspend_reg_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) ret = regmap_update_bits(rk808->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) suspend_reg[i].addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) suspend_reg[i].mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) suspend_reg[i].value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) dev_err(dev, "0x%x write err\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) suspend_reg[i].addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) switch (rk808->variant) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) case RK805_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) ret = regmap_update_bits(rk808->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) RK805_GPIO_IO_POL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) SLP_SD_MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) SLEEP_FUN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) case RK809_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) case RK817_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) if (rk808->pins && rk808->pins->p && rk808->pins->sleep) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) ret = regmap_update_bits(rk808->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) RK817_SYS_CFG(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) RK817_SLPPIN_FUNC_MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) SLPPIN_NULL_FUN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) dev_err(dev, "suspend: config SLPPIN_NULL_FUN error!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) ret = regmap_update_bits(rk808->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) RK817_SYS_CFG(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) RK817_SLPPOL_MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) RK817_SLPPOL_H);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) dev_err(dev, "suspend: config RK817_SLPPOL_H error!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) /* pmic need the SCL clock to synchronize register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) regmap_read(rk808->regmap, RK817_SYS_STS, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) mdelay(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) ret = pinctrl_select_state(rk808->pins->p, rk808->pins->sleep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) dev_err(dev, "failed to act slp pinctrl state\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) static int __maybe_unused rk8xx_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) struct rk808 *rk808 = i2c_get_clientdata(rk808_i2c_client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) int i, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) int value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) for (i = 0; i < resume_reg_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) ret = regmap_update_bits(rk808->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) resume_reg[i].addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) resume_reg[i].mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) resume_reg[i].value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) dev_err(dev, "0x%x write err\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) resume_reg[i].addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) switch (rk808->variant) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) case RK809_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) case RK817_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) if (rk808->pins && rk808->pins->p && rk808->pins->reset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) ret = regmap_update_bits(rk808->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) RK817_SYS_CFG(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) RK817_SLPPIN_FUNC_MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) SLPPIN_NULL_FUN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) dev_err(dev, "resume: config SLPPIN_NULL_FUN error!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) ret = regmap_update_bits(rk808->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) RK817_SYS_CFG(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) RK817_SLPPOL_MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) RK817_SLPPOL_L);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) dev_err(dev, "resume: config RK817_SLPPOL_L error!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) /* pmic need the SCL clock to synchronize register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) regmap_read(rk808->regmap, RK817_SYS_STS, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) mdelay(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) ret = pinctrl_select_state(rk808->pins->p, rk808->pins->reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) dev_dbg(dev, "failed to act reset pinctrl state\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) SIMPLE_DEV_PM_OPS(rk8xx_pm_ops, rk8xx_suspend, rk8xx_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) static struct i2c_driver rk808_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) .name = "rk808",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) .of_match_table = rk808_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) .pm = &rk8xx_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) .probe = rk808_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) .remove = rk808_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) #ifdef CONFIG_ROCKCHIP_THUNDER_BOOT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) static int __init rk808_i2c_driver_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) return i2c_add_driver(&rk808_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) subsys_initcall(rk808_i2c_driver_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) static void __exit rk808_i2c_driver_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) i2c_del_driver(&rk808_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) module_exit(rk808_i2c_driver_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) module_i2c_driver(rk808_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) MODULE_AUTHOR("Chris Zhong <zyw@rock-chips.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) MODULE_AUTHOR("Zhang Qing <zhangqing@rock-chips.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) MODULE_AUTHOR("Wadim Egorov <w.egorov@phytec.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) MODULE_DESCRIPTION("RK808/RK818 PMIC driver");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags