^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2020 Rockchip Electronics Co. Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Algea Cao <algea.cao@rock-chips.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/mfd/rk630.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) static int rk630_macphy_enable(struct rk630 *rk630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* IOMUX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) val = 0xfffc5554;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) ret = regmap_write(rk630->grf, GRF_REG(0x8), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) dev_err(rk630->dev, "Could not write to GRF: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* IOMUX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) val = 0x00330021;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) ret = regmap_write(rk630->grf, GRF_REG(0x10), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) dev_err(rk630->dev, "Could not write to GRF: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) val = BIT(12 + 16) | BIT(12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) ret = regmap_write(rk630->cru, CRU_REG(0x50), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) dev_err(rk630->dev, "Could not write to CRU: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) udelay(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) val = BIT(12 + 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) ret = regmap_write(rk630->cru, CRU_REG(0x50), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) dev_err(rk630->dev, "Could not write to CRU: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) udelay(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* power up && led*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) val = BIT(1 + 16) | BIT(1) | BIT(2 + 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) ret = regmap_write(rk630->grf, GRF_REG(0x408), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) dev_err(rk630->dev, "Could not write to GRF: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) usleep_range(20000, 50000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* mdio_sel: mdio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) val = BIT(8 + 16) | BIT(8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) ret = regmap_write(rk630->grf, GRF_REG(0x400), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) dev_err(rk630->dev, "Could not write to GRF: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* mode sel: RMII && clock sel: 24M && BGS value: OTP && id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) val = (2 << 14) | (0 << 12) | (0x1 << 8) | (6 << 5) | 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) ret = regmap_write(rk630->grf, GRF_REG(0x404), val | 0xffff0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) dev_err(rk630->dev, "Could not write to GRF: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) usleep_range(100, 150);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static int rk630_macphy_disable(struct rk630 *rk630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* GRF_SOC_CON2_CFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) val = BIT(2) | BIT(16 + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) ret = regmap_write(rk630->grf, GRF_REG(0x408), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) dev_err(rk630->dev, "Could not write to GRF: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static const struct mfd_cell rk630_devs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .name = "rk630-tve",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .of_compatible = "rockchip,rk630-tve",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .name = "rk630-macphy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .of_compatible = "rockchip,rk630-macphy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static const struct regmap_range rk630_grf_readable_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) regmap_reg_range(PLUMAGE_GRF_GPIO0A_IOMUX, PLUMAGE_GRF_GPIO0A_IOMUX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) regmap_reg_range(PLUMAGE_GRF_GPIO0B_IOMUX, PLUMAGE_GRF_GPIO0B_IOMUX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) regmap_reg_range(PLUMAGE_GRF_GPIO0C_IOMUX, PLUMAGE_GRF_GPIO0C_IOMUX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) regmap_reg_range(PLUMAGE_GRF_GPIO0D_IOMUX, PLUMAGE_GRF_GPIO0D_IOMUX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) regmap_reg_range(PLUMAGE_GRF_GPIO1A_IOMUX, PLUMAGE_GRF_GPIO1A_IOMUX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) regmap_reg_range(PLUMAGE_GRF_GPIO1B_IOMUX, PLUMAGE_GRF_GPIO1B_IOMUX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) regmap_reg_range(PLUMAGE_GRF_GPIO0A_P, PLUMAGE_GRF_GPIO1B_P),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) regmap_reg_range(PLUMAGE_GRF_GPIO1B_SR, PLUMAGE_GRF_GPIO1B_SR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) regmap_reg_range(PLUMAGE_GRF_GPIO1B_E, PLUMAGE_GRF_GPIO1B_E),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) regmap_reg_range(PLUMAGE_GRF_SOC_CON0, PLUMAGE_GRF_SOC_CON4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) regmap_reg_range(PLUMAGE_GRF_SOC_STATUS, PLUMAGE_GRF_SOC_STATUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) regmap_reg_range(PLUMAGE_GRF_GPIO0_REN0, PLUMAGE_GRF_GPIO1_REN0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static const struct regmap_access_table rk630_grf_readable_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .yes_ranges = rk630_grf_readable_ranges,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .n_yes_ranges = ARRAY_SIZE(rk630_grf_readable_ranges),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) const struct regmap_config rk630_grf_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .name = "grf",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .max_register = GRF_MAX_REGISTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .reg_format_endian = REGMAP_ENDIAN_NATIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .val_format_endian = REGMAP_ENDIAN_NATIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .rd_table = &rk630_grf_readable_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) EXPORT_SYMBOL_GPL(rk630_grf_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static const struct regmap_range rk630_cru_readable_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) regmap_reg_range(CRU_SPLL_CON0, CRU_SPLL_CON2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) regmap_reg_range(CRU_MODE_CON, CRU_MODE_CON),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) regmap_reg_range(CRU_CLKSEL_CON0, CRU_CLKSEL_CON3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) regmap_reg_range(CRU_GATE_CON0, CRU_GATE_CON0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) regmap_reg_range(CRU_SOFTRST_CON0, CRU_SOFTRST_CON0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static const struct regmap_access_table rk630_cru_readable_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .yes_ranges = rk630_cru_readable_ranges,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .n_yes_ranges = ARRAY_SIZE(rk630_cru_readable_ranges),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) const struct regmap_config rk630_cru_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .name = "cru",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .max_register = CRU_MAX_REGISTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .reg_format_endian = REGMAP_ENDIAN_NATIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .val_format_endian = REGMAP_ENDIAN_NATIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .rd_table = &rk630_cru_readable_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) EXPORT_SYMBOL_GPL(rk630_cru_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) int rk630_core_probe(struct rk630 *rk630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) bool macphy_enabled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) rk630->reset_gpio = devm_gpiod_get(rk630->dev, "reset", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (IS_ERR(rk630->reset_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) ret = PTR_ERR(rk630->reset_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) dev_err(rk630->dev, "failed to request reset GPIO: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) gpiod_direction_output(rk630->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) usleep_range(2000, 4000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) gpiod_direction_output(rk630->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) usleep_range(50000, 60000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) gpiod_direction_output(rk630->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) ret = devm_mfd_add_devices(rk630->dev, PLATFORM_DEVID_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) rk630_devs, ARRAY_SIZE(rk630_devs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) NULL, 0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) dev_err(rk630->dev, "failed to add MFD children: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) for_each_child_of_node(rk630->dev->of_node, np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (!of_device_is_compatible(np, "rockchip,rk630-macphy"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if (!of_device_is_available(np)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) macphy_enabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if (macphy_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) rk630_macphy_enable(rk630);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) rk630_macphy_disable(rk630);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) EXPORT_SYMBOL_GPL(rk630_core_probe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) MODULE_AUTHOR("Algea Cao <Algea.cao@rock-chips.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) MODULE_DESCRIPTION("Rockchip rk630 MFD Core driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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