Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (c) 2020 Rockchip Electronics Co. Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Author: Algea Cao <algea.cao@rock-chips.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/input.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/mfd/rk630.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define RK630_CMD_WRITE			0x00000011
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define RK630_CMD_WRITE_REG0		0x00010011
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define RK630_CMD_WRITE_REG1		0x00020011
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define RK630_CMD_WRITE_CTRL0		0x00030011
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define RK630_CMD_READ			0x00000077
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define RK630_CMD_READ_BEGIN		0x000000AA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define RK630_CMD_QUERY			0x000000FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define RK630_CMD_QUERY_REG2		0x000001FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define RK630_CMD_QUICK_WRITE		0x00030011
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define RK630_OP_STATE_ID_MASK		(0xffff0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define RK630_OP_STATE_ID		(0X16080000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define RK630_OP_STATE_MASK		(0x0000ffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define RK630_OP_STATE_WRITE_ERROR	(0x01 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define RK630_OP_STATE_WRITE_OVERFLOW	(0x01 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define RK630_OP_STATE_WRITE_UNFINISHED	(0x01 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define RK630_OP_STATE_READ_ERROR	(0x01 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define RK630_OP_STATE_READ_UNDERFLOW	(0x01 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define RK630_OP_STATE_PRE_READ_ERROR	(0x01 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define RK630_MAX_OP_BYTES		(60000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) static int rk630_spi_ctrl_init(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	u32 write_cmd = RK630_CMD_WRITE_CTRL0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	u32 buf = 0x00000008;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	struct spi_transfer write_cmd_packet = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 		.tx_buf = &write_cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 		.len	= 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	struct spi_transfer data_packet = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 		.tx_buf = &buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 		.len	= 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	struct spi_message m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	spi_message_init(&m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	spi_message_add_tail(&write_cmd_packet, &m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	spi_message_add_tail(&data_packet, &m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	return spi_sync(spi, &m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) static int rk630_spi_write(struct spi_device *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 			   u32 addr, const u32 *data, size_t data_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	u32 write_cmd = RK630_CMD_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	struct spi_transfer write_cmd_packet = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 		.tx_buf = &write_cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 		.len    = sizeof(write_cmd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	struct spi_transfer addr_packet = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 		.tx_buf = &addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 		.len    = sizeof(addr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	struct spi_transfer data_packet = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 		.tx_buf = data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 		.len    = data_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	struct spi_message m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	spi_message_init(&m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	spi_message_add_tail(&write_cmd_packet, &m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	spi_message_add_tail(&addr_packet, &m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	spi_message_add_tail(&data_packet, &m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	ret = spi_sync(spi, &m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) static int rk630_regmap_write(void *context, const void *data, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	struct device *dev = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	struct spi_device *spi = to_spi_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	u32 buf[count];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	if (count < 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		dev_err(&spi->dev, "regmap write err!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	memcpy(buf, data, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	return rk630_spi_write(spi, buf[0], &buf[1], (count - 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static int rk630_spi_read(struct spi_device *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		   u32 addr, u32 *data, size_t data_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	u32 read_cmd = RK630_CMD_READ | (1 << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	u32 read_begin_cmd = RK630_CMD_READ_BEGIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	u32 dummy = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	struct spi_transfer read_cmd_packet = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		.tx_buf = &read_cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		.len    = sizeof(read_cmd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	struct spi_transfer addr_packet = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 		.tx_buf = &addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		.len    = sizeof(addr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	struct spi_transfer read_dummy_packet = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		.tx_buf = &dummy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		.len    = sizeof(dummy),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	struct spi_transfer read_begin_cmd_packet = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		.tx_buf = &read_begin_cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		.len    = sizeof(read_begin_cmd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	struct spi_transfer data_packet = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		.rx_buf = data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		.len    = data_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	struct spi_message m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	spi_message_init(&m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	spi_message_add_tail(&read_cmd_packet, &m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	spi_message_add_tail(&addr_packet, &m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	spi_message_add_tail(&read_dummy_packet, &m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	spi_message_add_tail(&read_begin_cmd_packet, &m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	spi_message_add_tail(&data_packet, &m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	ret = spi_sync(spi, &m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static int rk630_regmap_read(void *context,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 			     const void *reg, size_t reg_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 			     void *val, size_t val_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	struct device *dev = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	struct spi_device *spi = to_spi_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	u32 rx_buf[2] = { 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	if (reg_size != sizeof(u32) || val_size != sizeof(u32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	/* Copy address to read from into first element of SPI buffer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	memcpy(rx_buf, reg, sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	ret = rk630_spi_read(spi, rx_buf[0], &rx_buf[1], val_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		dev_err(&spi->dev, "rk630 spi read err\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	memcpy(val, &rx_buf[1], val_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static struct regmap_bus rk630_regmap = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	.write = rk630_regmap_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	.read = rk630_regmap_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	.reg_format_endian_default = REGMAP_ENDIAN_NATIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	.val_format_endian_default = REGMAP_ENDIAN_NATIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) rk630_spi_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	struct device *dev = &spi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	struct rk630 *rk630;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	spi->bits_per_word = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	ret = spi_setup(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	rk630 = devm_kzalloc(dev, sizeof(*rk630), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	if (!rk630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	rk630->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	spi_set_drvdata(spi, rk630);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	rk630->grf = devm_regmap_init(&spi->dev, &rk630_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 				      &spi->dev, &rk630_grf_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	if (IS_ERR(rk630->grf)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		ret = PTR_ERR(rk630->grf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		dev_err(dev, "failed to allocate grf register map: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	rk630->cru = devm_regmap_init(&spi->dev, &rk630_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 				      &spi->dev, &rk630_cru_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	if (IS_ERR(rk630->cru)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		ret = PTR_ERR(rk630->cru);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		dev_err(dev, "failed to allocate cru register map: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	rk630->tve = devm_regmap_init(&spi->dev, &rk630_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 				      &spi->dev, &rk630_tve_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	if (IS_ERR(rk630->tve)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		ret = PTR_ERR(rk630->tve);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		dev_err(rk630->dev, "Failed to initialize tve regmap: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 			ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	ret = rk630_core_probe(rk630);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	rk630_spi_ctrl_init(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static const struct of_device_id rk630_spi_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	{ .compatible = "rockchip,rk630", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	{}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) MODULE_DEVICE_TABLE(of, rk630_spi_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static const struct spi_device_id rk630_spi_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	{ "rk630", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	{}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) MODULE_DEVICE_TABLE(spi, rk630_spi_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static struct spi_driver rk630_spi_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		.name = "rk630",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		.of_match_table = of_match_ptr(rk630_spi_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	.probe = rk630_spi_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	.id_table = rk630_spi_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) module_spi_driver(rk630_spi_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) MODULE_AUTHOR("Algea Cao <Algea.cao@rock-chips.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) MODULE_DESCRIPTION("Rockchip rk630 MFD SPI driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) MODULE_LICENSE("GPL v2");