^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2020 Rockchip Electronics Co. Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Wyon Bi <bivvy.bi@rock-chips.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/mfd/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/mfd/rk628.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) RK628_IRQ_HDMITX_HPD_HIGH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) RK628_IRQ_HDMITX_HPD_LOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) RK628_IRQ_HDMITX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) RK628_IRQ_GVI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) RK628_IRQ_DSI1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) RK628_IRQ_DSI0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) RK628_IRQ_CSI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) RK628_IRQ_HDMIRX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) RK628_IRQ_GPIO0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) RK628_IRQ_GPIO1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) RK628_IRQ_GPIO2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) RK628_IRQ_GPIO3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) RK628_IRQ_EFUSE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static struct resource rk628_gpio_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) DEFINE_RES_IRQ(RK628_IRQ_GPIO0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) DEFINE_RES_IRQ(RK628_IRQ_GPIO1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) DEFINE_RES_IRQ(RK628_IRQ_GPIO2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) DEFINE_RES_IRQ(RK628_IRQ_GPIO3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static struct resource rk628_dsi0_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) DEFINE_RES_IRQ(RK628_IRQ_DSI0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static struct resource rk628_dsi1_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) DEFINE_RES_IRQ(RK628_IRQ_DSI1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static struct resource rk628_csi_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) DEFINE_RES_IRQ(RK628_IRQ_CSI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) DEFINE_RES_IRQ(RK628_IRQ_HDMIRX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static struct resource rk628_gvi_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) DEFINE_RES_IRQ(RK628_IRQ_GVI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static struct resource rk628_hdmi_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) DEFINE_RES_IRQ(RK628_IRQ_HDMITX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) DEFINE_RES_IRQ(RK628_IRQ_HDMITX_HPD_HIGH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) DEFINE_RES_IRQ(RK628_IRQ_HDMITX_HPD_LOW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static struct resource rk628_hdmirx_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) DEFINE_RES_IRQ(RK628_IRQ_HDMIRX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static struct resource rk628_efuse_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) DEFINE_RES_IRQ(RK628_IRQ_EFUSE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static const struct mfd_cell rk628_devs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .name = "rk628-cru",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .of_compatible = "rockchip,rk628-cru",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .name = "rk628-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .of_compatible = "rockchip,rk628-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) .resources = rk628_gpio_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .num_resources = ARRAY_SIZE(rk628_gpio_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .name = "rk628-combrxphy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .of_compatible = "rockchip,rk628-combrxphy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .name = "rk628-combtxphy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .of_compatible = "rockchip,rk628-combtxphy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .name = "rk628-csi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .of_compatible = "rockchip,rk628-csi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .resources = rk628_csi_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .num_resources = ARRAY_SIZE(rk628_csi_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .name = "rk628-hdmirx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .of_compatible = "rockchip,rk628-hdmirx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .resources = rk628_hdmirx_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .num_resources = ARRAY_SIZE(rk628_hdmirx_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .name = "rk628-dsi1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .of_compatible = "rockchip,rk628-dsi1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .resources = rk628_dsi1_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .num_resources = ARRAY_SIZE(rk628_dsi1_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .name = "rk628-dsi0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .of_compatible = "rockchip,rk628-dsi0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .resources = rk628_dsi0_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .num_resources = ARRAY_SIZE(rk628_dsi0_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .name = "rk628-rgb-tx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .of_compatible = "rockchip,rk628-rgb-tx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .name = "rk628-yuv-rx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .of_compatible = "rockchip,rk628-yuv-rx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .name = "rk628-yuv-tx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .of_compatible = "rockchip,rk628-yuv-tx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .name = "rk628-bt1120-rx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .of_compatible = "rockchip,rk628-bt1120-rx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .name = "rk628-bt1120-tx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .of_compatible = "rockchip,rk628-bt1120-tx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .name = "rk628-lvds",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .of_compatible = "rockchip,rk628-lvds",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .name = "rk628-gvi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .of_compatible = "rockchip,rk628-gvi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .resources = rk628_gvi_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .num_resources = ARRAY_SIZE(rk628_gvi_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .name = "rk628-hdmi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .of_compatible = "rockchip,rk628-hdmi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .resources = rk628_hdmi_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .num_resources = ARRAY_SIZE(rk628_hdmi_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .name = "rk628-efuse",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .of_compatible = "rockchip,rk628-efuse",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .resources = rk628_efuse_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .num_resources = ARRAY_SIZE(rk628_efuse_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .name = "rk628-post-process",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .of_compatible = "rockchip,rk628-post-process",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static const struct regmap_irq rk628_irqs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) REGMAP_IRQ_REG(RK628_IRQ_HDMITX_HPD_HIGH, 0, BIT(0)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) REGMAP_IRQ_REG(RK628_IRQ_HDMITX_HPD_LOW, 0, BIT(1)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) REGMAP_IRQ_REG(RK628_IRQ_HDMITX, 0, BIT(2)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) REGMAP_IRQ_REG(RK628_IRQ_GVI, 0, BIT(3)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) REGMAP_IRQ_REG(RK628_IRQ_DSI1, 0, BIT(4)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) REGMAP_IRQ_REG(RK628_IRQ_DSI0, 0, BIT(5)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) REGMAP_IRQ_REG(RK628_IRQ_CSI, 0, BIT(6)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) REGMAP_IRQ_REG(RK628_IRQ_HDMIRX, 0, BIT(8)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) REGMAP_IRQ_REG(RK628_IRQ_GPIO0, 4, BIT(0)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) REGMAP_IRQ_REG(RK628_IRQ_GPIO1, 4, BIT(1)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) REGMAP_IRQ_REG(RK628_IRQ_GPIO2, 4, BIT(2)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) REGMAP_IRQ_REG(RK628_IRQ_GPIO3, 4, BIT(3)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) REGMAP_IRQ_REG(RK628_IRQ_EFUSE, 4, BIT(4)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static struct rk628_irq_chip_data rk628_irq_chip_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .name = "rk628",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .irqs = rk628_irqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .num_irqs = ARRAY_SIZE(rk628_irqs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .num_regs = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .irq_reg_stride = (GRF_INTR1_STATUS - GRF_INTR0_STATUS) / 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .status_base = GRF_INTR0_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .mask_base = GRF_INTR0_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .ack_base = GRF_INTR0_CLR_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static const struct regmap_config rk628_grf_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .name = "grf",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .max_register = GRF_MAX_REGISTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .reg_format_endian = REGMAP_ENDIAN_LITTLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .val_format_endian = REGMAP_ENDIAN_LITTLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static inline const struct regmap_irq *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) irq_to_regmap_irq(struct rk628_irq_chip_data *d, int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) return &d->irqs[irq];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static void rk628_irq_lock(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct rk628_irq_chip_data *d = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) mutex_lock(&d->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static void rk628_irq_sync_unlock(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) struct rk628_irq_chip_data *d = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) u32 reg, mask, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) for (i = 0; i < d->num_regs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) reg = d->mask_base + (i * d->reg_stride * d->irq_reg_stride);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) mask = d->mask_buf_def[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) val = mask << 16 | (~d->mask_buf[i] & mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) regmap_write(d->map, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) mutex_unlock(&d->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static void rk628_irq_enable(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) struct rk628_irq_chip_data *d = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) d->mask_buf[irq_data->reg_offset / d->reg_stride] &= ~irq_data->mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static void rk628_irq_disable(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) struct rk628_irq_chip_data *d = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) d->mask_buf[irq_data->reg_offset / d->reg_stride] |= irq_data->mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static const struct irq_chip rk628_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .irq_bus_lock = rk628_irq_lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .irq_bus_sync_unlock = rk628_irq_sync_unlock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .irq_disable = rk628_irq_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .irq_enable = rk628_irq_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static irqreturn_t rk628_irq_thread(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) struct rk628_irq_chip_data *d = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) bool handled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) for (i = 0; i < d->num_regs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) reg = d->status_base + (i * d->reg_stride * d->irq_reg_stride);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) regmap_read(d->map, reg, &d->status_buf[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) for (i = 0; i < d->num_irqs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) if (d->status_buf[d->irqs[i].reg_offset / d->reg_stride] & d->irqs[i].mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) handle_nested_irq(irq_find_mapping(d->domain, i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) handled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) for (i = 0; i < d->num_regs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) if (d->status_buf[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) reg = d->ack_base + (i * d->reg_stride * d->irq_reg_stride);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) regmap_write(d->map, reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) d->status_buf[i] << 16 | d->status_buf[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) if (handled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static int rk628_irq_map(struct irq_domain *h, unsigned int virq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) irq_hw_number_t hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) struct rk628_irq_chip_data *d = h->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) irq_set_chip_data(virq, d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) irq_set_chip(virq, &d->irq_chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) irq_set_nested_thread(virq, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) irq_set_parent(virq, d->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) irq_set_noprobe(virq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static const struct irq_domain_ops rk628_irq_domain_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .map = rk628_irq_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .xlate = irq_domain_xlate_onetwocell,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static int rk628_irq_init(struct rk628 *rk628, int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) struct device *dev = rk628->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) struct rk628_irq_chip_data *d = rk628->irq_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) struct regmap *map = rk628->grf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) u32 reg, mask, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) if (d->num_regs <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) d->status_buf = devm_kcalloc(dev, d->num_regs, sizeof(unsigned int),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) if (!d->status_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) d->mask_buf = devm_kcalloc(dev, d->num_regs, sizeof(unsigned int),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) if (!d->mask_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) d->mask_buf_def = devm_kcalloc(dev, d->num_regs, sizeof(unsigned int),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (!d->mask_buf_def)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) d->irq_chip = rk628_irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) d->irq_chip.name = d->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) d->irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) d->map = map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) mutex_init(&d->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) for (i = 0; i < d->num_irqs; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) d->mask_buf_def[d->irqs[i].reg_offset / d->reg_stride] |= d->irqs[i].mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /* Mask all the interrupts by default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) for (i = 0; i < d->num_regs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) d->mask_buf[i] = d->mask_buf_def[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) reg = d->mask_base + (i * d->reg_stride * d->irq_reg_stride);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) mask = d->mask_buf[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) val = mask << 16 | (~d->mask_buf[i] & mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) regmap_write(d->map, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) d->domain = irq_domain_add_linear(dev->of_node, d->num_irqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) &rk628_irq_domain_ops, d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) if (!d->domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) dev_err(dev, "Failed to create IRQ domain\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) ret = devm_request_threaded_irq(dev, irq, NULL, rk628_irq_thread,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) IRQF_ONESHOT, d->name, d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) irq_domain_remove(d->domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) dev_err(dev, "Failed to request IRQ %d: %d\n", irq, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) static void rk628_irq_exit(struct rk628 *rk628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) struct rk628_irq_chip_data *d = rk628->irq_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) unsigned int virq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) int hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) /* Dispose all virtual irq from irq domain before removing it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) for (hwirq = 0; hwirq < d->num_irqs; hwirq++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) /* Ignore hwirq if holes in the IRQ list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) if (!d->irqs[hwirq].mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) * Find the virtual irq of hwirq on chip and if it is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) * there then dispose it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) virq = irq_find_mapping(d->domain, hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if (virq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) irq_dispose_mapping(virq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) irq_domain_remove(d->domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) rk628_i2c_probe(struct i2c_client *client, const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) struct rk628 *rk628;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) rk628 = devm_kzalloc(dev, sizeof(*rk628), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) if (!rk628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) rk628->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) rk628->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) rk628->irq_data = &rk628_irq_chip_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) i2c_set_clientdata(client, rk628);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) rk628->enable_gpio = devm_gpiod_get_optional(dev, "enable",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) if (IS_ERR(rk628->enable_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) ret = PTR_ERR(rk628->enable_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) dev_err(dev, "failed to request enable GPIO: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) rk628->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) if (IS_ERR(rk628->reset_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) ret = PTR_ERR(rk628->reset_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) dev_err(dev, "failed to request reset GPIO: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) gpiod_set_value(rk628->enable_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) usleep_range(10000, 11000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) gpiod_set_value(rk628->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) usleep_range(10000, 11000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) gpiod_set_value(rk628->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) usleep_range(10000, 11000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) gpiod_set_value(rk628->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) usleep_range(10000, 11000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) rk628->grf = devm_regmap_init_i2c(client, &rk628_grf_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) if (IS_ERR(rk628->grf)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) ret = PTR_ERR(rk628->grf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) dev_err(dev, "failed to allocate register map: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) /* selete int io function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) ret = regmap_write(rk628->grf, GRF_GPIO3AB_SEL_CON, 0x30002000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) dev_err(dev, "failed to access register: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) ret = rk628_irq_init(rk628, client->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) dev_err(dev, "failed to add IRQ chip: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) ret = mfd_add_devices(dev, PLATFORM_DEVID_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) rk628_devs, ARRAY_SIZE(rk628_devs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) NULL, 0, rk628->irq_data->domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) rk628_irq_exit(rk628);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) dev_err(dev, "Failed to add MFD children: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) static int rk628_i2c_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) struct rk628 *rk628 = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) mfd_remove_devices(rk628->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) rk628_irq_exit(rk628);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) static const struct of_device_id rk628_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) { .compatible = "rockchip,rk628", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) MODULE_DEVICE_TABLE(of, rk628_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) static const struct i2c_device_id rk628_i2c_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) { "rk628", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) MODULE_DEVICE_TABLE(i2c, rk628_i2c_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) static struct i2c_driver rk628_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) .name = "rk628",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) .of_match_table = of_match_ptr(rk628_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) .probe = rk628_i2c_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) .remove = rk628_i2c_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) .id_table = rk628_i2c_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) module_i2c_driver(rk628_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) MODULE_AUTHOR("Wyon Bi <bivvy.bi@rock-chips.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) MODULE_DESCRIPTION("Rockchip RK628 MFD driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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