^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Interrupt driver for RICOH583 power management chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Laxman dewangan <ldewangan@nvidia.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * based on code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (C) 2011 RICOH COMPANY,LTD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/mfd/rc5t583.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) enum int_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) SYS_INT = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) DCDC_INT = 0x2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) RTC_INT = 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) ADC_INT = 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) GPIO_INT = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) static int gpedge_add[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) RC5T583_GPIO_GPEDGE2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) RC5T583_GPIO_GPEDGE2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) static int irq_en_add[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) RC5T583_INT_EN_SYS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) RC5T583_INT_EN_SYS2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) RC5T583_INT_EN_DCDC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) RC5T583_INT_EN_RTC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) RC5T583_INT_EN_ADC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) RC5T583_INT_EN_ADC2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) RC5T583_INT_EN_ADC3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) RC5T583_GPIO_EN_INT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static int irq_mon_add[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) RC5T583_INT_MON_SYS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) RC5T583_INT_MON_SYS2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) RC5T583_INT_MON_DCDC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) RC5T583_INT_MON_RTC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) RC5T583_INT_IR_ADCL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) RC5T583_INT_IR_ADCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) RC5T583_INT_IR_ADCEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) RC5T583_INT_IR_GPIOF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) RC5T583_INT_IR_GPIOR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static int irq_clr_add[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) RC5T583_INT_IR_SYS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) RC5T583_INT_IR_SYS2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) RC5T583_INT_IR_DCDC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) RC5T583_INT_IR_RTC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) RC5T583_INT_IR_ADCL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) RC5T583_INT_IR_ADCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) RC5T583_INT_IR_ADCEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) RC5T583_INT_IR_GPIOF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) RC5T583_INT_IR_GPIOR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static int main_int_type[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) SYS_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) SYS_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) DCDC_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) RTC_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) ADC_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) ADC_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) ADC_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) GPIO_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) GPIO_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct rc5t583_irq_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u8 int_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) u8 master_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) u8 int_en_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) u8 mask_reg_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) int grp_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define RC5T583_IRQ(_int_type, _master_bit, _grp_index, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) _int_bit, _mask_ind) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .int_type = _int_type, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .master_bit = _master_bit, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .grp_index = _grp_index, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .int_en_bit = _int_bit, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .mask_reg_index = _mask_ind, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static const struct rc5t583_irq_data rc5t583_irqs[RC5T583_MAX_IRQS] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) [RC5T583_IRQ_ONKEY] = RC5T583_IRQ(SYS_INT, 0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) [RC5T583_IRQ_ACOK] = RC5T583_IRQ(SYS_INT, 0, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) [RC5T583_IRQ_LIDOPEN] = RC5T583_IRQ(SYS_INT, 0, 2, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) [RC5T583_IRQ_PREOT] = RC5T583_IRQ(SYS_INT, 0, 3, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) [RC5T583_IRQ_CLKSTP] = RC5T583_IRQ(SYS_INT, 0, 4, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) [RC5T583_IRQ_ONKEY_OFF] = RC5T583_IRQ(SYS_INT, 0, 5, 5, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) [RC5T583_IRQ_WD] = RC5T583_IRQ(SYS_INT, 0, 7, 7, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) [RC5T583_IRQ_EN_PWRREQ1] = RC5T583_IRQ(SYS_INT, 0, 8, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) [RC5T583_IRQ_EN_PWRREQ2] = RC5T583_IRQ(SYS_INT, 0, 9, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) [RC5T583_IRQ_PRE_VINDET] = RC5T583_IRQ(SYS_INT, 0, 10, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) [RC5T583_IRQ_DC0LIM] = RC5T583_IRQ(DCDC_INT, 1, 0, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) [RC5T583_IRQ_DC1LIM] = RC5T583_IRQ(DCDC_INT, 1, 1, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) [RC5T583_IRQ_DC2LIM] = RC5T583_IRQ(DCDC_INT, 1, 2, 2, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) [RC5T583_IRQ_DC3LIM] = RC5T583_IRQ(DCDC_INT, 1, 3, 3, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) [RC5T583_IRQ_CTC] = RC5T583_IRQ(RTC_INT, 2, 0, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) [RC5T583_IRQ_YALE] = RC5T583_IRQ(RTC_INT, 2, 5, 5, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) [RC5T583_IRQ_DALE] = RC5T583_IRQ(RTC_INT, 2, 6, 6, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) [RC5T583_IRQ_WALE] = RC5T583_IRQ(RTC_INT, 2, 7, 7, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) [RC5T583_IRQ_AIN1L] = RC5T583_IRQ(ADC_INT, 3, 0, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) [RC5T583_IRQ_AIN2L] = RC5T583_IRQ(ADC_INT, 3, 1, 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) [RC5T583_IRQ_AIN3L] = RC5T583_IRQ(ADC_INT, 3, 2, 2, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) [RC5T583_IRQ_VBATL] = RC5T583_IRQ(ADC_INT, 3, 3, 3, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) [RC5T583_IRQ_VIN3L] = RC5T583_IRQ(ADC_INT, 3, 4, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) [RC5T583_IRQ_VIN8L] = RC5T583_IRQ(ADC_INT, 3, 5, 5, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) [RC5T583_IRQ_AIN1H] = RC5T583_IRQ(ADC_INT, 3, 6, 0, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) [RC5T583_IRQ_AIN2H] = RC5T583_IRQ(ADC_INT, 3, 7, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) [RC5T583_IRQ_AIN3H] = RC5T583_IRQ(ADC_INT, 3, 8, 2, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) [RC5T583_IRQ_VBATH] = RC5T583_IRQ(ADC_INT, 3, 9, 3, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) [RC5T583_IRQ_VIN3H] = RC5T583_IRQ(ADC_INT, 3, 10, 4, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) [RC5T583_IRQ_VIN8H] = RC5T583_IRQ(ADC_INT, 3, 11, 5, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) [RC5T583_IRQ_ADCEND] = RC5T583_IRQ(ADC_INT, 3, 12, 0, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) [RC5T583_IRQ_GPIO0] = RC5T583_IRQ(GPIO_INT, 4, 0, 0, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) [RC5T583_IRQ_GPIO1] = RC5T583_IRQ(GPIO_INT, 4, 1, 1, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) [RC5T583_IRQ_GPIO2] = RC5T583_IRQ(GPIO_INT, 4, 2, 2, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) [RC5T583_IRQ_GPIO3] = RC5T583_IRQ(GPIO_INT, 4, 3, 3, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) [RC5T583_IRQ_GPIO4] = RC5T583_IRQ(GPIO_INT, 4, 4, 4, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) [RC5T583_IRQ_GPIO5] = RC5T583_IRQ(GPIO_INT, 4, 5, 5, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) [RC5T583_IRQ_GPIO6] = RC5T583_IRQ(GPIO_INT, 4, 6, 6, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) [RC5T583_IRQ_GPIO7] = RC5T583_IRQ(GPIO_INT, 4, 7, 7, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static void rc5t583_irq_lock(struct irq_data *irq_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct rc5t583 *rc5t583 = irq_data_get_irq_chip_data(irq_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) mutex_lock(&rc5t583->irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static void rc5t583_irq_unmask(struct irq_data *irq_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct rc5t583 *rc5t583 = irq_data_get_irq_chip_data(irq_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) unsigned int __irq = irq_data->irq - rc5t583->irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) const struct rc5t583_irq_data *data = &rc5t583_irqs[__irq];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) rc5t583->group_irq_en[data->grp_index] |= 1 << data->grp_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) rc5t583->intc_inten_reg |= 1 << data->master_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) rc5t583->irq_en_reg[data->mask_reg_index] |= 1 << data->int_en_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static void rc5t583_irq_mask(struct irq_data *irq_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct rc5t583 *rc5t583 = irq_data_get_irq_chip_data(irq_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) unsigned int __irq = irq_data->irq - rc5t583->irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) const struct rc5t583_irq_data *data = &rc5t583_irqs[__irq];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) rc5t583->group_irq_en[data->grp_index] &= ~(1 << data->grp_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) if (!rc5t583->group_irq_en[data->grp_index])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) rc5t583->intc_inten_reg &= ~(1 << data->master_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) rc5t583->irq_en_reg[data->mask_reg_index] &= ~(1 << data->int_en_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static int rc5t583_irq_set_type(struct irq_data *irq_data, unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) struct rc5t583 *rc5t583 = irq_data_get_irq_chip_data(irq_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) unsigned int __irq = irq_data->irq - rc5t583->irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) const struct rc5t583_irq_data *data = &rc5t583_irqs[__irq];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) int val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) int gpedge_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) int gpedge_bit_pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* Supporting only trigger level inetrrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) if ((data->int_type & GPIO_INT) && (type & IRQ_TYPE_EDGE_BOTH)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) gpedge_index = data->int_en_bit / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) gpedge_bit_pos = data->int_en_bit % 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (type & IRQ_TYPE_EDGE_FALLING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) val |= 0x2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) if (type & IRQ_TYPE_EDGE_RISING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) val |= 0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) rc5t583->gpedge_reg[gpedge_index] &= ~(3 << gpedge_bit_pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) rc5t583->gpedge_reg[gpedge_index] |= (val << gpedge_bit_pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) rc5t583_irq_unmask(irq_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static void rc5t583_irq_sync_unlock(struct irq_data *irq_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) struct rc5t583 *rc5t583 = irq_data_get_irq_chip_data(irq_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) for (i = 0; i < ARRAY_SIZE(rc5t583->gpedge_reg); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) ret = rc5t583_write(rc5t583->dev, gpedge_add[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) rc5t583->gpedge_reg[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) dev_warn(rc5t583->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) "Error in writing reg 0x%02x error: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) gpedge_add[i], ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) for (i = 0; i < ARRAY_SIZE(rc5t583->irq_en_reg); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) ret = rc5t583_write(rc5t583->dev, irq_en_add[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) rc5t583->irq_en_reg[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) dev_warn(rc5t583->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) "Error in writing reg 0x%02x error: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) irq_en_add[i], ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) ret = rc5t583_write(rc5t583->dev, RC5T583_INTC_INTEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) rc5t583->intc_inten_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) dev_warn(rc5t583->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) "Error in writing reg 0x%02x error: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) RC5T583_INTC_INTEN, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) mutex_unlock(&rc5t583->irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static int rc5t583_irq_set_wake(struct irq_data *irq_data, unsigned int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) struct rc5t583 *rc5t583 = irq_data_get_irq_chip_data(irq_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return irq_set_irq_wake(rc5t583->chip_irq, on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define rc5t583_irq_set_wake NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static irqreturn_t rc5t583_irq(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) struct rc5t583 *rc5t583 = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) uint8_t int_sts[RC5T583_MAX_INTERRUPT_MASK_REGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) uint8_t master_int = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) unsigned int rtc_int_sts = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /* Clear the status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) for (i = 0; i < RC5T583_MAX_INTERRUPT_MASK_REGS; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) int_sts[i] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) ret = rc5t583_read(rc5t583->dev, RC5T583_INTC_INTMON, &master_int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) dev_err(rc5t583->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) "Error in reading reg 0x%02x error: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) RC5T583_INTC_INTMON, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) for (i = 0; i < RC5T583_MAX_INTERRUPT_MASK_REGS; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) if (!(master_int & main_int_type[i]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) ret = rc5t583_read(rc5t583->dev, irq_mon_add[i], &int_sts[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) dev_warn(rc5t583->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) "Error in reading reg 0x%02x error: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) irq_mon_add[i], ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) int_sts[i] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (main_int_type[i] & RTC_INT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) rtc_int_sts = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) if (int_sts[i] & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) rtc_int_sts |= BIT(6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) if (int_sts[i] & 0x2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) rtc_int_sts |= BIT(7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) if (int_sts[i] & 0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) rtc_int_sts |= BIT(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) if (int_sts[i] & 0x8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) rtc_int_sts |= BIT(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) ret = rc5t583_write(rc5t583->dev, irq_clr_add[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) ~int_sts[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) dev_warn(rc5t583->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) "Error in reading reg 0x%02x error: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) irq_clr_add[i], ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (main_int_type[i] & RTC_INT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) int_sts[i] = rtc_int_sts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /* Merge gpio interrupts for rising and falling case*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) int_sts[7] |= int_sts[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /* Call interrupt handler if enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) for (i = 0; i < RC5T583_MAX_IRQS; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) const struct rc5t583_irq_data *data = &rc5t583_irqs[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) if ((int_sts[data->mask_reg_index] & (1 << data->int_en_bit)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) (rc5t583->group_irq_en[data->master_bit] &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) (1 << data->grp_index)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) handle_nested_irq(rc5t583->irq_base + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static struct irq_chip rc5t583_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .name = "rc5t583-irq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .irq_mask = rc5t583_irq_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) .irq_unmask = rc5t583_irq_unmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) .irq_bus_lock = rc5t583_irq_lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .irq_bus_sync_unlock = rc5t583_irq_sync_unlock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) .irq_set_type = rc5t583_irq_set_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .irq_set_wake = rc5t583_irq_set_wake,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) int rc5t583_irq_init(struct rc5t583 *rc5t583, int irq, int irq_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) if (!irq_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) dev_warn(rc5t583->dev, "No interrupt support on IRQ base\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) mutex_init(&rc5t583->irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) /* Initailize all int register to 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) for (i = 0; i < RC5T583_MAX_INTERRUPT_EN_REGS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) ret = rc5t583_write(rc5t583->dev, irq_en_add[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) rc5t583->irq_en_reg[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) dev_warn(rc5t583->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) "Error in writing reg 0x%02x error: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) irq_en_add[i], ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) for (i = 0; i < RC5T583_MAX_GPEDGE_REG; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) ret = rc5t583_write(rc5t583->dev, gpedge_add[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) rc5t583->gpedge_reg[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) dev_warn(rc5t583->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) "Error in writing reg 0x%02x error: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) gpedge_add[i], ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) ret = rc5t583_write(rc5t583->dev, RC5T583_INTC_INTEN, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) dev_warn(rc5t583->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) "Error in writing reg 0x%02x error: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) RC5T583_INTC_INTEN, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) /* Clear all interrupts in case they woke up active. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) for (i = 0; i < RC5T583_MAX_INTERRUPT_MASK_REGS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) ret = rc5t583_write(rc5t583->dev, irq_clr_add[i], 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) dev_warn(rc5t583->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) "Error in writing reg 0x%02x error: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) irq_clr_add[i], ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) rc5t583->irq_base = irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) rc5t583->chip_irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) for (i = 0; i < RC5T583_MAX_IRQS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) int __irq = i + rc5t583->irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) irq_set_chip_data(__irq, rc5t583);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) irq_set_chip_and_handler(__irq, &rc5t583_irq_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) handle_simple_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) irq_set_nested_thread(__irq, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) irq_clear_status_flags(__irq, IRQ_NOREQUEST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) ret = devm_request_threaded_irq(rc5t583->dev, irq, NULL, rc5t583_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) IRQF_ONESHOT, "rc5t583", rc5t583);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) dev_err(rc5t583->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) "Error in registering interrupt error: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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