^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #define pr_fmt(fmt) "%s: " fmt, __func__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/irqchip/chained_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/ssbi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/mfd/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SSBI_REG_ADDR_IRQ_BASE 0x1BB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SSBI_REG_ADDR_IRQ_ROOT (SSBI_REG_ADDR_IRQ_BASE + 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SSBI_REG_ADDR_IRQ_M_STATUS1 (SSBI_REG_ADDR_IRQ_BASE + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SSBI_REG_ADDR_IRQ_M_STATUS2 (SSBI_REG_ADDR_IRQ_BASE + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SSBI_REG_ADDR_IRQ_M_STATUS3 (SSBI_REG_ADDR_IRQ_BASE + 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SSBI_REG_ADDR_IRQ_M_STATUS4 (SSBI_REG_ADDR_IRQ_BASE + 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SSBI_REG_ADDR_IRQ_BLK_SEL (SSBI_REG_ADDR_IRQ_BASE + 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SSBI_REG_ADDR_IRQ_IT_STATUS (SSBI_REG_ADDR_IRQ_BASE + 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SSBI_REG_ADDR_IRQ_CONFIG (SSBI_REG_ADDR_IRQ_BASE + 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SSBI_REG_ADDR_IRQ_RT_STATUS (SSBI_REG_ADDR_IRQ_BASE + 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PM8821_SSBI_REG_ADDR_IRQ_BASE 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PM8821_SSBI_REG_ADDR_IRQ_MASTER0 (PM8821_SSBI_REG_ADDR_IRQ_BASE + 0x30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PM8821_SSBI_REG_ADDR_IRQ_MASTER1 (PM8821_SSBI_REG_ADDR_IRQ_BASE + 0xb0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define PM8821_SSBI_REG(m, b, offset) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) ((m == 0) ? \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) (PM8821_SSBI_REG_ADDR_IRQ_MASTER0 + b + offset) : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) (PM8821_SSBI_REG_ADDR_IRQ_MASTER1 + b + offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PM8821_SSBI_ADDR_IRQ_ROOT(m, b) PM8821_SSBI_REG(m, b, 0x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PM8821_SSBI_ADDR_IRQ_CLEAR(m, b) PM8821_SSBI_REG(m, b, 0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PM8821_SSBI_ADDR_IRQ_MASK(m, b) PM8821_SSBI_REG(m, b, 0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PM8821_SSBI_ADDR_IRQ_RT_STATUS(m, b) PM8821_SSBI_REG(m, b, 0x0f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define PM8821_BLOCKS_PER_MASTER 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define PM_IRQF_LVL_SEL 0x01 /* level select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PM_IRQF_MASK_FE 0x02 /* mask falling edge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define PM_IRQF_MASK_RE 0x04 /* mask rising edge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define PM_IRQF_CLR 0x08 /* clear interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define PM_IRQF_BITS_MASK 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define PM_IRQF_BITS_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define PM_IRQF_WRITE 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define PM_IRQF_MASK_ALL (PM_IRQF_MASK_FE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) PM_IRQF_MASK_RE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define REG_HWREV 0x002 /* PMIC4 revision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define REG_HWREV_2 0x0E8 /* PMIC4 revision 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define PM8XXX_NR_IRQS 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define PM8821_NR_IRQS 112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct pm_irq_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) int num_irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct irq_chip *irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) void (*irq_handler)(struct irq_desc *desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct pm_irq_chip {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) spinlock_t pm_irq_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct irq_domain *irqdomain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) unsigned int num_blocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) unsigned int num_masters;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) const struct pm_irq_data *pm_irq_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* MUST BE AT THE END OF THIS STRUCT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) u8 config[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static int pm8xxx_read_block_irq(struct pm_irq_chip *chip, unsigned int bp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) unsigned int *ip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) spin_lock(&chip->pm_irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) rc = regmap_write(chip->regmap, SSBI_REG_ADDR_IRQ_BLK_SEL, bp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) pr_err("Failed Selecting Block %d rc=%d\n", bp, rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) goto bail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) rc = regmap_read(chip->regmap, SSBI_REG_ADDR_IRQ_IT_STATUS, ip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) pr_err("Failed Reading Status rc=%d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) bail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) spin_unlock(&chip->pm_irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) pm8xxx_config_irq(struct pm_irq_chip *chip, unsigned int bp, unsigned int cp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) spin_lock(&chip->pm_irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) rc = regmap_write(chip->regmap, SSBI_REG_ADDR_IRQ_BLK_SEL, bp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) pr_err("Failed Selecting Block %d rc=%d\n", bp, rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) goto bail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) cp |= PM_IRQF_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) rc = regmap_write(chip->regmap, SSBI_REG_ADDR_IRQ_CONFIG, cp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) pr_err("Failed Configuring IRQ rc=%d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) bail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) spin_unlock(&chip->pm_irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static int pm8xxx_irq_block_handler(struct pm_irq_chip *chip, int block)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) int pmirq, irq, i, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) unsigned int bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) ret = pm8xxx_read_block_irq(chip, block, &bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) pr_err("Failed reading %d block ret=%d", block, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) if (!bits) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) pr_err("block bit set in master but no irqs: %d", block);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* Check IRQ bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) for (i = 0; i < 8; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) if (bits & (1 << i)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) pmirq = block * 8 + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) irq = irq_find_mapping(chip->irqdomain, pmirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) generic_handle_irq(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static int pm8xxx_irq_master_handler(struct pm_irq_chip *chip, int master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) unsigned int blockbits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) int block_number, i, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) ret = regmap_read(chip->regmap, SSBI_REG_ADDR_IRQ_M_STATUS1 + master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) &blockbits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) pr_err("Failed to read master %d ret=%d\n", master, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) if (!blockbits) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) pr_err("master bit set in root but no blocks: %d", master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) for (i = 0; i < 8; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) if (blockbits & (1 << i)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) block_number = master * 8 + i; /* block # */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) ret |= pm8xxx_irq_block_handler(chip, block_number);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static void pm8xxx_irq_handler(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) struct pm_irq_chip *chip = irq_desc_get_handler_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) struct irq_chip *irq_chip = irq_desc_get_chip(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) unsigned int root;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) int i, ret, masters = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) chained_irq_enter(irq_chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) ret = regmap_read(chip->regmap, SSBI_REG_ADDR_IRQ_ROOT, &root);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) pr_err("Can't read root status ret=%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /* on pm8xxx series masters start from bit 1 of the root */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) masters = root >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /* Read allowed masters for blocks. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) for (i = 0; i < chip->num_masters; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) if (masters & (1 << i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) pm8xxx_irq_master_handler(chip, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) chained_irq_exit(irq_chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static void pm8821_irq_block_handler(struct pm_irq_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) int master, int block)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) int pmirq, irq, i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) unsigned int bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) ret = regmap_read(chip->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) PM8821_SSBI_ADDR_IRQ_ROOT(master, block), &bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) pr_err("Reading block %d failed ret=%d", block, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /* Convert block offset to global block number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) block += (master * PM8821_BLOCKS_PER_MASTER) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /* Check IRQ bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) for (i = 0; i < 8; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (bits & BIT(i)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) pmirq = block * 8 + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) irq = irq_find_mapping(chip->irqdomain, pmirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) generic_handle_irq(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static inline void pm8821_irq_master_handler(struct pm_irq_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) int master, u8 master_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) int block;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) for (block = 1; block < 8; block++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (master_val & BIT(block))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) pm8821_irq_block_handler(chip, master, block);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static void pm8821_irq_handler(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) struct pm_irq_chip *chip = irq_desc_get_handler_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) struct irq_chip *irq_chip = irq_desc_get_chip(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) unsigned int master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) chained_irq_enter(irq_chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) ret = regmap_read(chip->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) PM8821_SSBI_REG_ADDR_IRQ_MASTER0, &master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) pr_err("Failed to read master 0 ret=%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /* bits 1 through 7 marks the first 7 blocks in master 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if (master & GENMASK(7, 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) pm8821_irq_master_handler(chip, 0, master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /* bit 0 marks if master 1 contains any bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) if (!(master & BIT(0)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) ret = regmap_read(chip->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) PM8821_SSBI_REG_ADDR_IRQ_MASTER1, &master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) pr_err("Failed to read master 1 ret=%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) pm8821_irq_master_handler(chip, 1, master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) chained_irq_exit(irq_chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static void pm8xxx_irq_mask_ack(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) unsigned int pmirq = irqd_to_hwirq(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) u8 block, config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) block = pmirq / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) config = chip->config[pmirq] | PM_IRQF_MASK_ALL | PM_IRQF_CLR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) pm8xxx_config_irq(chip, block, config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static void pm8xxx_irq_unmask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) unsigned int pmirq = irqd_to_hwirq(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) u8 block, config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) block = pmirq / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) config = chip->config[pmirq];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) pm8xxx_config_irq(chip, block, config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static int pm8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) unsigned int pmirq = irqd_to_hwirq(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) int irq_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) u8 block, config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) block = pmirq / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) irq_bit = pmirq % 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) chip->config[pmirq] = (irq_bit << PM_IRQF_BITS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) | PM_IRQF_MASK_ALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) if (flow_type & IRQF_TRIGGER_RISING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) chip->config[pmirq] &= ~PM_IRQF_MASK_RE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if (flow_type & IRQF_TRIGGER_FALLING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) chip->config[pmirq] &= ~PM_IRQF_MASK_FE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) chip->config[pmirq] |= PM_IRQF_LVL_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) if (flow_type & IRQF_TRIGGER_HIGH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) chip->config[pmirq] &= ~PM_IRQF_MASK_RE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) chip->config[pmirq] &= ~PM_IRQF_MASK_FE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) config = chip->config[pmirq] | PM_IRQF_CLR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) return pm8xxx_config_irq(chip, block, config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static int pm8xxx_irq_get_irqchip_state(struct irq_data *d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) enum irqchip_irq_state which,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) bool *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) unsigned int pmirq = irqd_to_hwirq(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) unsigned int bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) int irq_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) u8 block;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) if (which != IRQCHIP_STATE_LINE_LEVEL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) block = pmirq / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) irq_bit = pmirq % 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) spin_lock(&chip->pm_irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) rc = regmap_write(chip->regmap, SSBI_REG_ADDR_IRQ_BLK_SEL, block);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) pr_err("Failed Selecting Block %d rc=%d\n", block, rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) goto bail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) rc = regmap_read(chip->regmap, SSBI_REG_ADDR_IRQ_RT_STATUS, &bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) pr_err("Failed Reading Status rc=%d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) goto bail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) *state = !!(bits & BIT(irq_bit));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) bail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) spin_unlock(&chip->pm_irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) static struct irq_chip pm8xxx_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) .name = "pm8xxx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .irq_mask_ack = pm8xxx_irq_mask_ack,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) .irq_unmask = pm8xxx_irq_unmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) .irq_set_type = pm8xxx_irq_set_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .irq_get_irqchip_state = pm8xxx_irq_get_irqchip_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SKIP_SET_WAKE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) static void pm8xxx_irq_domain_map(struct pm_irq_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) struct irq_domain *domain, unsigned int irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) irq_hw_number_t hwirq, unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) irq_domain_set_info(domain, irq, hwirq, chip->pm_irq_data->irq_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) chip, handle_level_irq, NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) irq_set_noprobe(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) static int pm8xxx_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) unsigned int nr_irqs, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) struct pm_irq_chip *chip = domain->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) struct irq_fwspec *fwspec = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) irq_hw_number_t hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) unsigned int type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) ret = irq_domain_translate_twocell(domain, fwspec, &hwirq, &type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) for (i = 0; i < nr_irqs; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) pm8xxx_irq_domain_map(chip, domain, virq + i, hwirq + i, type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) static const struct irq_domain_ops pm8xxx_irq_domain_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) .alloc = pm8xxx_irq_domain_alloc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) .free = irq_domain_free_irqs_common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .translate = irq_domain_translate_twocell,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) static void pm8821_irq_mask_ack(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) unsigned int pmirq = irqd_to_hwirq(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) u8 block, master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) int irq_bit, rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) block = pmirq / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) master = block / PM8821_BLOCKS_PER_MASTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) irq_bit = pmirq % 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) block %= PM8821_BLOCKS_PER_MASTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) rc = regmap_update_bits(chip->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) PM8821_SSBI_ADDR_IRQ_MASK(master, block),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) BIT(irq_bit), BIT(irq_bit));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) pr_err("Failed to mask IRQ:%d rc=%d\n", pmirq, rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) rc = regmap_update_bits(chip->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) PM8821_SSBI_ADDR_IRQ_CLEAR(master, block),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) BIT(irq_bit), BIT(irq_bit));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) pr_err("Failed to CLEAR IRQ:%d rc=%d\n", pmirq, rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) static void pm8821_irq_unmask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) unsigned int pmirq = irqd_to_hwirq(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) int irq_bit, rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) u8 block, master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) block = pmirq / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) master = block / PM8821_BLOCKS_PER_MASTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) irq_bit = pmirq % 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) block %= PM8821_BLOCKS_PER_MASTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) rc = regmap_update_bits(chip->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) PM8821_SSBI_ADDR_IRQ_MASK(master, block),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) BIT(irq_bit), ~BIT(irq_bit));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) pr_err("Failed to read/write unmask IRQ:%d rc=%d\n", pmirq, rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) static int pm8821_irq_get_irqchip_state(struct irq_data *d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) enum irqchip_irq_state which,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) bool *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) int rc, pmirq = irqd_to_hwirq(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) u8 block, irq_bit, master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) unsigned int bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) block = pmirq / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) master = block / PM8821_BLOCKS_PER_MASTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) irq_bit = pmirq % 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) block %= PM8821_BLOCKS_PER_MASTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) rc = regmap_read(chip->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) PM8821_SSBI_ADDR_IRQ_RT_STATUS(master, block), &bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) pr_err("Reading Status of IRQ %d failed rc=%d\n", pmirq, rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) *state = !!(bits & BIT(irq_bit));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) static struct irq_chip pm8821_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) .name = "pm8821",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) .irq_mask_ack = pm8821_irq_mask_ack,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) .irq_unmask = pm8821_irq_unmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) .irq_get_irqchip_state = pm8821_irq_get_irqchip_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) .flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SKIP_SET_WAKE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) static const struct regmap_config ssbi_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) .reg_bits = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) .val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) .max_register = 0x3ff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) .fast_io = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) .reg_read = ssbi_reg_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) .reg_write = ssbi_reg_write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) static const struct pm_irq_data pm8xxx_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) .num_irqs = PM8XXX_NR_IRQS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) .irq_chip = &pm8xxx_irq_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) .irq_handler = pm8xxx_irq_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) static const struct pm_irq_data pm8821_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) .num_irqs = PM8821_NR_IRQS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) .irq_chip = &pm8821_irq_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) .irq_handler = pm8821_irq_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) static const struct of_device_id pm8xxx_id_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) { .compatible = "qcom,pm8018", .data = &pm8xxx_data},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) { .compatible = "qcom,pm8058", .data = &pm8xxx_data},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) { .compatible = "qcom,pm8821", .data = &pm8821_data},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) { .compatible = "qcom,pm8921", .data = &pm8xxx_data},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) MODULE_DEVICE_TABLE(of, pm8xxx_id_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) static int pm8xxx_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) const struct pm_irq_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) int irq, rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) u32 rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) struct pm_irq_chip *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) data = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) if (!data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) dev_err(&pdev->dev, "No matching driver data found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) regmap = devm_regmap_init(&pdev->dev, NULL, pdev->dev.parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) &ssbi_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) if (IS_ERR(regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) return PTR_ERR(regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) /* Read PMIC chip revision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) rc = regmap_read(regmap, REG_HWREV, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) pr_err("Failed to read hw rev reg %d:rc=%d\n", REG_HWREV, rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) pr_info("PMIC revision 1: %02X\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) rev = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) /* Read PMIC chip revision 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) rc = regmap_read(regmap, REG_HWREV_2, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) pr_err("Failed to read hw rev 2 reg %d:rc=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) REG_HWREV_2, rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) pr_info("PMIC revision 2: %02X\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) rev |= val << BITS_PER_BYTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) chip = devm_kzalloc(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) struct_size(chip, config, data->num_irqs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) if (!chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) platform_set_drvdata(pdev, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) chip->regmap = regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) chip->num_blocks = DIV_ROUND_UP(data->num_irqs, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) chip->num_masters = DIV_ROUND_UP(chip->num_blocks, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) chip->pm_irq_data = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) spin_lock_init(&chip->pm_irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) chip->irqdomain = irq_domain_add_linear(pdev->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) data->num_irqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) &pm8xxx_irq_domain_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) if (!chip->irqdomain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) irq_set_chained_handler_and_data(irq, data->irq_handler, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) irq_set_irq_wake(irq, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) rc = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) irq_set_chained_handler_and_data(irq, NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) irq_domain_remove(chip->irqdomain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) static int pm8xxx_remove_child(struct device *dev, void *unused)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) platform_device_unregister(to_platform_device(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) static int pm8xxx_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) int irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) struct pm_irq_chip *chip = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) device_for_each_child(&pdev->dev, NULL, pm8xxx_remove_child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) irq_set_chained_handler_and_data(irq, NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) irq_domain_remove(chip->irqdomain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) static struct platform_driver pm8xxx_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) .probe = pm8xxx_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) .remove = pm8xxx_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) .name = "pm8xxx-core",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) .of_match_table = pm8xxx_id_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) static int __init pm8xxx_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) return platform_driver_register(&pm8xxx_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) subsys_initcall(pm8xxx_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) static void __exit pm8xxx_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) platform_driver_unregister(&pm8xxx_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) module_exit(pm8xxx_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) MODULE_DESCRIPTION("PMIC 8xxx core driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) MODULE_VERSION("1.0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) MODULE_ALIAS("platform:pm8xxx-core");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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