Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /* NXP PCF50633 GPIO Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * (C) 2006-2008 by Openmoko, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Author: Balaji Rao <balajirrao@openmoko.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  * Broken down from monstrous PCF50633 driver mainly by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  * Harald Welte, Andy Green and Werner Almesberger
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/mfd/pcf50633/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/mfd/pcf50633/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/mfd/pcf50633/pmic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) static const u8 pcf50633_regulator_registers[PCF50633_NUM_REGULATORS] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	[PCF50633_REGULATOR_AUTO]	= PCF50633_REG_AUTOOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	[PCF50633_REGULATOR_DOWN1]	= PCF50633_REG_DOWN1OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	[PCF50633_REGULATOR_DOWN2]	= PCF50633_REG_DOWN2OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	[PCF50633_REGULATOR_MEMLDO]	= PCF50633_REG_MEMLDOOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	[PCF50633_REGULATOR_LDO1]	= PCF50633_REG_LDO1OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	[PCF50633_REGULATOR_LDO2]	= PCF50633_REG_LDO2OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	[PCF50633_REGULATOR_LDO3]	= PCF50633_REG_LDO3OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	[PCF50633_REGULATOR_LDO4]	= PCF50633_REG_LDO4OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	[PCF50633_REGULATOR_LDO5]	= PCF50633_REG_LDO5OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	[PCF50633_REGULATOR_LDO6]	= PCF50633_REG_LDO6OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	[PCF50633_REGULATOR_HCLDO]	= PCF50633_REG_HCLDOOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) int pcf50633_gpio_set(struct pcf50633 *pcf, int gpio, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	u8 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	reg = gpio - PCF50633_GPIO1 + PCF50633_REG_GPIO1CFG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	return pcf50633_reg_set_bit_mask(pcf, reg, 0x07, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) EXPORT_SYMBOL_GPL(pcf50633_gpio_set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) u8 pcf50633_gpio_get(struct pcf50633 *pcf, int gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	u8 reg, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	reg = gpio - PCF50633_GPIO1 + PCF50633_REG_GPIO1CFG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	val = pcf50633_reg_read(pcf, reg) & 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) EXPORT_SYMBOL_GPL(pcf50633_gpio_get);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) int pcf50633_gpio_invert_set(struct pcf50633 *pcf, int gpio, int invert)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	u8 val, reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 	reg = gpio - PCF50633_GPIO1 + PCF50633_REG_GPIO1CFG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 	val = !!invert << 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	return pcf50633_reg_set_bit_mask(pcf, reg, 1 << 3, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) EXPORT_SYMBOL_GPL(pcf50633_gpio_invert_set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) int pcf50633_gpio_invert_get(struct pcf50633 *pcf, int gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 	u8 reg, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 	reg = gpio - PCF50633_GPIO1 + PCF50633_REG_GPIO1CFG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 	val = pcf50633_reg_read(pcf, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 	return val & (1 << 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) EXPORT_SYMBOL_GPL(pcf50633_gpio_invert_get);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) int pcf50633_gpio_power_supply_set(struct pcf50633 *pcf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 					int gpio, int regulator, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) 	u8 reg, val, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) 	/* the *ENA register is always one after the *OUT register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) 	reg = pcf50633_regulator_registers[regulator] + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) 	val = !!on << (gpio - PCF50633_GPIO1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) 	mask = 1 << (gpio - PCF50633_GPIO1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) 	return pcf50633_reg_set_bit_mask(pcf, reg, mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) EXPORT_SYMBOL_GPL(pcf50633_gpio_power_supply_set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) MODULE_LICENSE("GPL");