^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * omap-usb-tll.c - The USB TLL driver for OMAP EHCI & OHCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2012-2013 Texas Instruments Incorporated - https://www.ti.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Keshava Munegowda <keshava_mgowda@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Roger Quadros <rogerq@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/platform_data/usb-omap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "omap-usb.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define USBTLL_DRIVER_NAME "usbhs_tll"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* TLL Register Set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define OMAP_USBTLL_REVISION (0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define OMAP_USBTLL_SYSCONFIG (0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define OMAP_USBTLL_SYSCONFIG_CACTIVITY (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define OMAP_USBTLL_SYSCONFIG_SIDLEMODE (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define OMAP_USBTLL_SYSCONFIG_ENAWAKEUP (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define OMAP_USBTLL_SYSCONFIG_SOFTRESET (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define OMAP_USBTLL_SYSCONFIG_AUTOIDLE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define OMAP_USBTLL_SYSSTATUS (0x14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define OMAP_USBTLL_SYSSTATUS_RESETDONE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define OMAP_USBTLL_IRQSTATUS (0x18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define OMAP_USBTLL_IRQENABLE (0x1C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define OMAP_TLL_SHARED_CONF (0x30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define OMAP_TLL_SHARED_CONF_USB_90D_DDR_EN (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define OMAP_TLL_SHARED_CONF_USB_180D_SDR_EN (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define OMAP_TLL_SHARED_CONF_USB_DIVRATION (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define OMAP_TLL_SHARED_CONF_FCLK_REQ (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define OMAP_TLL_SHARED_CONF_FCLK_IS_ON (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define OMAP_TLL_CHANNEL_CONF(num) (0x040 + 0x004 * num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define OMAP_TLL_CHANNEL_CONF_FSLSMODE_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define OMAP_TLL_CHANNEL_CONF_DRVVBUS (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define OMAP_TLL_CHANNEL_CONF_CHRGVBUS (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define OMAP_TLL_CHANNEL_CONF_ULPI_ULPIAUTOIDLE (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define OMAP_TLL_CHANNEL_CONF_UTMIAUTOIDLE (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define OMAP_TLL_CHANNEL_CONF_ULPIDDRMODE (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define OMAP_TLL_CHANNEL_CONF_MODE_TRANSPARENT_UTMI (2 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define OMAP_TLL_CHANNEL_CONF_CHANMODE_FSLS (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define OMAP_TLL_CHANNEL_CONF_CHANEN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define OMAP_TLL_FSLSMODE_6PIN_PHY_DAT_SE0 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define OMAP_TLL_FSLSMODE_6PIN_PHY_DP_DM 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define OMAP_TLL_FSLSMODE_3PIN_PHY 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define OMAP_TLL_FSLSMODE_4PIN_PHY 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define OMAP_TLL_FSLSMODE_6PIN_TLL_DAT_SE0 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define OMAP_TLL_FSLSMODE_6PIN_TLL_DP_DM 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define OMAP_TLL_FSLSMODE_3PIN_TLL 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define OMAP_TLL_FSLSMODE_4PIN_TLL 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define OMAP_TLL_FSLSMODE_2PIN_TLL_DAT_SE0 0xA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define OMAP_TLL_FSLSMODE_2PIN_DAT_DP_DM 0xB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define OMAP_TLL_ULPI_FUNCTION_CTRL(num) (0x804 + 0x100 * num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define OMAP_TLL_ULPI_INTERFACE_CTRL(num) (0x807 + 0x100 * num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define OMAP_TLL_ULPI_OTG_CTRL(num) (0x80A + 0x100 * num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define OMAP_TLL_ULPI_INT_EN_RISE(num) (0x80D + 0x100 * num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define OMAP_TLL_ULPI_INT_EN_FALL(num) (0x810 + 0x100 * num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define OMAP_TLL_ULPI_INT_STATUS(num) (0x813 + 0x100 * num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define OMAP_TLL_ULPI_INT_LATCH(num) (0x814 + 0x100 * num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define OMAP_TLL_ULPI_DEBUG(num) (0x815 + 0x100 * num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define OMAP_TLL_ULPI_SCRATCH_REGISTER(num) (0x816 + 0x100 * num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define OMAP_REV2_TLL_CHANNEL_COUNT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define OMAP_TLL_CHANNEL_COUNT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define OMAP_TLL_CHANNEL_1_EN_MASK (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define OMAP_TLL_CHANNEL_2_EN_MASK (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define OMAP_TLL_CHANNEL_3_EN_MASK (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* Values of USBTLL_REVISION - Note: these are not given in the TRM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define OMAP_USBTLL_REV1 0x00000015 /* OMAP3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define OMAP_USBTLL_REV2 0x00000018 /* OMAP 3630 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define OMAP_USBTLL_REV3 0x00000004 /* OMAP4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define OMAP_USBTLL_REV4 0x00000006 /* OMAP5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define is_ehci_tll_mode(x) (x == OMAP_EHCI_PORT_MODE_TLL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* only PHY and UNUSED modes don't need TLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define omap_usb_mode_needs_tll(x) ((x) != OMAP_USBHS_PORT_MODE_UNUSED &&\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) (x) != OMAP_EHCI_PORT_MODE_PHY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct usbtll_omap {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) int nch; /* num. of channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct clk *ch_clk[]; /* must be the last member */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static const char usbtll_driver_name[] = USBTLL_DRIVER_NAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static struct device *tll_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static DEFINE_SPINLOCK(tll_lock); /* serialize access to tll_dev */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static inline void usbtll_write(void __iomem *base, u32 reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) writel_relaxed(val, base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static inline u32 usbtll_read(void __iomem *base, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) return readl_relaxed(base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static inline void usbtll_writeb(void __iomem *base, u32 reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) writeb_relaxed(val, base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static inline u8 usbtll_readb(void __iomem *base, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) return readb_relaxed(base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static bool is_ohci_port(enum usbhs_omap_port_mode pmode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) switch (pmode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * convert the port-mode enum to a value we can use in the FSLSMODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * field of USBTLL_CHANNEL_CONF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static unsigned ohci_omap3_fslsmode(enum usbhs_omap_port_mode mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) case OMAP_USBHS_PORT_MODE_UNUSED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) return OMAP_TLL_FSLSMODE_6PIN_PHY_DAT_SE0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) return OMAP_TLL_FSLSMODE_6PIN_PHY_DP_DM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) return OMAP_TLL_FSLSMODE_3PIN_PHY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) return OMAP_TLL_FSLSMODE_4PIN_PHY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return OMAP_TLL_FSLSMODE_6PIN_TLL_DAT_SE0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) return OMAP_TLL_FSLSMODE_6PIN_TLL_DP_DM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) return OMAP_TLL_FSLSMODE_3PIN_TLL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) return OMAP_TLL_FSLSMODE_4PIN_TLL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) return OMAP_TLL_FSLSMODE_2PIN_TLL_DAT_SE0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) return OMAP_TLL_FSLSMODE_2PIN_DAT_DP_DM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) pr_warn("Invalid port mode, using default\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) return OMAP_TLL_FSLSMODE_6PIN_PHY_DAT_SE0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * usbtll_omap_probe - initialize TI-based HCDs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * Allocates basic resources for this USB host controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * @pdev: Pointer to this device's platform device structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static int usbtll_omap_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) struct usbtll_omap *tll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) int i, nch, ver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) dev_dbg(dev, "starting TI HSUSB TLL Controller\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) base = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (IS_ERR(base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) return PTR_ERR(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) pm_runtime_get_sync(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) ver = usbtll_read(base, OMAP_USBTLL_REVISION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) switch (ver) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) case OMAP_USBTLL_REV1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) case OMAP_USBTLL_REV4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) nch = OMAP_TLL_CHANNEL_COUNT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) case OMAP_USBTLL_REV2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) case OMAP_USBTLL_REV3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) nch = OMAP_REV2_TLL_CHANNEL_COUNT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) nch = OMAP_TLL_CHANNEL_COUNT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) dev_dbg(dev, "rev 0x%x not recognized, assuming %d channels\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) ver, nch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) tll = devm_kzalloc(dev, sizeof(*tll) + sizeof(tll->ch_clk[nch]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) if (!tll) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) pm_runtime_put_sync(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) pm_runtime_disable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) tll->base = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) tll->nch = nch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) platform_set_drvdata(pdev, tll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) for (i = 0; i < nch; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) char clkname[] = "usb_tll_hs_usb_chx_clk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) snprintf(clkname, sizeof(clkname),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) "usb_tll_hs_usb_ch%d_clk", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) tll->ch_clk[i] = clk_get(dev, clkname);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) if (IS_ERR(tll->ch_clk[i]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) dev_dbg(dev, "can't get clock : %s\n", clkname);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) clk_prepare(tll->ch_clk[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) pm_runtime_put_sync(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /* only after this can omap_tll_enable/disable work */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) spin_lock(&tll_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) tll_dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) spin_unlock(&tll_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) * usbtll_omap_remove - shutdown processing for UHH & TLL HCDs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) * @pdev: USB Host Controller being removed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) * Reverses the effect of usbtll_omap_probe().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static int usbtll_omap_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) struct usbtll_omap *tll = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) spin_lock(&tll_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) tll_dev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) spin_unlock(&tll_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) for (i = 0; i < tll->nch; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) if (!IS_ERR(tll->ch_clk[i])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) clk_unprepare(tll->ch_clk[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) clk_put(tll->ch_clk[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static const struct of_device_id usbtll_omap_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) { .compatible = "ti,usbhs-tll" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) MODULE_DEVICE_TABLE(of, usbtll_omap_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static struct platform_driver usbtll_omap_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .name = usbtll_driver_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .of_match_table = usbtll_omap_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) .probe = usbtll_omap_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .remove = usbtll_omap_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) int omap_tll_init(struct usbhs_omap_platform_data *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) bool needs_tll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) unsigned reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) struct usbtll_omap *tll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) if (!tll_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) pm_runtime_get_sync(tll_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) spin_lock(&tll_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) tll = dev_get_drvdata(tll_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) needs_tll = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) for (i = 0; i < tll->nch; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) needs_tll |= omap_usb_mode_needs_tll(pdata->port_mode[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) if (needs_tll) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) void __iomem *base = tll->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /* Program Common TLL register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) reg = usbtll_read(base, OMAP_TLL_SHARED_CONF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) reg |= (OMAP_TLL_SHARED_CONF_FCLK_IS_ON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) | OMAP_TLL_SHARED_CONF_USB_DIVRATION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) reg &= ~OMAP_TLL_SHARED_CONF_USB_90D_DDR_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) reg &= ~OMAP_TLL_SHARED_CONF_USB_180D_SDR_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) usbtll_write(base, OMAP_TLL_SHARED_CONF, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /* Enable channels now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) for (i = 0; i < tll->nch; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) reg = usbtll_read(base, OMAP_TLL_CHANNEL_CONF(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) if (is_ohci_port(pdata->port_mode[i])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) reg |= ohci_omap3_fslsmode(pdata->port_mode[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) << OMAP_TLL_CHANNEL_CONF_FSLSMODE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) reg |= OMAP_TLL_CHANNEL_CONF_CHANMODE_FSLS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) } else if (pdata->port_mode[i] ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) OMAP_EHCI_PORT_MODE_TLL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) * Disable UTMI AutoIdle, BitStuffing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) * and use SDR Mode. Enable ULPI AutoIdle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) reg &= ~(OMAP_TLL_CHANNEL_CONF_UTMIAUTOIDLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) | OMAP_TLL_CHANNEL_CONF_ULPIDDRMODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) reg |= OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) reg |= OMAP_TLL_CHANNEL_CONF_ULPI_ULPIAUTOIDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) } else if (pdata->port_mode[i] ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) OMAP_EHCI_PORT_MODE_HSIC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) * HSIC Mode requires UTMI port configurations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) reg |= OMAP_TLL_CHANNEL_CONF_DRVVBUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) | OMAP_TLL_CHANNEL_CONF_CHRGVBUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) | OMAP_TLL_CHANNEL_CONF_MODE_TRANSPARENT_UTMI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) | OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) reg |= OMAP_TLL_CHANNEL_CONF_CHANEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) usbtll_write(base, OMAP_TLL_CHANNEL_CONF(i), reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) usbtll_writeb(base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) OMAP_TLL_ULPI_SCRATCH_REGISTER(i),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 0xbe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) spin_unlock(&tll_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) pm_runtime_put_sync(tll_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) EXPORT_SYMBOL_GPL(omap_tll_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) int omap_tll_enable(struct usbhs_omap_platform_data *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) struct usbtll_omap *tll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) if (!tll_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) pm_runtime_get_sync(tll_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) spin_lock(&tll_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) tll = dev_get_drvdata(tll_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) for (i = 0; i < tll->nch; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) if (omap_usb_mode_needs_tll(pdata->port_mode[i])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) if (IS_ERR(tll->ch_clk[i]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) r = clk_enable(tll->ch_clk[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) dev_err(tll_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) "Error enabling ch %d clock: %d\n", i, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) spin_unlock(&tll_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) EXPORT_SYMBOL_GPL(omap_tll_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) int omap_tll_disable(struct usbhs_omap_platform_data *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) struct usbtll_omap *tll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) if (!tll_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) spin_lock(&tll_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) tll = dev_get_drvdata(tll_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) for (i = 0; i < tll->nch; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) if (omap_usb_mode_needs_tll(pdata->port_mode[i])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) if (!IS_ERR(tll->ch_clk[i]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) clk_disable(tll->ch_clk[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) spin_unlock(&tll_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) pm_runtime_put_sync(tll_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) EXPORT_SYMBOL_GPL(omap_tll_disable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) MODULE_AUTHOR("Keshava Munegowda <keshava_mgowda@ti.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) MODULE_AUTHOR("Roger Quadros <rogerq@ti.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) MODULE_DESCRIPTION("usb tll driver for TI OMAP EHCI and OHCI controllers");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) static int __init omap_usbtll_drvinit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) return platform_driver_register(&usbtll_omap_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) * init before usbhs core driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) * The usbtll driver should be initialized before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) * the usbhs core driver probe function is called.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) fs_initcall(omap_usbtll_drvinit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) static void __exit omap_usbtll_drvexit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) platform_driver_unregister(&usbtll_omap_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) module_exit(omap_usbtll_drvexit);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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