^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * omap-usb-host.c - The USBHS core driver for OMAP EHCI & OHCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2011-2013 Texas Instruments Incorporated - https://www.ti.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Keshava Munegowda <keshava_mgowda@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Roger Quadros <rogerq@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/platform_data/usb-omap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "omap-usb.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define USBHS_DRIVER_NAME "usbhs_omap"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define OMAP_EHCI_DEVICE "ehci-omap"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define OMAP_OHCI_DEVICE "ohci-omap3"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* OMAP USBHOST Register addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* UHH Register Set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define OMAP_UHH_REVISION (0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define OMAP_UHH_SYSCONFIG (0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define OMAP_UHH_SYSCONFIG_MIDLEMODE (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define OMAP_UHH_SYSCONFIG_CACTIVITY (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define OMAP_UHH_SYSCONFIG_SIDLEMODE (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define OMAP_UHH_SYSCONFIG_ENAWAKEUP (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define OMAP_UHH_SYSCONFIG_SOFTRESET (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define OMAP_UHH_SYSCONFIG_AUTOIDLE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define OMAP_UHH_SYSSTATUS (0x14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define OMAP_UHH_HOSTCONFIG (0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define OMAP_UHH_HOSTCONFIG_ULPI_BYPASS (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define OMAP_UHH_HOSTCONFIG_P2_CONNECT_STATUS (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define OMAP_UHH_HOSTCONFIG_P3_CONNECT_STATUS (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define OMAP4_UHH_HOSTCONFIG_APP_START_CLK (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* OMAP4-specific defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define OMAP4_UHH_SYSCONFIG_IDLEMODE_CLEAR (3 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define OMAP4_UHH_SYSCONFIG_NOIDLE (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define OMAP4_UHH_SYSCONFIG_STDBYMODE_CLEAR (3 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define OMAP4_UHH_SYSCONFIG_NOSTDBY (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define OMAP4_UHH_SYSCONFIG_SOFTRESET (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define OMAP4_P1_MODE_CLEAR (3 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define OMAP4_P1_MODE_TLL (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define OMAP4_P1_MODE_HSIC (3 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define OMAP4_P2_MODE_CLEAR (3 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define OMAP4_P2_MODE_TLL (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define OMAP4_P2_MODE_HSIC (3 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define OMAP_UHH_DEBUG_CSR (0x44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* Values of UHH_REVISION - Note: these are not given in the TRM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define OMAP_USBHS_REV1 0x00000010 /* OMAP3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define OMAP_USBHS_REV2 0x50700100 /* OMAP4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define is_omap_usbhs_rev1(x) (x->usbhs_rev == OMAP_USBHS_REV1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define is_omap_usbhs_rev2(x) (x->usbhs_rev == OMAP_USBHS_REV2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define is_ehci_phy_mode(x) (x == OMAP_EHCI_PORT_MODE_PHY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define is_ehci_tll_mode(x) (x == OMAP_EHCI_PORT_MODE_TLL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define is_ehci_hsic_mode(x) (x == OMAP_EHCI_PORT_MODE_HSIC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct usbhs_hcd_omap {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) int nports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct clk **utmi_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct clk **hsic60m_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct clk **hsic480m_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct clk *xclk60mhsp1_ck;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct clk *xclk60mhsp2_ck;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct clk *utmi_p1_gfclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct clk *utmi_p2_gfclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct clk *init_60m_fclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct clk *ehci_logic_fck;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) void __iomem *uhh_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct usbhs_omap_platform_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) u32 usbhs_rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static const char usbhs_driver_name[] = USBHS_DRIVER_NAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static u64 usbhs_dmamask = DMA_BIT_MASK(32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static inline void usbhs_write(void __iomem *base, u32 reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) writel_relaxed(val, base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static inline u32 usbhs_read(void __iomem *base, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) return readl_relaxed(base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * Map 'enum usbhs_omap_port_mode' found in <linux/platform_data/usb-omap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * to the device tree binding portN-mode found in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * 'Documentation/devicetree/bindings/mfd/omap-usb-host.txt'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static const char * const port_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) [OMAP_USBHS_PORT_MODE_UNUSED] = "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) [OMAP_EHCI_PORT_MODE_PHY] = "ehci-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) [OMAP_EHCI_PORT_MODE_TLL] = "ehci-tll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) [OMAP_EHCI_PORT_MODE_HSIC] = "ehci-hsic",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) [OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0] = "ohci-phy-6pin-datse0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) [OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM] = "ohci-phy-6pin-dpdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) [OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0] = "ohci-phy-3pin-datse0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) [OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM] = "ohci-phy-4pin-dpdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) [OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0] = "ohci-tll-6pin-datse0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) [OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM] = "ohci-tll-6pin-dpdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) [OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0] = "ohci-tll-3pin-datse0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) [OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM] = "ohci-tll-4pin-dpdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) [OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0] = "ohci-tll-2pin-datse0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) [OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM] = "ohci-tll-2pin-dpdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static struct platform_device *omap_usbhs_alloc_child(const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct resource *res, int num_resources, void *pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) size_t pdata_size, struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct platform_device *child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) child = platform_device_alloc(name, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) if (!child) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) dev_err(dev, "platform_device_alloc %s failed\n", name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) goto err_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) ret = platform_device_add_resources(child, res, num_resources);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) dev_err(dev, "platform_device_add_resources failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) goto err_alloc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) ret = platform_device_add_data(child, pdata, pdata_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) dev_err(dev, "platform_device_add_data failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) goto err_alloc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) child->dev.dma_mask = &usbhs_dmamask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) dma_set_coherent_mask(&child->dev, DMA_BIT_MASK(32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) child->dev.parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) ret = platform_device_add(child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) dev_err(dev, "platform_device_add failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) goto err_alloc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) err_alloc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) platform_device_put(child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) err_end:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static int omap_usbhs_alloc_children(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct usbhs_omap_platform_data *pdata = dev_get_platdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) struct platform_device *ehci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) struct platform_device *ohci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) struct resource resources[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ehci");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) if (!res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) dev_err(dev, "EHCI get resource IORESOURCE_MEM failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) goto err_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) resources[0] = *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "ehci-irq");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) if (!res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) dev_err(dev, " EHCI get resource IORESOURCE_IRQ failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) goto err_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) resources[1] = *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) ehci = omap_usbhs_alloc_child(OMAP_EHCI_DEVICE, resources, 2, pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) sizeof(*pdata), dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (!ehci) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) dev_err(dev, "omap_usbhs_alloc_child failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) goto err_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ohci");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) if (!res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) dev_err(dev, "OHCI get resource IORESOURCE_MEM failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) goto err_ehci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) resources[0] = *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "ohci-irq");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) if (!res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) dev_err(dev, "OHCI get resource IORESOURCE_IRQ failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) goto err_ehci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) resources[1] = *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) ohci = omap_usbhs_alloc_child(OMAP_OHCI_DEVICE, resources, 2, pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) sizeof(*pdata), dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) if (!ohci) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) dev_err(dev, "omap_usbhs_alloc_child failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) goto err_ehci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) err_ehci:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) platform_device_unregister(ehci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) err_end:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static bool is_ohci_port(enum usbhs_omap_port_mode pmode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) switch (pmode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static int usbhs_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) struct usbhs_hcd_omap *omap = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) struct usbhs_omap_platform_data *pdata = omap->pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) int i, r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) dev_dbg(dev, "usbhs_runtime_resume\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) omap_tll_enable(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) if (!IS_ERR(omap->ehci_logic_fck))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) clk_prepare_enable(omap->ehci_logic_fck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) for (i = 0; i < omap->nports; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) switch (pdata->port_mode[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) case OMAP_EHCI_PORT_MODE_HSIC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (!IS_ERR(omap->hsic60m_clk[i])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) r = clk_prepare_enable(omap->hsic60m_clk[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) dev_err(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) "Can't enable port %d hsic60m clk:%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) i, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) if (!IS_ERR(omap->hsic480m_clk[i])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) r = clk_prepare_enable(omap->hsic480m_clk[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) dev_err(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) "Can't enable port %d hsic480m clk:%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) i, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) fallthrough; /* as HSIC mode needs utmi_clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) case OMAP_EHCI_PORT_MODE_TLL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) if (!IS_ERR(omap->utmi_clk[i])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) r = clk_prepare_enable(omap->utmi_clk[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) dev_err(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) "Can't enable port %d clk : %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) i, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) static int usbhs_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) struct usbhs_hcd_omap *omap = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) struct usbhs_omap_platform_data *pdata = omap->pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) dev_dbg(dev, "usbhs_runtime_suspend\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) for (i = 0; i < omap->nports; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) switch (pdata->port_mode[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) case OMAP_EHCI_PORT_MODE_HSIC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) if (!IS_ERR(omap->hsic60m_clk[i]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) clk_disable_unprepare(omap->hsic60m_clk[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) if (!IS_ERR(omap->hsic480m_clk[i]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) clk_disable_unprepare(omap->hsic480m_clk[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) fallthrough; /* as utmi_clks were used in HSIC mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) case OMAP_EHCI_PORT_MODE_TLL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) if (!IS_ERR(omap->utmi_clk[i]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) clk_disable_unprepare(omap->utmi_clk[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) if (!IS_ERR(omap->ehci_logic_fck))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) clk_disable_unprepare(omap->ehci_logic_fck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) omap_tll_disable(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) static unsigned omap_usbhs_rev1_hostconfig(struct usbhs_hcd_omap *omap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) unsigned reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) struct usbhs_omap_platform_data *pdata = omap->pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) for (i = 0; i < omap->nports; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) switch (pdata->port_mode[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) case OMAP_USBHS_PORT_MODE_UNUSED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) reg &= ~(OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS << i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) case OMAP_EHCI_PORT_MODE_PHY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) if (pdata->single_ulpi_bypass)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) if (i == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) reg &= ~(OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) << (i-1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) if (pdata->single_ulpi_bypass)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) if (i == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) reg |= OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) reg |= OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) << (i-1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) if (pdata->single_ulpi_bypass) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) /* bypass ULPI only if none of the ports use PHY mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) reg |= OMAP_UHH_HOSTCONFIG_ULPI_BYPASS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) for (i = 0; i < omap->nports; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) if (is_ehci_phy_mode(pdata->port_mode[i])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_BYPASS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) return reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) static unsigned omap_usbhs_rev2_hostconfig(struct usbhs_hcd_omap *omap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) unsigned reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) struct usbhs_omap_platform_data *pdata = omap->pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) for (i = 0; i < omap->nports; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) /* Clear port mode fields for PHY mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) reg &= ~(OMAP4_P1_MODE_CLEAR << 2 * i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) if (is_ehci_tll_mode(pdata->port_mode[i]) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) (is_ohci_port(pdata->port_mode[i])))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) reg |= OMAP4_P1_MODE_TLL << 2 * i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) else if (is_ehci_hsic_mode(pdata->port_mode[i]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) reg |= OMAP4_P1_MODE_HSIC << 2 * i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) return reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static void omap_usbhs_init(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) struct usbhs_hcd_omap *omap = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) unsigned reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) dev_dbg(dev, "starting TI HSUSB Controller\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) pm_runtime_get_sync(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) reg = usbhs_read(omap->uhh_base, OMAP_UHH_HOSTCONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) /* setup ULPI bypass and burst configurations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) reg |= (OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) | OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) | OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) reg |= OMAP4_UHH_HOSTCONFIG_APP_START_CLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) reg &= ~OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) switch (omap->usbhs_rev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) case OMAP_USBHS_REV1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) reg = omap_usbhs_rev1_hostconfig(omap, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) case OMAP_USBHS_REV2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) reg = omap_usbhs_rev2_hostconfig(omap, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) default: /* newer revisions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) reg = omap_usbhs_rev2_hostconfig(omap, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) usbhs_write(omap->uhh_base, OMAP_UHH_HOSTCONFIG, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) dev_dbg(dev, "UHH setup done, uhh_hostconfig=%x\n", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) pm_runtime_put_sync(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) static int usbhs_omap_get_dt_pdata(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) struct usbhs_omap_platform_data *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) ret = of_property_read_u32(node, "num-ports", &pdata->nports);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) pdata->nports = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) if (pdata->nports > OMAP3_HS_USB_PORTS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) dev_warn(dev, "Too many num_ports <%d> in device tree. Max %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) pdata->nports, OMAP3_HS_USB_PORTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) /* get port modes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) for (i = 0; i < OMAP3_HS_USB_PORTS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) char prop[11];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) const char *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) pdata->port_mode[i] = OMAP_USBHS_PORT_MODE_UNUSED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) snprintf(prop, sizeof(prop), "port%d-mode", i + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) ret = of_property_read_string(node, prop, &mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) /* get 'enum usbhs_omap_port_mode' from port mode string */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) ret = match_string(port_modes, ARRAY_SIZE(port_modes), mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) dev_warn(dev, "Invalid port%d-mode \"%s\" in device tree\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) i, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) dev_dbg(dev, "port%d-mode: %s -> %d\n", i, mode, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) pdata->port_mode[i] = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) /* get flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) pdata->single_ulpi_bypass = of_property_read_bool(node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) "single-ulpi-bypass");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) static const struct of_device_id usbhs_child_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) { .compatible = "ti,ehci-omap", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) { .compatible = "ti,ohci-omap3", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) * usbhs_omap_probe - initialize TI-based HCDs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) * Allocates basic resources for this USB host controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) * @pdev: Pointer to this device's platform device structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) static int usbhs_omap_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) struct usbhs_omap_platform_data *pdata = dev_get_platdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) struct usbhs_hcd_omap *omap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) bool need_logic_fck;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) if (dev->of_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) /* For DT boot we populate platform data from OF node */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) if (!pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) ret = usbhs_omap_get_dt_pdata(dev, pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) dev->platform_data = pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) if (!pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) dev_err(dev, "Missing platform data\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) if (pdata->nports > OMAP3_HS_USB_PORTS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) dev_info(dev, "Too many num_ports <%d> in platform_data. Max %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) pdata->nports, OMAP3_HS_USB_PORTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) omap = devm_kzalloc(dev, sizeof(*omap), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) if (!omap) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) dev_err(dev, "Memory allocation failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) omap->uhh_base = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) if (IS_ERR(omap->uhh_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) return PTR_ERR(omap->uhh_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) omap->pdata = pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) /* Initialize the TLL subsystem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) omap_tll_init(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) platform_set_drvdata(pdev, omap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) pm_runtime_get_sync(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) omap->usbhs_rev = usbhs_read(omap->uhh_base, OMAP_UHH_REVISION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) /* we need to call runtime suspend before we update omap->nports
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) * to prevent unbalanced clk_disable()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) pm_runtime_put_sync(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) * If platform data contains nports then use that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) * else make out number of ports from USBHS revision
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) if (pdata->nports) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) omap->nports = pdata->nports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) switch (omap->usbhs_rev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) case OMAP_USBHS_REV1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) omap->nports = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) case OMAP_USBHS_REV2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) omap->nports = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) omap->nports = OMAP3_HS_USB_PORTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) dev_dbg(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) "USB HOST Rev:0x%x not recognized, assuming %d ports\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) omap->usbhs_rev, omap->nports);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) pdata->nports = omap->nports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) i = sizeof(struct clk *) * omap->nports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) omap->utmi_clk = devm_kzalloc(dev, i, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) omap->hsic480m_clk = devm_kzalloc(dev, i, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) omap->hsic60m_clk = devm_kzalloc(dev, i, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) if (!omap->utmi_clk || !omap->hsic480m_clk || !omap->hsic60m_clk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) dev_err(dev, "Memory allocation failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) goto err_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) /* Set all clocks as invalid to begin with */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) omap->ehci_logic_fck = ERR_PTR(-ENODEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) omap->init_60m_fclk = ERR_PTR(-ENODEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) omap->utmi_p1_gfclk = ERR_PTR(-ENODEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) omap->utmi_p2_gfclk = ERR_PTR(-ENODEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) omap->xclk60mhsp1_ck = ERR_PTR(-ENODEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) omap->xclk60mhsp2_ck = ERR_PTR(-ENODEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) for (i = 0; i < omap->nports; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) omap->utmi_clk[i] = ERR_PTR(-ENODEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) omap->hsic480m_clk[i] = ERR_PTR(-ENODEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) omap->hsic60m_clk[i] = ERR_PTR(-ENODEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) /* for OMAP3 i.e. USBHS REV1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) if (omap->usbhs_rev == OMAP_USBHS_REV1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) need_logic_fck = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) for (i = 0; i < omap->nports; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) if (is_ehci_phy_mode(pdata->port_mode[i]) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) is_ehci_tll_mode(pdata->port_mode[i]) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) is_ehci_hsic_mode(pdata->port_mode[i]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) need_logic_fck |= true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) if (need_logic_fck) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) omap->ehci_logic_fck = devm_clk_get(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) "usbhost_120m_fck");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) if (IS_ERR(omap->ehci_logic_fck)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) ret = PTR_ERR(omap->ehci_logic_fck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) dev_err(dev, "usbhost_120m_fck failed:%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) goto err_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) goto initialize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) /* for OMAP4+ i.e. USBHS REV2+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) omap->utmi_p1_gfclk = devm_clk_get(dev, "utmi_p1_gfclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) if (IS_ERR(omap->utmi_p1_gfclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) ret = PTR_ERR(omap->utmi_p1_gfclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) dev_err(dev, "utmi_p1_gfclk failed error:%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) goto err_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) omap->utmi_p2_gfclk = devm_clk_get(dev, "utmi_p2_gfclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) if (IS_ERR(omap->utmi_p2_gfclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) ret = PTR_ERR(omap->utmi_p2_gfclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) dev_err(dev, "utmi_p2_gfclk failed error:%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) goto err_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) omap->xclk60mhsp1_ck = devm_clk_get(dev, "refclk_60m_ext_p1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) if (IS_ERR(omap->xclk60mhsp1_ck)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) ret = PTR_ERR(omap->xclk60mhsp1_ck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) dev_err(dev, "refclk_60m_ext_p1 failed error:%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) goto err_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) omap->xclk60mhsp2_ck = devm_clk_get(dev, "refclk_60m_ext_p2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) if (IS_ERR(omap->xclk60mhsp2_ck)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) ret = PTR_ERR(omap->xclk60mhsp2_ck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) dev_err(dev, "refclk_60m_ext_p2 failed error:%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) goto err_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) omap->init_60m_fclk = devm_clk_get(dev, "refclk_60m_int");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) if (IS_ERR(omap->init_60m_fclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) ret = PTR_ERR(omap->init_60m_fclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) dev_err(dev, "refclk_60m_int failed error:%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) goto err_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) for (i = 0; i < omap->nports; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) char clkname[30];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) /* clock names are indexed from 1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) snprintf(clkname, sizeof(clkname),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) "usb_host_hs_utmi_p%d_clk", i + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) /* If a clock is not found we won't bail out as not all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) * platforms have all clocks and we can function without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) * them
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) omap->utmi_clk[i] = devm_clk_get(dev, clkname);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) if (IS_ERR(omap->utmi_clk[i])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) ret = PTR_ERR(omap->utmi_clk[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) dev_err(dev, "Failed to get clock : %s : %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) clkname, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) goto err_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) snprintf(clkname, sizeof(clkname),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) "usb_host_hs_hsic480m_p%d_clk", i + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) omap->hsic480m_clk[i] = devm_clk_get(dev, clkname);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) if (IS_ERR(omap->hsic480m_clk[i])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) ret = PTR_ERR(omap->hsic480m_clk[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) dev_err(dev, "Failed to get clock : %s : %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) clkname, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) goto err_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) snprintf(clkname, sizeof(clkname),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) "usb_host_hs_hsic60m_p%d_clk", i + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) omap->hsic60m_clk[i] = devm_clk_get(dev, clkname);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) if (IS_ERR(omap->hsic60m_clk[i])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) ret = PTR_ERR(omap->hsic60m_clk[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) dev_err(dev, "Failed to get clock : %s : %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) clkname, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) goto err_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) if (is_ehci_phy_mode(pdata->port_mode[0])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) ret = clk_set_parent(omap->utmi_p1_gfclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) omap->xclk60mhsp1_ck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) dev_err(dev, "xclk60mhsp1_ck set parent failed: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) goto err_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) } else if (is_ehci_tll_mode(pdata->port_mode[0])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) ret = clk_set_parent(omap->utmi_p1_gfclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) omap->init_60m_fclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) dev_err(dev, "P0 init_60m_fclk set parent failed: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) goto err_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) if (is_ehci_phy_mode(pdata->port_mode[1])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) ret = clk_set_parent(omap->utmi_p2_gfclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) omap->xclk60mhsp2_ck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) dev_err(dev, "xclk60mhsp2_ck set parent failed: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) goto err_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) } else if (is_ehci_tll_mode(pdata->port_mode[1])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) ret = clk_set_parent(omap->utmi_p2_gfclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) omap->init_60m_fclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) dev_err(dev, "P1 init_60m_fclk set parent failed: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) goto err_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) initialize:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) omap_usbhs_init(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) if (dev->of_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) ret = of_platform_populate(dev->of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) usbhs_child_match_table, NULL, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) dev_err(dev, "Failed to create DT children: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) goto err_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) ret = omap_usbhs_alloc_children(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) dev_err(dev, "omap_usbhs_alloc_children failed: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) goto err_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) err_mem:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) pm_runtime_disable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) static int usbhs_omap_remove_child(struct device *dev, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) dev_info(dev, "unregistering\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) platform_device_unregister(to_platform_device(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) * usbhs_omap_remove - shutdown processing for UHH & TLL HCDs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) * @pdev: USB Host Controller being removed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) * Reverses the effect of usbhs_omap_probe().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) static int usbhs_omap_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) /* remove children */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) device_for_each_child(&pdev->dev, NULL, usbhs_omap_remove_child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) static const struct dev_pm_ops usbhsomap_dev_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) .runtime_suspend = usbhs_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) .runtime_resume = usbhs_runtime_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) static const struct of_device_id usbhs_omap_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) { .compatible = "ti,usbhs-host" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) MODULE_DEVICE_TABLE(of, usbhs_omap_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) static struct platform_driver usbhs_omap_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) .name = usbhs_driver_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) .pm = &usbhsomap_dev_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) .of_match_table = usbhs_omap_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) .probe = usbhs_omap_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) .remove = usbhs_omap_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) MODULE_AUTHOR("Keshava Munegowda <keshava_mgowda@ti.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) MODULE_AUTHOR("Roger Quadros <rogerq@ti.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) MODULE_ALIAS("platform:" USBHS_DRIVER_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) MODULE_DESCRIPTION("usb host common core driver for omap EHCI and OHCI");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) static int omap_usbhs_drvinit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) return platform_driver_register(&usbhs_omap_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) * init before ehci and ohci drivers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) * The usbhs core driver should be initialized much before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) * the omap ehci and ohci probe functions are called.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) * This usbhs core driver should be initialized after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) * usb tll driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) fs_initcall_sync(omap_usbhs_drvinit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) static void omap_usbhs_drvexit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) platform_driver_unregister(&usbhs_omap_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) module_exit(omap_usbhs_drvexit);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags