Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) // Copyright (c) 2019 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/suspend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/mfd/mt6323/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/mfd/mt6323/registers.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/mfd/mt6397/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/mfd/mt6397/registers.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) static void mt6397_irq_lock(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 	struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	mutex_lock(&mt6397->irqlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) static void mt6397_irq_sync_unlock(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	regmap_write(mt6397->regmap, mt6397->int_con[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 		     mt6397->irq_masks_cur[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	regmap_write(mt6397->regmap, mt6397->int_con[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 		     mt6397->irq_masks_cur[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	mutex_unlock(&mt6397->irqlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) static void mt6397_irq_disable(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	int shift = data->hwirq & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	int reg = data->hwirq >> 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	mt6397->irq_masks_cur[reg] &= ~BIT(shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) static void mt6397_irq_enable(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	int shift = data->hwirq & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	int reg = data->hwirq >> 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	mt6397->irq_masks_cur[reg] |= BIT(shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) static int mt6397_irq_set_wake(struct irq_data *irq_data, unsigned int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(irq_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	int shift = irq_data->hwirq & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	int reg = irq_data->hwirq >> 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	if (on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 		mt6397->wake_mask[reg] |= BIT(shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 		mt6397->wake_mask[reg] &= ~BIT(shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define mt6397_irq_set_wake NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) static struct irq_chip mt6397_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	.name = "mt6397-irq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	.irq_bus_lock = mt6397_irq_lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	.irq_bus_sync_unlock = mt6397_irq_sync_unlock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	.irq_enable = mt6397_irq_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	.irq_disable = mt6397_irq_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	.irq_set_wake = mt6397_irq_set_wake,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) static void mt6397_irq_handle_reg(struct mt6397_chip *mt6397, int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 				  int irqbase)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	unsigned int status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	int i, irq, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	ret = regmap_read(mt6397->regmap, reg, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		dev_err(mt6397->dev, "Failed to read irq status: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	for (i = 0; i < 16; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		if (status & BIT(i)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 			irq = irq_find_mapping(mt6397->irq_domain, irqbase + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 			if (irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 				handle_nested_irq(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	regmap_write(mt6397->regmap, reg, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static irqreturn_t mt6397_irq_thread(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	struct mt6397_chip *mt6397 = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	mt6397_irq_handle_reg(mt6397, mt6397->int_status[0], 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	mt6397_irq_handle_reg(mt6397, mt6397->int_status[1], 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static int mt6397_irq_domain_map(struct irq_domain *d, unsigned int irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 				 irq_hw_number_t hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	struct mt6397_chip *mt6397 = d->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	irq_set_chip_data(irq, mt6397);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	irq_set_chip_and_handler(irq, &mt6397_irq_chip, handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	irq_set_nested_thread(irq, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	irq_set_noprobe(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static const struct irq_domain_ops mt6397_irq_domain_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	.map = mt6397_irq_domain_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static int mt6397_irq_pm_notifier(struct notifier_block *notifier,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 				  unsigned long pm_event, void *unused)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	struct mt6397_chip *chip =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		container_of(notifier, struct mt6397_chip, pm_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	switch (pm_event) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	case PM_SUSPEND_PREPARE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		regmap_write(chip->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 			     chip->int_con[0], chip->wake_mask[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		regmap_write(chip->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 			     chip->int_con[1], chip->wake_mask[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		enable_irq_wake(chip->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	case PM_POST_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		regmap_write(chip->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 			     chip->int_con[0], chip->irq_masks_cur[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		regmap_write(chip->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 			     chip->int_con[1], chip->irq_masks_cur[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		disable_irq_wake(chip->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	return NOTIFY_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) int mt6397_irq_init(struct mt6397_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	mutex_init(&chip->irqlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	switch (chip->chip_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	case MT6323_CHIP_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		chip->int_con[0] = MT6323_INT_CON0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		chip->int_con[1] = MT6323_INT_CON1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		chip->int_status[0] = MT6323_INT_STATUS0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		chip->int_status[1] = MT6323_INT_STATUS1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	case MT6391_CHIP_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	case MT6397_CHIP_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		chip->int_con[0] = MT6397_INT_CON0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		chip->int_con[1] = MT6397_INT_CON1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		chip->int_status[0] = MT6397_INT_STATUS0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		chip->int_status[1] = MT6397_INT_STATUS1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		dev_err(chip->dev, "unsupported chip: 0x%x\n", chip->chip_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	/* Mask all interrupt sources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	regmap_write(chip->regmap, chip->int_con[0], 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	regmap_write(chip->regmap, chip->int_con[1], 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	chip->pm_nb.notifier_call = mt6397_irq_pm_notifier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	chip->irq_domain = irq_domain_add_linear(chip->dev->of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 						 MT6397_IRQ_NR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 						 &mt6397_irq_domain_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 						 chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	if (!chip->irq_domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		dev_err(chip->dev, "could not create irq domain\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	ret = devm_request_threaded_irq(chip->dev, chip->irq, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 					mt6397_irq_thread, IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 					"mt6397-pmic", chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		dev_err(chip->dev, "failed to register irq=%d; err: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 			chip->irq, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	register_pm_notifier(&chip->pm_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }