^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // Copyright (c) 2020 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/mfd/mt6358/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/mfd/mt6358/registers.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/mfd/mt6397/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) static struct irq_top_t mt6358_ints[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) MT6358_TOP_GEN(BUCK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) MT6358_TOP_GEN(LDO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) MT6358_TOP_GEN(PSC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) MT6358_TOP_GEN(SCK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) MT6358_TOP_GEN(BM),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) MT6358_TOP_GEN(HK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) MT6358_TOP_GEN(AUD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) MT6358_TOP_GEN(MISC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) static void pmic_irq_enable(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) unsigned int hwirq = irqd_to_hwirq(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct mt6397_chip *chip = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct pmic_irq_data *irqd = chip->irq_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) irqd->enable_hwirq[hwirq] = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static void pmic_irq_disable(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) unsigned int hwirq = irqd_to_hwirq(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct mt6397_chip *chip = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct pmic_irq_data *irqd = chip->irq_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) irqd->enable_hwirq[hwirq] = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static void pmic_irq_lock(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct mt6397_chip *chip = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) mutex_lock(&chip->irqlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static void pmic_irq_sync_unlock(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) unsigned int i, top_gp, gp_offset, en_reg, int_regs, shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct mt6397_chip *chip = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct pmic_irq_data *irqd = chip->irq_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) for (i = 0; i < irqd->num_pmic_irqs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) if (irqd->enable_hwirq[i] == irqd->cache_hwirq[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* Find out the IRQ group */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) top_gp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) while ((top_gp + 1) < irqd->num_top &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) i >= mt6358_ints[top_gp + 1].hwirq_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) top_gp++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* Find the IRQ registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) gp_offset = i - mt6358_ints[top_gp].hwirq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) int_regs = gp_offset / MT6358_REG_WIDTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) shift = gp_offset % MT6358_REG_WIDTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) en_reg = mt6358_ints[top_gp].en_reg +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) (mt6358_ints[top_gp].en_reg_shift * int_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) regmap_update_bits(chip->regmap, en_reg, BIT(shift),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) irqd->enable_hwirq[i] << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) irqd->cache_hwirq[i] = irqd->enable_hwirq[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) mutex_unlock(&chip->irqlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static struct irq_chip mt6358_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .name = "mt6358-irq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .flags = IRQCHIP_SKIP_SET_WAKE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .irq_enable = pmic_irq_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .irq_disable = pmic_irq_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .irq_bus_lock = pmic_irq_lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .irq_bus_sync_unlock = pmic_irq_sync_unlock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static void mt6358_irq_sp_handler(struct mt6397_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) unsigned int top_gp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) unsigned int irq_status, sta_reg, status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) unsigned int hwirq, virq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) int i, j, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) for (i = 0; i < mt6358_ints[top_gp].num_int_regs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) sta_reg = mt6358_ints[top_gp].sta_reg +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) mt6358_ints[top_gp].sta_reg_shift * i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) ret = regmap_read(chip->regmap, sta_reg, &irq_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) dev_err(chip->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) "Failed to read IRQ status, ret=%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) if (!irq_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) status = irq_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) j = __ffs(status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) hwirq = mt6358_ints[top_gp].hwirq_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) MT6358_REG_WIDTH * i + j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) virq = irq_find_mapping(chip->irq_domain, hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) if (virq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) handle_nested_irq(virq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) status &= ~BIT(j);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) } while (status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) regmap_write(chip->regmap, sta_reg, irq_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static irqreturn_t mt6358_irq_handler(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct mt6397_chip *chip = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct pmic_irq_data *mt6358_irq_data = chip->irq_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) unsigned int bit, i, top_irq_status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) ret = regmap_read(chip->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) mt6358_irq_data->top_int_status_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) &top_irq_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) dev_err(chip->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) "Failed to read status from the device, ret=%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) for (i = 0; i < mt6358_irq_data->num_top; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) bit = BIT(mt6358_ints[i].top_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) if (top_irq_status & bit) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) mt6358_irq_sp_handler(chip, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) top_irq_status &= ~bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) if (!top_irq_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static int pmic_irq_domain_map(struct irq_domain *d, unsigned int irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) irq_hw_number_t hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct mt6397_chip *mt6397 = d->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) irq_set_chip_data(irq, mt6397);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) irq_set_chip_and_handler(irq, &mt6358_irq_chip, handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) irq_set_nested_thread(irq, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) irq_set_noprobe(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static const struct irq_domain_ops mt6358_irq_domain_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .map = pmic_irq_domain_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .xlate = irq_domain_xlate_twocell,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) int mt6358_irq_init(struct mt6397_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) int i, j, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) struct pmic_irq_data *irqd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) irqd = devm_kzalloc(chip->dev, sizeof(*irqd), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (!irqd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) chip->irq_data = irqd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) mutex_init(&chip->irqlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) irqd->top_int_status_reg = MT6358_TOP_INT_STATUS0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) irqd->num_pmic_irqs = MT6358_IRQ_NR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) irqd->num_top = ARRAY_SIZE(mt6358_ints);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) irqd->enable_hwirq = devm_kcalloc(chip->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) irqd->num_pmic_irqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) sizeof(*irqd->enable_hwirq),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if (!irqd->enable_hwirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) irqd->cache_hwirq = devm_kcalloc(chip->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) irqd->num_pmic_irqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) sizeof(*irqd->cache_hwirq),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if (!irqd->cache_hwirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /* Disable all interrupts for initializing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) for (i = 0; i < irqd->num_top; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) for (j = 0; j < mt6358_ints[i].num_int_regs; j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) regmap_write(chip->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) mt6358_ints[i].en_reg +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) mt6358_ints[i].en_reg_shift * j, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) chip->irq_domain = irq_domain_add_linear(chip->dev->of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) irqd->num_pmic_irqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) &mt6358_irq_domain_ops, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (!chip->irq_domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) dev_err(chip->dev, "Could not create IRQ domain\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) ret = devm_request_threaded_irq(chip->dev, chip->irq, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) mt6358_irq_handler, IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) mt6358_irq_chip.name, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) dev_err(chip->dev, "Failed to register IRQ=%d, ret=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) chip->irq, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) enable_irq_wake(chip->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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