Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) // Interrupt controller support for MAX8998
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) // Copyright (C) 2010 Samsung Electronics Co.Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) // Author: Joonyoung Shim <jy0922.shim@samsung.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/mfd/max8998-private.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) struct max8998_irq_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 	int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 	int mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) static struct max8998_irq_data max8998_irqs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 	[MAX8998_IRQ_DCINF] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 		.reg = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 		.mask = MAX8998_IRQ_DCINF_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	[MAX8998_IRQ_DCINR] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 		.reg = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 		.mask = MAX8998_IRQ_DCINR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	[MAX8998_IRQ_JIGF] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 		.reg = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 		.mask = MAX8998_IRQ_JIGF_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	[MAX8998_IRQ_JIGR] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 		.reg = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 		.mask = MAX8998_IRQ_JIGR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	[MAX8998_IRQ_PWRONF] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 		.reg = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 		.mask = MAX8998_IRQ_PWRONF_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	[MAX8998_IRQ_PWRONR] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 		.reg = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 		.mask = MAX8998_IRQ_PWRONR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	[MAX8998_IRQ_WTSREVNT] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 		.reg = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 		.mask = MAX8998_IRQ_WTSREVNT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	[MAX8998_IRQ_SMPLEVNT] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 		.reg = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 		.mask = MAX8998_IRQ_SMPLEVNT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	[MAX8998_IRQ_ALARM1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 		.reg = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 		.mask = MAX8998_IRQ_ALARM1_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	[MAX8998_IRQ_ALARM0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 		.reg = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 		.mask = MAX8998_IRQ_ALARM0_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	[MAX8998_IRQ_ONKEY1S] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 		.reg = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 		.mask = MAX8998_IRQ_ONKEY1S_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	[MAX8998_IRQ_TOPOFFR] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 		.reg = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 		.mask = MAX8998_IRQ_TOPOFFR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	[MAX8998_IRQ_DCINOVPR] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 		.reg = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 		.mask = MAX8998_IRQ_DCINOVPR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	[MAX8998_IRQ_CHGRSTF] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 		.reg = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		.mask = MAX8998_IRQ_CHGRSTF_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	[MAX8998_IRQ_DONER] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		.reg = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 		.mask = MAX8998_IRQ_DONER_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	[MAX8998_IRQ_CHGFAULT] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		.reg = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		.mask = MAX8998_IRQ_CHGFAULT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	[MAX8998_IRQ_LOBAT1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		.reg = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		.mask = MAX8998_IRQ_LOBAT1_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	[MAX8998_IRQ_LOBAT2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		.reg = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		.mask = MAX8998_IRQ_LOBAT2_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) static inline struct max8998_irq_data *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) irq_to_max8998_irq(struct max8998_dev *max8998, struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	return &max8998_irqs[data->hwirq];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static void max8998_irq_lock(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	struct max8998_dev *max8998 = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	mutex_lock(&max8998->irqlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static void max8998_irq_sync_unlock(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	struct max8998_dev *max8998 = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	for (i = 0; i < ARRAY_SIZE(max8998->irq_masks_cur); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		 * If there's been a change in the mask write it back
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		 * to the hardware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		if (max8998->irq_masks_cur[i] != max8998->irq_masks_cache[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 			max8998->irq_masks_cache[i] = max8998->irq_masks_cur[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 			max8998_write_reg(max8998->i2c, MAX8998_REG_IRQM1 + i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 					max8998->irq_masks_cur[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	mutex_unlock(&max8998->irqlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static void max8998_irq_unmask(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	struct max8998_dev *max8998 = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	struct max8998_irq_data *irq_data = irq_to_max8998_irq(max8998, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	max8998->irq_masks_cur[irq_data->reg - 1] &= ~irq_data->mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static void max8998_irq_mask(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	struct max8998_dev *max8998 = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	struct max8998_irq_data *irq_data = irq_to_max8998_irq(max8998, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	max8998->irq_masks_cur[irq_data->reg - 1] |= irq_data->mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static struct irq_chip max8998_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	.name = "max8998",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	.irq_bus_lock = max8998_irq_lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	.irq_bus_sync_unlock = max8998_irq_sync_unlock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	.irq_mask = max8998_irq_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	.irq_unmask = max8998_irq_unmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static irqreturn_t max8998_irq_thread(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	struct max8998_dev *max8998 = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	u8 irq_reg[MAX8998_NUM_IRQ_REGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	ret = max8998_bulk_read(max8998->i2c, MAX8998_REG_IRQ1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 			MAX8998_NUM_IRQ_REGS, irq_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		dev_err(max8998->dev, "Failed to read interrupt register: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 				ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	/* Apply masking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	for (i = 0; i < MAX8998_NUM_IRQ_REGS; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		irq_reg[i] &= ~max8998->irq_masks_cur[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	/* Report */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	for (i = 0; i < MAX8998_IRQ_NR; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		if (irq_reg[max8998_irqs[i].reg - 1] & max8998_irqs[i].mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 			irq = irq_find_mapping(max8998->irq_domain, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 			if (WARN_ON(!irq)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 				disable_irq_nosync(max8998->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 				return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 			handle_nested_irq(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) int max8998_irq_resume(struct max8998_dev *max8998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	if (max8998->irq && max8998->irq_domain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		max8998_irq_thread(max8998->irq, max8998);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static int max8998_irq_domain_map(struct irq_domain *d, unsigned int irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 					irq_hw_number_t hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	struct max8997_dev *max8998 = d->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	irq_set_chip_data(irq, max8998);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	irq_set_chip_and_handler(irq, &max8998_irq_chip, handle_edge_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	irq_set_nested_thread(irq, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	irq_set_noprobe(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static const struct irq_domain_ops max8998_irq_domain_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	.map = max8998_irq_domain_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) int max8998_irq_init(struct max8998_dev *max8998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	struct irq_domain *domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	if (!max8998->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		dev_warn(max8998->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 			 "No interrupt specified, no interrupts\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	mutex_init(&max8998->irqlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	/* Mask the individual interrupt sources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	for (i = 0; i < MAX8998_NUM_IRQ_REGS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		max8998->irq_masks_cur[i] = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		max8998->irq_masks_cache[i] = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		max8998_write_reg(max8998->i2c, MAX8998_REG_IRQM1 + i, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	max8998_write_reg(max8998->i2c, MAX8998_REG_STATUSM1, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	max8998_write_reg(max8998->i2c, MAX8998_REG_STATUSM2, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	domain = irq_domain_add_simple(NULL, MAX8998_IRQ_NR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 			max8998->irq_base, &max8998_irq_domain_ops, max8998);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	if (!domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		dev_err(max8998->dev, "could not create irq domain\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	max8998->irq_domain = domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	ret = request_threaded_irq(max8998->irq, NULL, max8998_irq_thread,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 				   IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 				   "max8998-irq", max8998);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		dev_err(max8998->dev, "Failed to request IRQ %d: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 			max8998->irq, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	if (!max8998->ono)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	ret = request_threaded_irq(max8998->ono, NULL, max8998_irq_thread,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 				   IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 				   IRQF_ONESHOT, "max8998-ono", max8998);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 		dev_err(max8998->dev, "Failed to request IRQ %d: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 			max8998->ono, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) void max8998_irq_exit(struct max8998_dev *max8998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	if (max8998->ono)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		free_irq(max8998->ono, max8998);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	if (max8998->irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		free_irq(max8998->irq, max8998);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }