Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) // max8997-irq.c - Interrupt controller support for MAX8997
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) // Copyright (C) 2011 Samsung Electronics Co.Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) // MyungJoo Ham <myungjoo.ham@samsung.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) // This driver is based on max8998-irq.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/mfd/max8997.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/mfd/max8997-private.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) static const u8 max8997_mask_reg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 	[PMIC_INT1] = MAX8997_REG_INT1MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 	[PMIC_INT2] = MAX8997_REG_INT2MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 	[PMIC_INT3] = MAX8997_REG_INT3MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 	[PMIC_INT4] = MAX8997_REG_INT4MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 	[FUEL_GAUGE] = MAX8997_REG_INVALID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	[MUIC_INT1] = MAX8997_MUIC_REG_INTMASK1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	[MUIC_INT2] = MAX8997_MUIC_REG_INTMASK2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	[MUIC_INT3] = MAX8997_MUIC_REG_INTMASK3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	[GPIO_LOW] = MAX8997_REG_INVALID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	[GPIO_HI] = MAX8997_REG_INVALID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	[FLASH_STATUS] = MAX8997_REG_INVALID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) static struct i2c_client *get_i2c(struct max8997_dev *max8997,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 				enum max8997_irq_source src)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	switch (src) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	case PMIC_INT1 ... PMIC_INT4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 		return max8997->i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	case FUEL_GAUGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 		return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	case MUIC_INT1 ... MUIC_INT3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 		return max8997->muic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	case GPIO_LOW ... GPIO_HI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 		return max8997->i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	case FLASH_STATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 		return max8997->i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 		return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) struct max8997_irq_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	int mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	enum max8997_irq_source group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define DECLARE_IRQ(idx, _group, _mask)		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	[(idx)] = { .group = (_group), .mask = (_mask) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) static const struct max8997_irq_data max8997_irqs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	DECLARE_IRQ(MAX8997_PMICIRQ_PWRONR,	PMIC_INT1, 1 << 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	DECLARE_IRQ(MAX8997_PMICIRQ_PWRONF,	PMIC_INT1, 1 << 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	DECLARE_IRQ(MAX8997_PMICIRQ_PWRON1SEC,	PMIC_INT1, 1 << 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	DECLARE_IRQ(MAX8997_PMICIRQ_JIGONR,	PMIC_INT1, 1 << 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	DECLARE_IRQ(MAX8997_PMICIRQ_JIGONF,	PMIC_INT1, 1 << 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	DECLARE_IRQ(MAX8997_PMICIRQ_LOWBAT2,	PMIC_INT1, 1 << 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	DECLARE_IRQ(MAX8997_PMICIRQ_LOWBAT1,	PMIC_INT1, 1 << 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	DECLARE_IRQ(MAX8997_PMICIRQ_JIGR,	PMIC_INT2, 1 << 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	DECLARE_IRQ(MAX8997_PMICIRQ_JIGF,	PMIC_INT2, 1 << 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	DECLARE_IRQ(MAX8997_PMICIRQ_MR,		PMIC_INT2, 1 << 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	DECLARE_IRQ(MAX8997_PMICIRQ_DVS1OK,	PMIC_INT2, 1 << 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	DECLARE_IRQ(MAX8997_PMICIRQ_DVS2OK,	PMIC_INT2, 1 << 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	DECLARE_IRQ(MAX8997_PMICIRQ_DVS3OK,	PMIC_INT2, 1 << 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	DECLARE_IRQ(MAX8997_PMICIRQ_DVS4OK,	PMIC_INT2, 1 << 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	DECLARE_IRQ(MAX8997_PMICIRQ_CHGINS,	PMIC_INT3, 1 << 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	DECLARE_IRQ(MAX8997_PMICIRQ_CHGRM,	PMIC_INT3, 1 << 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	DECLARE_IRQ(MAX8997_PMICIRQ_DCINOVP,	PMIC_INT3, 1 << 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	DECLARE_IRQ(MAX8997_PMICIRQ_TOPOFFR,	PMIC_INT3, 1 << 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	DECLARE_IRQ(MAX8997_PMICIRQ_CHGRSTF,	PMIC_INT3, 1 << 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	DECLARE_IRQ(MAX8997_PMICIRQ_MBCHGTMEXPD,	PMIC_INT3, 1 << 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	DECLARE_IRQ(MAX8997_PMICIRQ_RTC60S,	PMIC_INT4, 1 << 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	DECLARE_IRQ(MAX8997_PMICIRQ_RTCA1,	PMIC_INT4, 1 << 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	DECLARE_IRQ(MAX8997_PMICIRQ_RTCA2,	PMIC_INT4, 1 << 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	DECLARE_IRQ(MAX8997_PMICIRQ_SMPL_INT,	PMIC_INT4, 1 << 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	DECLARE_IRQ(MAX8997_PMICIRQ_RTC1S,	PMIC_INT4, 1 << 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	DECLARE_IRQ(MAX8997_PMICIRQ_WTSR,	PMIC_INT4, 1 << 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	DECLARE_IRQ(MAX8997_MUICIRQ_ADCError,	MUIC_INT1, 1 << 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	DECLARE_IRQ(MAX8997_MUICIRQ_ADCLow,	MUIC_INT1, 1 << 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	DECLARE_IRQ(MAX8997_MUICIRQ_ADC,	MUIC_INT1, 1 << 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	DECLARE_IRQ(MAX8997_MUICIRQ_VBVolt,	MUIC_INT2, 1 << 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	DECLARE_IRQ(MAX8997_MUICIRQ_DBChg,	MUIC_INT2, 1 << 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	DECLARE_IRQ(MAX8997_MUICIRQ_DCDTmr,	MUIC_INT2, 1 << 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	DECLARE_IRQ(MAX8997_MUICIRQ_ChgDetRun,	MUIC_INT2, 1 << 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	DECLARE_IRQ(MAX8997_MUICIRQ_ChgTyp,	MUIC_INT2, 1 << 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	DECLARE_IRQ(MAX8997_MUICIRQ_OVP,	MUIC_INT3, 1 << 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static void max8997_irq_lock(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	struct max8997_dev *max8997 = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	mutex_lock(&max8997->irqlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static void max8997_irq_sync_unlock(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	struct max8997_dev *max8997 = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	for (i = 0; i < MAX8997_IRQ_GROUP_NR; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 		u8 mask_reg = max8997_mask_reg[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		struct i2c_client *i2c = get_i2c(max8997, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		if (mask_reg == MAX8997_REG_INVALID ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 				IS_ERR_OR_NULL(i2c))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		max8997->irq_masks_cache[i] = max8997->irq_masks_cur[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		max8997_write_reg(i2c, max8997_mask_reg[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 				max8997->irq_masks_cur[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	mutex_unlock(&max8997->irqlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) inline static const struct max8997_irq_data *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) irq_to_max8997_irq(struct max8997_dev *max8997, struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	return &max8997_irqs[data->hwirq];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static void max8997_irq_mask(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	struct max8997_dev *max8997 = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	const struct max8997_irq_data *irq_data = irq_to_max8997_irq(max8997,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 								     data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	max8997->irq_masks_cur[irq_data->group] |= irq_data->mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static void max8997_irq_unmask(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	struct max8997_dev *max8997 = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	const struct max8997_irq_data *irq_data = irq_to_max8997_irq(max8997,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 								     data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	max8997->irq_masks_cur[irq_data->group] &= ~irq_data->mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static struct irq_chip max8997_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	.name			= "max8997",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	.irq_bus_lock		= max8997_irq_lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	.irq_bus_sync_unlock	= max8997_irq_sync_unlock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	.irq_mask		= max8997_irq_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	.irq_unmask		= max8997_irq_unmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define MAX8997_IRQSRC_PMIC		(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define MAX8997_IRQSRC_FUELGAUGE	(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define MAX8997_IRQSRC_MUIC		(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define MAX8997_IRQSRC_GPIO		(1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define MAX8997_IRQSRC_FLASH		(1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static irqreturn_t max8997_irq_thread(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	struct max8997_dev *max8997 = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	u8 irq_reg[MAX8997_IRQ_GROUP_NR] = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	u8 irq_src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	int i, cur_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	ret = max8997_read_reg(max8997->i2c, MAX8997_REG_INTSRC, &irq_src);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		dev_err(max8997->dev, "Failed to read interrupt source: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 				ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	if (irq_src & MAX8997_IRQSRC_PMIC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		/* PMIC INT1 ~ INT4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		max8997_bulk_read(max8997->i2c, MAX8997_REG_INT1, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 				&irq_reg[PMIC_INT1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	if (irq_src & MAX8997_IRQSRC_FUELGAUGE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		 * TODO: FUEL GAUGE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		 * This is to be supported by Max17042 driver. When
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		 * an interrupt incurs here, it should be relayed to a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		 * Max17042 device that is connected (probably by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		 * platform-data). However, we do not have interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		 * handling in Max17042 driver currently. The Max17042 IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		 * driver should be ready to be used as a stand-alone device and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		 * a Max8997-dependent device. Because it is not ready in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		 * Max17042-side and it is not too critical in operating
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		 * Max8997, we do not implement this in initial releases.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		irq_reg[FUEL_GAUGE] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	if (irq_src & MAX8997_IRQSRC_MUIC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		/* MUIC INT1 ~ INT3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		max8997_bulk_read(max8997->muic, MAX8997_MUIC_REG_INT1, 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 				&irq_reg[MUIC_INT1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	if (irq_src & MAX8997_IRQSRC_GPIO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		/* GPIO Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		u8 gpio_info[MAX8997_NUM_GPIO];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		irq_reg[GPIO_LOW] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		irq_reg[GPIO_HI] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		max8997_bulk_read(max8997->i2c, MAX8997_REG_GPIOCNTL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 				MAX8997_NUM_GPIO, gpio_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		for (i = 0; i < MAX8997_NUM_GPIO; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 			bool interrupt = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 			switch (gpio_info[i] & MAX8997_GPIO_INT_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 			case MAX8997_GPIO_INT_BOTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 				if (max8997->gpio_status[i] != gpio_info[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 					interrupt = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 				break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 			case MAX8997_GPIO_INT_RISE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 				if ((max8997->gpio_status[i] != gpio_info[i]) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 				    (gpio_info[i] & MAX8997_GPIO_DATA_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 					interrupt = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 				break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 			case MAX8997_GPIO_INT_FALL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 				if ((max8997->gpio_status[i] != gpio_info[i]) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 				    !(gpio_info[i] & MAX8997_GPIO_DATA_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 					interrupt = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 				break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 			default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 				break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 			if (interrupt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 				if (i < 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 					irq_reg[GPIO_LOW] |= (1 << i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 				else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 					irq_reg[GPIO_HI] |= (1 << (i - 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	if (irq_src & MAX8997_IRQSRC_FLASH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		/* Flash Status Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		ret = max8997_read_reg(max8997->i2c, MAX8997_REG_FLASHSTATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 				&irq_reg[FLASH_STATUS]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	/* Apply masking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	for (i = 0; i < MAX8997_IRQ_GROUP_NR; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		irq_reg[i] &= ~max8997->irq_masks_cur[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	/* Report */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	for (i = 0; i < MAX8997_IRQ_NR; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		if (irq_reg[max8997_irqs[i].group] & max8997_irqs[i].mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 			cur_irq = irq_find_mapping(max8997->irq_domain, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 			if (cur_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 				handle_nested_irq(cur_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) int max8997_irq_resume(struct max8997_dev *max8997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	if (max8997->irq && max8997->irq_domain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		max8997_irq_thread(0, max8997);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static int max8997_irq_domain_map(struct irq_domain *d, unsigned int irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 					irq_hw_number_t hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	struct max8997_dev *max8997 = d->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	irq_set_chip_data(irq, max8997);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	irq_set_chip_and_handler(irq, &max8997_irq_chip, handle_edge_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	irq_set_nested_thread(irq, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	irq_set_noprobe(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static const struct irq_domain_ops max8997_irq_domain_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	.map = max8997_irq_domain_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) int max8997_irq_init(struct max8997_dev *max8997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	struct irq_domain *domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	if (!max8997->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 		dev_warn(max8997->dev, "No interrupt specified.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	mutex_init(&max8997->irqlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	/* Mask individual interrupt sources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	for (i = 0; i < MAX8997_IRQ_GROUP_NR; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 		struct i2c_client *i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 		max8997->irq_masks_cur[i] = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 		max8997->irq_masks_cache[i] = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 		i2c = get_i2c(max8997, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 		if (IS_ERR_OR_NULL(i2c))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 		if (max8997_mask_reg[i] == MAX8997_REG_INVALID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 		max8997_write_reg(i2c, max8997_mask_reg[i], 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	for (i = 0; i < MAX8997_NUM_GPIO; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 		max8997->gpio_status[i] = (max8997_read_reg(max8997->i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 						MAX8997_REG_GPIOCNTL1 + i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 						&val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 					& MAX8997_GPIO_DATA_MASK) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 					true : false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	domain = irq_domain_add_linear(NULL, MAX8997_IRQ_NR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 					&max8997_irq_domain_ops, max8997);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	if (!domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 		dev_err(max8997->dev, "could not create irq domain\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	max8997->irq_domain = domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	ret = request_threaded_irq(max8997->irq, NULL, max8997_irq_thread,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 			IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 			"max8997-irq", max8997);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 		dev_err(max8997->dev, "Failed to request IRQ %d: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 				max8997->irq, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	if (!max8997->ono)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	ret = request_threaded_irq(max8997->ono, NULL, max8997_irq_thread,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 			IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 			IRQF_ONESHOT, "max8997-ono", max8997);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 		dev_err(max8997->dev, "Failed to request ono-IRQ %d: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 				max8997->ono, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) void max8997_irq_exit(struct max8997_dev *max8997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	if (max8997->ono)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 		free_irq(max8997->ono, max8997);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	if (max8997->irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 		free_irq(max8997->irq, max8997);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) }