Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) // max77686.c - mfd core driver for the Maxim 77686/802
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) // Copyright (C) 2012 Samsung Electronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) // Chiwoong Byun <woong.byun@samsung.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) // Jonghwa Lee <jonghwa3.lee@samsung.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) //This driver is based on max8997.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/mfd/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/mfd/max77686.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/mfd/max77686-private.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) static const struct mfd_cell max77686_devs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	{ .name = "max77686-pmic", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	{ .name = "max77686-rtc", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	{ .name = "max77686-clk", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) static const struct mfd_cell max77802_devs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	{ .name = "max77802-pmic", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	{ .name = "max77802-clk", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	{ .name = "max77802-rtc", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) static bool max77802_pmic_is_accessible_reg(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 					    unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	return reg < MAX77802_REG_PMIC_END;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) static bool max77802_rtc_is_accessible_reg(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 					   unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	return (reg >= MAX77802_RTC_INT && reg < MAX77802_RTC_END);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) static bool max77802_is_accessible_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	return (max77802_pmic_is_accessible_reg(dev, reg) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 		max77802_rtc_is_accessible_reg(dev, reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) static bool max77802_pmic_is_precious_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	return (reg == MAX77802_REG_INTSRC || reg == MAX77802_REG_INT1 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 		reg == MAX77802_REG_INT2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) static bool max77802_rtc_is_precious_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	return (reg == MAX77802_RTC_INT ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 		reg == MAX77802_RTC_UPDATE0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 		reg == MAX77802_RTC_UPDATE1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) static bool max77802_is_precious_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	return (max77802_pmic_is_precious_reg(dev, reg) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 		max77802_rtc_is_precious_reg(dev, reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) static bool max77802_pmic_is_volatile_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	return (max77802_is_precious_reg(dev, reg) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		reg == MAX77802_REG_STATUS1 || reg == MAX77802_REG_STATUS2 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 		reg == MAX77802_REG_PWRON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) static bool max77802_rtc_is_volatile_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	return (max77802_rtc_is_precious_reg(dev, reg) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		reg == MAX77802_RTC_SEC ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		reg == MAX77802_RTC_MIN ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		reg == MAX77802_RTC_HOUR ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 		reg == MAX77802_RTC_WEEKDAY ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		reg == MAX77802_RTC_MONTH ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		reg == MAX77802_RTC_YEAR ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		reg == MAX77802_RTC_DATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) static bool max77802_is_volatile_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	return (max77802_pmic_is_volatile_reg(dev, reg) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		max77802_rtc_is_volatile_reg(dev, reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) static const struct regmap_config max77686_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	.reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	.val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static const struct regmap_config max77802_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	.reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	.val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	.writeable_reg = max77802_is_accessible_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	.readable_reg = max77802_is_accessible_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	.precious_reg = max77802_is_precious_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	.volatile_reg = max77802_is_volatile_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	.name = "max77802-pmic",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	.cache_type = REGCACHE_RBTREE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static const struct regmap_irq max77686_irqs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	/* INT1 interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	{ .reg_offset = 0, .mask = MAX77686_INT1_PWRONF_MSK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	{ .reg_offset = 0, .mask = MAX77686_INT1_PWRONR_MSK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	{ .reg_offset = 0, .mask = MAX77686_INT1_JIGONBF_MSK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	{ .reg_offset = 0, .mask = MAX77686_INT1_JIGONBR_MSK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	{ .reg_offset = 0, .mask = MAX77686_INT1_ACOKBF_MSK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	{ .reg_offset = 0, .mask = MAX77686_INT1_ACOKBR_MSK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	{ .reg_offset = 0, .mask = MAX77686_INT1_ONKEY1S_MSK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	{ .reg_offset = 0, .mask = MAX77686_INT1_MRSTB_MSK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	/* INT2 interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	{ .reg_offset = 1, .mask = MAX77686_INT2_140C_MSK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	{ .reg_offset = 1, .mask = MAX77686_INT2_120C_MSK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static const struct regmap_irq_chip max77686_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	.name			= "max77686-pmic",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	.status_base		= MAX77686_REG_INT1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	.mask_base		= MAX77686_REG_INT1MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	.num_regs		= 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	.irqs			= max77686_irqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	.num_irqs		= ARRAY_SIZE(max77686_irqs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static const struct regmap_irq_chip max77802_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	.name			= "max77802-pmic",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	.status_base		= MAX77802_REG_INT1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	.mask_base		= MAX77802_REG_INT1MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	.num_regs		= 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	.irqs			= max77686_irqs, /* same masks as 77686 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	.num_irqs		= ARRAY_SIZE(max77686_irqs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static const struct of_device_id max77686_pmic_dt_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		.compatible = "maxim,max77686",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		.data = (void *)TYPE_MAX77686,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		.compatible = "maxim,max77802",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		.data = (void *)TYPE_MAX77802,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	{ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) MODULE_DEVICE_TABLE(of, max77686_pmic_dt_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static int max77686_i2c_probe(struct i2c_client *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	struct max77686_dev *max77686 = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	unsigned int data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	const struct regmap_config *config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	const struct regmap_irq_chip *irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	const struct mfd_cell *cells;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	int n_devs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	max77686 = devm_kzalloc(&i2c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 				sizeof(struct max77686_dev), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	if (!max77686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	i2c_set_clientdata(i2c, max77686);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	max77686->type = (unsigned long)of_device_get_match_data(&i2c->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	max77686->dev = &i2c->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	max77686->i2c = i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	max77686->irq = i2c->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	if (max77686->type == TYPE_MAX77686) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		config = &max77686_regmap_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		irq_chip = &max77686_irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		cells =  max77686_devs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		n_devs = ARRAY_SIZE(max77686_devs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		config = &max77802_regmap_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		irq_chip = &max77802_irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		cells =  max77802_devs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		n_devs = ARRAY_SIZE(max77802_devs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	max77686->regmap = devm_regmap_init_i2c(i2c, config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	if (IS_ERR(max77686->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		ret = PTR_ERR(max77686->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		dev_err(max77686->dev, "Failed to allocate register map: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 				ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	ret = regmap_read(max77686->regmap, MAX77686_REG_DEVICE_ID, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		dev_err(max77686->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 			"device not found on this channel (this is not an error)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	ret = devm_regmap_add_irq_chip(&i2c->dev, max77686->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 				       max77686->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 				       IRQF_TRIGGER_FALLING | IRQF_ONESHOT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 				       IRQF_SHARED, 0, irq_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 				       &max77686->irq_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		dev_err(&i2c->dev, "failed to add PMIC irq chip: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	ret = devm_mfd_add_devices(max77686->dev, -1, cells, n_devs, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 				   0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		dev_err(&i2c->dev, "failed to add MFD devices: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static int max77686_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	struct i2c_client *i2c = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	struct max77686_dev *max77686 = i2c_get_clientdata(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	if (device_may_wakeup(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		enable_irq_wake(max77686->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	 * IRQ must be disabled during suspend because if it happens
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	 * while suspended it will be handled before resuming I2C.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	 * When device is woken up from suspend (e.g. by RTC wake alarm),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	 * an interrupt occurs before resuming I2C bus controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	 * Interrupt handler tries to read registers but this read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	 * will fail because I2C is still suspended.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	disable_irq(max77686->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static int max77686_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	struct i2c_client *i2c = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	struct max77686_dev *max77686 = i2c_get_clientdata(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	if (device_may_wakeup(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		disable_irq_wake(max77686->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	enable_irq(max77686->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #endif /* CONFIG_PM_SLEEP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static SIMPLE_DEV_PM_OPS(max77686_pm, max77686_suspend, max77686_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static struct i2c_driver max77686_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		   .name = "max77686",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		   .pm = &max77686_pm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		   .of_match_table = of_match_ptr(max77686_pmic_dt_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	.probe_new = max77686_i2c_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) module_i2c_driver(max77686_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) MODULE_DESCRIPTION("MAXIM 77686/802 multi-function core driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) MODULE_AUTHOR("Chiwoong Byun <woong.byun@samsung.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) MODULE_LICENSE("GPL");