Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) // Copyright (C) 2018 BayLibre SAS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) // Author: Bartosz Golaszewski <bgolaszewski@baylibre.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) // Core MFD driver for MAXIM 77650/77651 charger/power-supply.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) // Programming manual: https://pdfserv.maximintegrated.com/en/an/AN6428.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/mfd/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/mfd/max77650.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define MAX77650_INT_GPI_F_MSK		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define MAX77650_INT_GPI_R_MSK		BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define MAX77650_INT_GPI_MSK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 			(MAX77650_INT_GPI_F_MSK | MAX77650_INT_GPI_R_MSK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define MAX77650_INT_nEN_F_MSK		BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define MAX77650_INT_nEN_R_MSK		BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define MAX77650_INT_TJAL1_R_MSK	BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define MAX77650_INT_TJAL2_R_MSK	BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define MAX77650_INT_DOD_R_MSK		BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define MAX77650_INT_THM_MSK		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define MAX77650_INT_CHG_MSK		BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define MAX77650_INT_CHGIN_MSK		BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define MAX77650_INT_TJ_REG_MSK		BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define MAX77650_INT_CHGIN_CTRL_MSK	BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define MAX77650_INT_SYS_CTRL_MSK	BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define MAX77650_INT_SYS_CNFG_MSK	BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define MAX77650_INT_GLBL_OFFSET	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define MAX77650_INT_CHG_OFFSET		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define MAX77650_SBIA_LPM_MASK		BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define MAX77650_SBIA_LPM_DISABLED	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	MAX77650_INT_GPI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	MAX77650_INT_nEN_F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	MAX77650_INT_nEN_R,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	MAX77650_INT_TJAL1_R,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	MAX77650_INT_TJAL2_R,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	MAX77650_INT_DOD_R,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	MAX77650_INT_THM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	MAX77650_INT_CHG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	MAX77650_INT_CHGIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	MAX77650_INT_TJ_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	MAX77650_INT_CHGIN_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	MAX77650_INT_SYS_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	MAX77650_INT_SYS_CNFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) static const struct resource max77650_charger_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	DEFINE_RES_IRQ_NAMED(MAX77650_INT_CHG, "CHG"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	DEFINE_RES_IRQ_NAMED(MAX77650_INT_CHGIN, "CHGIN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) static const struct resource max77650_gpio_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	DEFINE_RES_IRQ_NAMED(MAX77650_INT_GPI, "GPI"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) static const struct resource max77650_onkey_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	DEFINE_RES_IRQ_NAMED(MAX77650_INT_nEN_F, "nEN_F"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	DEFINE_RES_IRQ_NAMED(MAX77650_INT_nEN_R, "nEN_R"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) static const struct mfd_cell max77650_cells[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		.name		= "max77650-regulator",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		.of_compatible	= "maxim,max77650-regulator",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		.name		= "max77650-charger",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 		.of_compatible	= "maxim,max77650-charger",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 		.resources	= max77650_charger_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 		.num_resources	= ARRAY_SIZE(max77650_charger_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		.name		= "max77650-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		.of_compatible	= "maxim,max77650-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		.resources	= max77650_gpio_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		.num_resources	= ARRAY_SIZE(max77650_gpio_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 		.name		= "max77650-led",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		.of_compatible	= "maxim,max77650-led",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		.name		= "max77650-onkey",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		.of_compatible	= "maxim,max77650-onkey",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		.resources	= max77650_onkey_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		.num_resources	= ARRAY_SIZE(max77650_onkey_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) static const struct regmap_irq max77650_irqs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	[MAX77650_INT_GPI] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		.reg_offset = MAX77650_INT_GLBL_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		.mask = MAX77650_INT_GPI_MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		.type = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 			.type_falling_val = MAX77650_INT_GPI_F_MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 			.type_rising_val = MAX77650_INT_GPI_R_MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 			.types_supported = IRQ_TYPE_EDGE_BOTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	REGMAP_IRQ_REG(MAX77650_INT_nEN_F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		       MAX77650_INT_GLBL_OFFSET, MAX77650_INT_nEN_F_MSK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	REGMAP_IRQ_REG(MAX77650_INT_nEN_R,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		       MAX77650_INT_GLBL_OFFSET, MAX77650_INT_nEN_R_MSK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	REGMAP_IRQ_REG(MAX77650_INT_TJAL1_R,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		       MAX77650_INT_GLBL_OFFSET, MAX77650_INT_TJAL1_R_MSK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	REGMAP_IRQ_REG(MAX77650_INT_TJAL2_R,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		       MAX77650_INT_GLBL_OFFSET, MAX77650_INT_TJAL2_R_MSK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	REGMAP_IRQ_REG(MAX77650_INT_DOD_R,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		       MAX77650_INT_GLBL_OFFSET, MAX77650_INT_DOD_R_MSK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	REGMAP_IRQ_REG(MAX77650_INT_THM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		       MAX77650_INT_CHG_OFFSET, MAX77650_INT_THM_MSK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	REGMAP_IRQ_REG(MAX77650_INT_CHG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		       MAX77650_INT_CHG_OFFSET, MAX77650_INT_CHG_MSK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	REGMAP_IRQ_REG(MAX77650_INT_CHGIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		       MAX77650_INT_CHG_OFFSET, MAX77650_INT_CHGIN_MSK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	REGMAP_IRQ_REG(MAX77650_INT_TJ_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		       MAX77650_INT_CHG_OFFSET, MAX77650_INT_TJ_REG_MSK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	REGMAP_IRQ_REG(MAX77650_INT_CHGIN_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		       MAX77650_INT_CHG_OFFSET, MAX77650_INT_CHGIN_CTRL_MSK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	REGMAP_IRQ_REG(MAX77650_INT_SYS_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		       MAX77650_INT_CHG_OFFSET, MAX77650_INT_SYS_CTRL_MSK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	REGMAP_IRQ_REG(MAX77650_INT_SYS_CNFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		       MAX77650_INT_CHG_OFFSET, MAX77650_INT_SYS_CNFG_MSK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static const struct regmap_irq_chip max77650_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	.name			= "max77650-irq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	.irqs			= max77650_irqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	.num_irqs		= ARRAY_SIZE(max77650_irqs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	.num_regs		= 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	.status_base		= MAX77650_REG_INT_GLBL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	.mask_base		= MAX77650_REG_INTM_GLBL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	.type_in_mask		= true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	.type_invert		= true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	.init_ack_masked	= true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	.clear_on_unmask	= true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static const struct regmap_config max77650_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	.name		= "max77650",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	.reg_bits	= 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	.val_bits	= 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static int max77650_i2c_probe(struct i2c_client *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	struct regmap_irq_chip_data *irq_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	struct device *dev = &i2c->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	struct irq_domain *domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	struct regmap *map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	int rv, id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	map = devm_regmap_init_i2c(i2c, &max77650_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	if (IS_ERR(map)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		dev_err(dev, "Unable to initialise I2C Regmap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		return PTR_ERR(map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	rv = regmap_read(map, MAX77650_REG_CID, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	if (rv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		dev_err(dev, "Unable to read Chip ID\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		return rv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	id = MAX77650_CID_BITS(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	switch (id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	case MAX77650_CID_77650A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	case MAX77650_CID_77650C:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	case MAX77650_CID_77651A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	case MAX77650_CID_77651B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		dev_err(dev, "Chip not supported - ID: 0x%02x\n", id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	 * This IC has a low-power mode which reduces the quiescent current
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	 * consumption to ~5.6uA but is only suitable for systems consuming
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	 * less than ~2mA. Since this is not likely the case even on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	 * linux-based wearables - keep the chip in normal power mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	rv = regmap_update_bits(map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 				MAX77650_REG_CNFG_GLBL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 				MAX77650_SBIA_LPM_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 				MAX77650_SBIA_LPM_DISABLED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	if (rv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		dev_err(dev, "Unable to change the power mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		return rv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	rv = devm_regmap_add_irq_chip(dev, map, i2c->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 				      IRQF_ONESHOT | IRQF_SHARED, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 				      &max77650_irq_chip, &irq_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	if (rv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		dev_err(dev, "Unable to add Regmap IRQ chip\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		return rv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	domain = regmap_irq_get_domain(irq_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	return devm_mfd_add_devices(dev, PLATFORM_DEVID_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 				    max77650_cells, ARRAY_SIZE(max77650_cells),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 				    NULL, 0, domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static const struct of_device_id max77650_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	{ .compatible = "maxim,max77650" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) MODULE_DEVICE_TABLE(of, max77650_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static struct i2c_driver max77650_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		.name = "max77650",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		.of_match_table = of_match_ptr(max77650_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	.probe_new = max77650_i2c_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) module_i2c_driver(max77650_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) MODULE_DESCRIPTION("MAXIM 77650/77651 multi-function core driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) MODULE_AUTHOR("Bartosz Golaszewski <bgolaszewski@baylibre.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) MODULE_LICENSE("GPL v2");