^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Maxim MAX77620 MFD Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2016 NVIDIA CORPORATION. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Laxman Dewangan <ldewangan@nvidia.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Chaitanya Bandi <bandik@nvidia.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Mallikarjun Kasoju <mkasoju@nvidia.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /****************** Teminology used in driver ********************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Here are some terminology used from datasheet for quick reference:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * Flexible Power Sequence (FPS):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * The Flexible Power Sequencer (FPS) allows each regulator to power up under
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * hardware or software control. Additionally, each regulator can power on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * independently or among a group of other regulators with an adjustable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * power-up and power-down delays (sequencing). GPIO1, GPIO2, and GPIO3 can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * be programmed to be part of a sequence allowing external regulators to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * sequenced along with internal regulators. 32KHz clock can be programmed to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * be part of a sequence.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * There is 3 FPS confguration registers and all resources are configured to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * any of these FPS or no FPS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/mfd/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/mfd/max77620.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static struct max77620_chip *max77620_scratch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static const struct resource gpio_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) DEFINE_RES_IRQ(MAX77620_IRQ_TOP_GPIO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static const struct resource power_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) DEFINE_RES_IRQ(MAX77620_IRQ_LBT_MBATLOW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static const struct resource rtc_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) DEFINE_RES_IRQ(MAX77620_IRQ_TOP_RTC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static const struct resource thermal_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) DEFINE_RES_IRQ(MAX77620_IRQ_LBT_TJALRM1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) DEFINE_RES_IRQ(MAX77620_IRQ_LBT_TJALRM2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static const struct regmap_irq max77620_top_irqs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) REGMAP_IRQ_REG(MAX77620_IRQ_TOP_GLBL, 0, MAX77620_IRQ_TOP_GLBL_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) REGMAP_IRQ_REG(MAX77620_IRQ_TOP_SD, 0, MAX77620_IRQ_TOP_SD_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) REGMAP_IRQ_REG(MAX77620_IRQ_TOP_LDO, 0, MAX77620_IRQ_TOP_LDO_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) REGMAP_IRQ_REG(MAX77620_IRQ_TOP_GPIO, 0, MAX77620_IRQ_TOP_GPIO_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) REGMAP_IRQ_REG(MAX77620_IRQ_TOP_RTC, 0, MAX77620_IRQ_TOP_RTC_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) REGMAP_IRQ_REG(MAX77620_IRQ_TOP_32K, 0, MAX77620_IRQ_TOP_32K_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) REGMAP_IRQ_REG(MAX77620_IRQ_TOP_ONOFF, 0, MAX77620_IRQ_TOP_ONOFF_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) REGMAP_IRQ_REG(MAX77620_IRQ_LBT_MBATLOW, 1, MAX77620_IRQ_LBM_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) REGMAP_IRQ_REG(MAX77620_IRQ_LBT_TJALRM1, 1, MAX77620_IRQ_TJALRM1_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) REGMAP_IRQ_REG(MAX77620_IRQ_LBT_TJALRM2, 1, MAX77620_IRQ_TJALRM2_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static const struct mfd_cell max77620_children[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) { .name = "max77620-pinctrl", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) { .name = "max77620-clock", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) { .name = "max77620-pmic", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) { .name = "max77620-watchdog", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .name = "max77620-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .resources = gpio_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .num_resources = ARRAY_SIZE(gpio_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) .name = "max77620-rtc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .resources = rtc_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .num_resources = ARRAY_SIZE(rtc_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .name = "max77620-power",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .resources = power_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .num_resources = ARRAY_SIZE(power_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .name = "max77620-thermal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .resources = thermal_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .num_resources = ARRAY_SIZE(thermal_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static const struct mfd_cell max20024_children[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) { .name = "max20024-pinctrl", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) { .name = "max77620-clock", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) { .name = "max20024-pmic", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) { .name = "max77620-watchdog", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .name = "max77620-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .resources = gpio_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .num_resources = ARRAY_SIZE(gpio_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .name = "max77620-rtc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .resources = rtc_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .num_resources = ARRAY_SIZE(rtc_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .name = "max20024-power",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .resources = power_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .num_resources = ARRAY_SIZE(power_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static const struct mfd_cell max77663_children[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) { .name = "max77620-pinctrl", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) { .name = "max77620-clock", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) { .name = "max77663-pmic", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) { .name = "max77620-watchdog", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .name = "max77620-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .resources = gpio_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .num_resources = ARRAY_SIZE(gpio_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .name = "max77620-rtc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .resources = rtc_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .num_resources = ARRAY_SIZE(rtc_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .name = "max77663-power",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .resources = power_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .num_resources = ARRAY_SIZE(power_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static const struct regmap_range max77620_readable_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) regmap_reg_range(MAX77620_REG_CNFGGLBL1, MAX77620_REG_DVSSD4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static const struct regmap_access_table max77620_readable_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .yes_ranges = max77620_readable_ranges,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .n_yes_ranges = ARRAY_SIZE(max77620_readable_ranges),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static const struct regmap_range max20024_readable_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) regmap_reg_range(MAX77620_REG_CNFGGLBL1, MAX77620_REG_DVSSD4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) regmap_reg_range(MAX20024_REG_MAX_ADD, MAX20024_REG_MAX_ADD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static const struct regmap_access_table max20024_readable_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .yes_ranges = max20024_readable_ranges,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .n_yes_ranges = ARRAY_SIZE(max20024_readable_ranges),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static const struct regmap_range max77620_writable_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) regmap_reg_range(MAX77620_REG_CNFGGLBL1, MAX77620_REG_DVSSD4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static const struct regmap_access_table max77620_writable_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .yes_ranges = max77620_writable_ranges,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .n_yes_ranges = ARRAY_SIZE(max77620_writable_ranges),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static const struct regmap_range max77620_cacheable_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) regmap_reg_range(MAX77620_REG_SD0_CFG, MAX77620_REG_LDO_CFG3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) regmap_reg_range(MAX77620_REG_FPS_CFG0, MAX77620_REG_FPS_SD3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static const struct regmap_access_table max77620_volatile_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .no_ranges = max77620_cacheable_ranges,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .n_no_ranges = ARRAY_SIZE(max77620_cacheable_ranges),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static const struct regmap_config max77620_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .name = "power-slave",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .max_register = MAX77620_REG_DVSSD4 + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .cache_type = REGCACHE_RBTREE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .rd_table = &max77620_readable_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .wr_table = &max77620_writable_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .volatile_table = &max77620_volatile_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .use_single_write = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static const struct regmap_config max20024_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .name = "power-slave",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .max_register = MAX20024_REG_MAX_ADD + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .cache_type = REGCACHE_RBTREE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .rd_table = &max20024_readable_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .wr_table = &max77620_writable_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .volatile_table = &max77620_volatile_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static const struct regmap_range max77663_readable_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) regmap_reg_range(MAX77620_REG_CNFGGLBL1, MAX77620_REG_CID5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static const struct regmap_access_table max77663_readable_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .yes_ranges = max77663_readable_ranges,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .n_yes_ranges = ARRAY_SIZE(max77663_readable_ranges),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static const struct regmap_range max77663_writable_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) regmap_reg_range(MAX77620_REG_CNFGGLBL1, MAX77620_REG_CID5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static const struct regmap_access_table max77663_writable_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .yes_ranges = max77663_writable_ranges,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .n_yes_ranges = ARRAY_SIZE(max77663_writable_ranges),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static const struct regmap_config max77663_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .name = "power-slave",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .max_register = MAX77620_REG_CID5 + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .cache_type = REGCACHE_RBTREE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .rd_table = &max77663_readable_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .wr_table = &max77663_writable_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .volatile_table = &max77620_volatile_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * MAX77620 and MAX20024 has the following steps of the interrupt handling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * for TOP interrupts:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * 1. When interrupt occurs from PMIC, mask the PMIC interrupt by setting GLBLM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * 2. Read IRQTOP and service the interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * 3. Once all interrupts has been checked and serviced, the interrupt service
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * routine un-masks the hardware interrupt line by clearing GLBLM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static int max77620_irq_global_mask(void *irq_drv_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) struct max77620_chip *chip = irq_drv_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) ret = regmap_update_bits(chip->rmap, MAX77620_REG_INTENLBT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) MAX77620_GLBLM_MASK, MAX77620_GLBLM_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) dev_err(chip->dev, "Failed to set GLBLM: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static int max77620_irq_global_unmask(void *irq_drv_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) struct max77620_chip *chip = irq_drv_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) ret = regmap_update_bits(chip->rmap, MAX77620_REG_INTENLBT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) MAX77620_GLBLM_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) dev_err(chip->dev, "Failed to reset GLBLM: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static struct regmap_irq_chip max77620_top_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .name = "max77620-top",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .irqs = max77620_top_irqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .num_irqs = ARRAY_SIZE(max77620_top_irqs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .num_regs = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .status_base = MAX77620_REG_IRQTOP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .mask_base = MAX77620_REG_IRQTOPM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .handle_pre_irq = max77620_irq_global_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .handle_post_irq = max77620_irq_global_unmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /* max77620_get_fps_period_reg_value: Get FPS bit field value from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) * requested periods.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) * MAX77620 supports the FPS period of 40, 80, 160, 320, 540, 1280, 2560
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) * and 5120 microseconds. MAX20024 supports the FPS period of 20, 40, 80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * 160, 320, 540, 1280 and 2560 microseconds.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) * The FPS register has 3 bits field to set the FPS period as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) * bits max77620 max20024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) * 000 40 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) * 001 80 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) * :::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static int max77620_get_fps_period_reg_value(struct max77620_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) int tperiod)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) int fps_min_period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) switch (chip->chip_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) case MAX20024:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) fps_min_period = MAX20024_FPS_PERIOD_MIN_US;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) case MAX77620:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) fps_min_period = MAX77620_FPS_PERIOD_MIN_US;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) case MAX77663:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) fps_min_period = MAX20024_FPS_PERIOD_MIN_US;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) for (i = 0; i < 7; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) if (fps_min_period >= tperiod)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) fps_min_period *= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /* max77620_config_fps: Configure FPS configuration registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) * based on platform specific information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) static int max77620_config_fps(struct max77620_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) struct device_node *fps_np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) struct device *dev = chip->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) unsigned int mask = 0, config = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) u32 fps_max_period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) u32 param_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) int tperiod, fps_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) char fps_name[10];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) switch (chip->chip_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) case MAX20024:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) fps_max_period = MAX20024_FPS_PERIOD_MAX_US;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) case MAX77620:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) fps_max_period = MAX77620_FPS_PERIOD_MAX_US;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) case MAX77663:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) fps_max_period = MAX20024_FPS_PERIOD_MAX_US;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) for (fps_id = 0; fps_id < MAX77620_FPS_COUNT; fps_id++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) sprintf(fps_name, "fps%d", fps_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) if (of_node_name_eq(fps_np, fps_name))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) if (fps_id == MAX77620_FPS_COUNT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) dev_err(dev, "FPS node name %pOFn is not valid\n", fps_np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) ret = of_property_read_u32(fps_np, "maxim,shutdown-fps-time-period-us",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) ¶m_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) mask |= MAX77620_FPS_TIME_PERIOD_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) chip->shutdown_fps_period[fps_id] = min(param_val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) fps_max_period);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) tperiod = max77620_get_fps_period_reg_value(chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) chip->shutdown_fps_period[fps_id]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) config |= tperiod << MAX77620_FPS_TIME_PERIOD_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) ret = of_property_read_u32(fps_np, "maxim,suspend-fps-time-period-us",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) ¶m_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) chip->suspend_fps_period[fps_id] = min(param_val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) fps_max_period);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) ret = of_property_read_u32(fps_np, "maxim,fps-event-source",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) ¶m_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) if (param_val > 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) dev_err(dev, "FPS%d event-source invalid\n", fps_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) mask |= MAX77620_FPS_EN_SRC_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) config |= param_val << MAX77620_FPS_EN_SRC_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) if (param_val == 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) mask |= MAX77620_FPS_ENFPS_SW_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) config |= MAX77620_FPS_ENFPS_SW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) if (!chip->sleep_enable && !chip->enable_global_lpm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) ret = of_property_read_u32(fps_np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) "maxim,device-state-on-disabled-event",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) ¶m_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) if (param_val == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) chip->sleep_enable = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) else if (param_val == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) chip->enable_global_lpm = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) ret = regmap_update_bits(chip->rmap, MAX77620_REG_FPS_CFG0 + fps_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) mask, config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) dev_err(dev, "Failed to update FPS CFG: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) static int max77620_initialise_fps(struct max77620_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) struct device *dev = chip->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) struct device_node *fps_np, *fps_child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) u8 config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) int fps_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) for (fps_id = 0; fps_id < MAX77620_FPS_COUNT; fps_id++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) chip->shutdown_fps_period[fps_id] = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) chip->suspend_fps_period[fps_id] = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) fps_np = of_get_child_by_name(dev->of_node, "fps");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) if (!fps_np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) goto skip_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) for_each_child_of_node(fps_np, fps_child) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) ret = max77620_config_fps(chip, fps_child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) of_node_put(fps_child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) config = chip->enable_global_lpm ? MAX77620_ONOFFCNFG2_SLP_LPM_MSK : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) MAX77620_ONOFFCNFG2_SLP_LPM_MSK, config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) dev_err(dev, "Failed to update SLP_LPM: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) skip_fps:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) if (chip->chip_id == MAX77663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) /* Enable wake on EN0 pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) MAX77620_ONOFFCNFG2_WK_EN0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) MAX77620_ONOFFCNFG2_WK_EN0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) dev_err(dev, "Failed to update WK_EN0: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) /* For MAX20024, SLPEN will be POR reset if CLRSE is b11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) if ((chip->chip_id == MAX20024) && chip->sleep_enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) config = MAX77620_ONOFFCNFG1_SLPEN | MAX20024_ONOFFCNFG1_CLRSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) config, config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) dev_err(dev, "Failed to update SLPEN: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) static int max77620_read_es_version(struct max77620_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) u8 cid_val[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) for (i = MAX77620_REG_CID0; i <= MAX77620_REG_CID5; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) ret = regmap_read(chip->rmap, i, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) dev_err(chip->dev, "Failed to read CID: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) dev_dbg(chip->dev, "CID%d: 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) i - MAX77620_REG_CID0, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) cid_val[i - MAX77620_REG_CID0] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) /* CID4 is OTP Version and CID5 is ES version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) dev_info(chip->dev, "PMIC Version OTP:0x%02X and ES:0x%X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) cid_val[4], MAX77620_CID5_DIDM(cid_val[5]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) static void max77620_pm_power_off(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) struct max77620_chip *chip = max77620_scratch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) MAX77620_ONOFFCNFG1_SFT_RST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) MAX77620_ONOFFCNFG1_SFT_RST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) static int max77620_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) const struct regmap_config *rmap_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) struct max77620_chip *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) const struct mfd_cell *mfd_cells;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) int n_mfd_cells;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) bool pm_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) chip = devm_kzalloc(&client->dev, sizeof(*chip), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) if (!chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) i2c_set_clientdata(client, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) chip->dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) chip->chip_irq = client->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) chip->chip_id = (enum max77620_chip_id)id->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) switch (chip->chip_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) case MAX77620:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) mfd_cells = max77620_children;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) n_mfd_cells = ARRAY_SIZE(max77620_children);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) rmap_config = &max77620_regmap_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) case MAX20024:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) mfd_cells = max20024_children;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) n_mfd_cells = ARRAY_SIZE(max20024_children);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) rmap_config = &max20024_regmap_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) case MAX77663:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) mfd_cells = max77663_children;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) n_mfd_cells = ARRAY_SIZE(max77663_children);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) rmap_config = &max77663_regmap_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) dev_err(chip->dev, "ChipID is invalid %d\n", chip->chip_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) chip->rmap = devm_regmap_init_i2c(client, rmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) if (IS_ERR(chip->rmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) ret = PTR_ERR(chip->rmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) dev_err(chip->dev, "Failed to initialise regmap: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) ret = max77620_read_es_version(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) max77620_top_irq_chip.irq_drv_data = chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) ret = devm_regmap_add_irq_chip(chip->dev, chip->rmap, client->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) IRQF_ONESHOT | IRQF_SHARED, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) &max77620_top_irq_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) &chip->top_irq_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) dev_err(chip->dev, "Failed to add regmap irq: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) ret = max77620_initialise_fps(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) ret = devm_mfd_add_devices(chip->dev, PLATFORM_DEVID_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) mfd_cells, n_mfd_cells, NULL, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) regmap_irq_get_domain(chip->top_irq_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) dev_err(chip->dev, "Failed to add MFD children: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) pm_off = of_device_is_system_power_controller(client->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) if (pm_off && !pm_power_off) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) max77620_scratch = chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) pm_power_off = max77620_pm_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) static int max77620_set_fps_period(struct max77620_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) int fps_id, int time_period)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) int period = max77620_get_fps_period_reg_value(chip, time_period);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) ret = regmap_update_bits(chip->rmap, MAX77620_REG_FPS_CFG0 + fps_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) MAX77620_FPS_TIME_PERIOD_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) period << MAX77620_FPS_TIME_PERIOD_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) dev_err(chip->dev, "Failed to update FPS period: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) static int max77620_i2c_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) struct max77620_chip *chip = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) unsigned int config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) int fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) for (fps = 0; fps < MAX77620_FPS_COUNT; fps++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) if (chip->suspend_fps_period[fps] < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) ret = max77620_set_fps_period(chip, fps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) chip->suspend_fps_period[fps]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) * For MAX20024: No need to configure SLPEN on suspend as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) * it will be configured on Init.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) if (chip->chip_id == MAX20024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) config = (chip->sleep_enable) ? MAX77620_ONOFFCNFG1_SLPEN : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) MAX77620_ONOFFCNFG1_SLPEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) dev_err(dev, "Failed to configure sleep in suspend: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) if (chip->chip_id == MAX77663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) /* Disable WK_EN0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) MAX77620_ONOFFCNFG2_WK_EN0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) dev_err(dev, "Failed to configure WK_EN in suspend: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) disable_irq(client->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) static int max77620_i2c_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) struct max77620_chip *chip = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) int fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) for (fps = 0; fps < MAX77620_FPS_COUNT; fps++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) if (chip->shutdown_fps_period[fps] < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) ret = max77620_set_fps_period(chip, fps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) chip->shutdown_fps_period[fps]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) * For MAX20024: No need to configure WKEN0 on resume as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) * it is configured on Init.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) if (chip->chip_id == MAX20024 || chip->chip_id == MAX77663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) /* Enable WK_EN0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) MAX77620_ONOFFCNFG2_WK_EN0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) MAX77620_ONOFFCNFG2_WK_EN0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) dev_err(dev, "Failed to configure WK_EN0 n resume: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) enable_irq(client->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) static const struct i2c_device_id max77620_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) {"max77620", MAX77620},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) {"max20024", MAX20024},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) {"max77663", MAX77663},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) static const struct dev_pm_ops max77620_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) SET_SYSTEM_SLEEP_PM_OPS(max77620_i2c_suspend, max77620_i2c_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) static struct i2c_driver max77620_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) .name = "max77620",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) .pm = &max77620_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) .probe = max77620_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) .id_table = max77620_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) builtin_i2c_driver(max77620_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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