Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) // max14577.c - mfd core driver for the Maxim 14577/77836
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) // Copyright (C) 2014 Samsung Electronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) // Chanwoo Choi <cw00.choi@samsung.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) // Krzysztof Kozlowski <krzk@kernel.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) // This driver is based on max8997.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/mfd/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/mfd/max14577.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/mfd/max14577-private.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  * Table of valid charger currents for different Maxim chipsets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  * It is placed here because it is used by both charger and regulator driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) const struct maxim_charger_current maxim_charger_currents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	[MAXIM_DEVICE_TYPE_UNKNOWN] = { 0, 0, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	[MAXIM_DEVICE_TYPE_MAX14577] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 		.min		= MAX14577_CHARGER_CURRENT_LIMIT_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 		.high_start	= MAX14577_CHARGER_CURRENT_LIMIT_HIGH_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 		.high_step	= MAX14577_CHARGER_CURRENT_LIMIT_HIGH_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 		.max		= MAX14577_CHARGER_CURRENT_LIMIT_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	[MAXIM_DEVICE_TYPE_MAX77836] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 		.min		= MAX77836_CHARGER_CURRENT_LIMIT_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 		.high_start	= MAX77836_CHARGER_CURRENT_LIMIT_HIGH_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 		.high_step	= MAX77836_CHARGER_CURRENT_LIMIT_HIGH_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 		.max		= MAX77836_CHARGER_CURRENT_LIMIT_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) EXPORT_SYMBOL_GPL(maxim_charger_currents);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41)  * maxim_charger_calc_reg_current - Calculate register value for current
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42)  * @limits:	constraints for charger, matching the MBCICHWRC register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43)  * @min_ua:	minimal requested current, micro Amps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44)  * @max_ua:	maximum requested current, micro Amps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45)  * @dst:	destination to store calculated register value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47)  * Calculates the value of MBCICHWRC (Fast Battery Charge Current) register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48)  * for given current and stores it under pointed 'dst'. The stored value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49)  * combines low bit (MBCICHWRCL) and high bits (MBCICHWRCH). It is also
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50)  * properly shifted.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52)  * The calculated register value matches the current which:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53)  *  - is always between <limits.min, limits.max>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54)  *  - is always less or equal to max_ua;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55)  *  - is the highest possible value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56)  *  - may be lower than min_ua.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58)  * On success returns 0. On error returns -EINVAL (requested min/max current
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59)  * is outside of given charger limits) and 'dst' is not set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) int maxim_charger_calc_reg_current(const struct maxim_charger_current *limits,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 		unsigned int min_ua, unsigned int max_ua, u8 *dst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	unsigned int current_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	if (min_ua > max_ua)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	if (min_ua > limits->max || max_ua < limits->min)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	if (max_ua < limits->high_start) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		 * Less than high_start, so set the minimal current
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		 * (turn Low Bit off, 0 as high bits).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		*dst = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	/* max_ua is in range: <high_start, infinite>, cut it to limits.max */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	max_ua = min(limits->max, max_ua);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	max_ua -= limits->high_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	 * There is no risk of overflow 'max_ua' here because:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	 *  - max_ua >= limits.high_start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	 *  - BUILD_BUG checks that 'limits' are: max >= high_start + high_step
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	current_bits = max_ua / limits->high_step;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	/* Turn Low Bit on (use range <limits.high_start, limits.max>) ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	*dst = 0x1 << CHGCTRL4_MBCICHWRCL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	/* and set proper High Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	*dst |= current_bits << CHGCTRL4_MBCICHWRCH_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) EXPORT_SYMBOL_GPL(maxim_charger_calc_reg_current);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static const struct mfd_cell max14577_devs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		.name = "max14577-muic",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		.of_compatible = "maxim,max14577-muic",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		.name = "max14577-regulator",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		.of_compatible = "maxim,max14577-regulator",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		.name = "max14577-charger",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		.of_compatible = "maxim,max14577-charger",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static const struct mfd_cell max77836_devs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		.name = "max77836-muic",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		.of_compatible = "maxim,max77836-muic",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		.name = "max77836-regulator",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		.of_compatible = "maxim,max77836-regulator",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		.name = "max77836-charger",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		.of_compatible = "maxim,max77836-charger",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		.name = "max77836-battery",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		.of_compatible = "maxim,max77836-battery",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static const struct of_device_id max14577_dt_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		.compatible = "maxim,max14577",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		.data = (void *)MAXIM_DEVICE_TYPE_MAX14577,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		.compatible = "maxim,max77836",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		.data = (void *)MAXIM_DEVICE_TYPE_MAX77836,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static bool max14577_muic_volatile_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	case MAX14577_REG_INT1 ... MAX14577_REG_STATUS3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static bool max77836_muic_volatile_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	/* Any max14577 volatile registers are also max77836 volatile. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	if (max14577_muic_volatile_reg(dev, reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	case MAX77836_FG_REG_VCELL_MSB ... MAX77836_FG_REG_SOC_LSB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	case MAX77836_FG_REG_CRATE_MSB ... MAX77836_FG_REG_CRATE_LSB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	case MAX77836_FG_REG_STATUS_H ... MAX77836_FG_REG_STATUS_L:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	case MAX77836_PMIC_REG_INTSRC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	case MAX77836_PMIC_REG_TOPSYS_INT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	case MAX77836_PMIC_REG_TOPSYS_STAT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static const struct regmap_config max14577_muic_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	.reg_bits	= 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	.val_bits	= 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	.volatile_reg	= max14577_muic_volatile_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	.max_register	= MAX14577_REG_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static const struct regmap_config max77836_pmic_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	.reg_bits	= 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	.val_bits	= 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	.volatile_reg	= max77836_muic_volatile_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	.max_register	= MAX77836_PMIC_REG_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static const struct regmap_irq max14577_irqs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	/* INT1 interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	{ .reg_offset = 0, .mask = MAX14577_INT1_ADC_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	{ .reg_offset = 0, .mask = MAX14577_INT1_ADCLOW_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	{ .reg_offset = 0, .mask = MAX14577_INT1_ADCERR_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	/* INT2 interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	{ .reg_offset = 1, .mask = MAX14577_INT2_CHGTYP_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	{ .reg_offset = 1, .mask = MAX14577_INT2_CHGDETRUN_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	{ .reg_offset = 1, .mask = MAX14577_INT2_DCDTMR_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	{ .reg_offset = 1, .mask = MAX14577_INT2_DBCHG_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	{ .reg_offset = 1, .mask = MAX14577_INT2_VBVOLT_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	/* INT3 interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	{ .reg_offset = 2, .mask = MAX14577_INT3_EOC_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	{ .reg_offset = 2, .mask = MAX14577_INT3_CGMBC_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	{ .reg_offset = 2, .mask = MAX14577_INT3_OVP_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	{ .reg_offset = 2, .mask = MAX14577_INT3_MBCCHGERR_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static const struct regmap_irq_chip max14577_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	.name			= "max14577",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	.status_base		= MAX14577_REG_INT1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	.mask_base		= MAX14577_REG_INTMASK1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	.mask_invert		= true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	.num_regs		= 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	.irqs			= max14577_irqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	.num_irqs		= ARRAY_SIZE(max14577_irqs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static const struct regmap_irq max77836_muic_irqs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	/* INT1 interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	{ .reg_offset = 0, .mask = MAX14577_INT1_ADC_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	{ .reg_offset = 0, .mask = MAX14577_INT1_ADCLOW_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	{ .reg_offset = 0, .mask = MAX14577_INT1_ADCERR_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	{ .reg_offset = 0, .mask = MAX77836_INT1_ADC1K_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	/* INT2 interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	{ .reg_offset = 1, .mask = MAX14577_INT2_CHGTYP_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	{ .reg_offset = 1, .mask = MAX14577_INT2_CHGDETRUN_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	{ .reg_offset = 1, .mask = MAX14577_INT2_DCDTMR_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	{ .reg_offset = 1, .mask = MAX14577_INT2_DBCHG_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	{ .reg_offset = 1, .mask = MAX14577_INT2_VBVOLT_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	{ .reg_offset = 1, .mask = MAX77836_INT2_VIDRM_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	/* INT3 interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	{ .reg_offset = 2, .mask = MAX14577_INT3_EOC_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	{ .reg_offset = 2, .mask = MAX14577_INT3_CGMBC_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	{ .reg_offset = 2, .mask = MAX14577_INT3_OVP_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	{ .reg_offset = 2, .mask = MAX14577_INT3_MBCCHGERR_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static const struct regmap_irq_chip max77836_muic_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	.name			= "max77836-muic",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	.status_base		= MAX14577_REG_INT1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	.mask_base		= MAX14577_REG_INTMASK1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	.mask_invert		= true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	.num_regs		= 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	.irqs			= max77836_muic_irqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	.num_irqs		= ARRAY_SIZE(max77836_muic_irqs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static const struct regmap_irq max77836_pmic_irqs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	{ .reg_offset = 0, .mask = MAX77836_TOPSYS_INT_T120C_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	{ .reg_offset = 0, .mask = MAX77836_TOPSYS_INT_T140C_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) static const struct regmap_irq_chip max77836_pmic_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	.name			= "max77836-pmic",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	.status_base		= MAX77836_PMIC_REG_TOPSYS_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	.mask_base		= MAX77836_PMIC_REG_TOPSYS_INT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	.mask_invert		= false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	.num_regs		= 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	.irqs			= max77836_pmic_irqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	.num_irqs		= ARRAY_SIZE(max77836_pmic_irqs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static void max14577_print_dev_type(struct max14577 *max14577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	u8 reg_data, vendor_id, device_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	ret = max14577_read_reg(max14577->regmap, MAX14577_REG_DEVICEID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 			&reg_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		dev_err(max14577->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 			"Failed to read DEVICEID register: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	vendor_id = ((reg_data & DEVID_VENDORID_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 				DEVID_VENDORID_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	device_id = ((reg_data & DEVID_DEVICEID_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 				DEVID_DEVICEID_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	dev_info(max14577->dev, "Device type: %u (ID: 0x%x, vendor: 0x%x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 			max14577->dev_type, device_id, vendor_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)  * Max77836 specific initialization code for driver probe.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)  * Adds new I2C dummy device, regmap and regmap IRQ chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)  * Unmasks Interrupt Source register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)  * On success returns 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)  * On failure returns errno and reverts any changes done so far (e.g. remove
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)  * I2C dummy device), except masking the INT SRC register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static int max77836_init(struct max14577 *max14577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	u8 intsrc_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	max14577->i2c_pmic = i2c_new_dummy_device(max14577->i2c->adapter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 			I2C_ADDR_PMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	if (IS_ERR(max14577->i2c_pmic)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 		dev_err(max14577->dev, "Failed to register PMIC I2C device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 		return PTR_ERR(max14577->i2c_pmic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	i2c_set_clientdata(max14577->i2c_pmic, max14577);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	max14577->regmap_pmic = devm_regmap_init_i2c(max14577->i2c_pmic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 			&max77836_pmic_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	if (IS_ERR(max14577->regmap_pmic)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 		ret = PTR_ERR(max14577->regmap_pmic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 		dev_err(max14577->dev, "Failed to allocate PMIC register map: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 				ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	/* Un-mask MAX77836 Interrupt Source register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	ret = max14577_read_reg(max14577->regmap_pmic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 			MAX77836_PMIC_REG_INTSRC_MASK, &intsrc_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 		dev_err(max14577->dev, "Failed to read PMIC register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	intsrc_mask &= ~(MAX77836_INTSRC_MASK_TOP_INT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	intsrc_mask &= ~(MAX77836_INTSRC_MASK_MUIC_CHG_INT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	ret = max14577_write_reg(max14577->regmap_pmic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 			MAX77836_PMIC_REG_INTSRC_MASK, intsrc_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 		dev_err(max14577->dev, "Failed to write PMIC register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	ret = regmap_add_irq_chip(max14577->regmap_pmic, max14577->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 			IRQF_TRIGGER_FALLING | IRQF_ONESHOT | IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 			0, &max77836_pmic_irq_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 			&max14577->irq_data_pmic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 		dev_err(max14577->dev, "Failed to request PMIC IRQ %d: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 				max14577->irq, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	i2c_unregister_device(max14577->i2c_pmic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)  * Max77836 specific de-initialization code for driver remove.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static void max77836_remove(struct max14577 *max14577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	regmap_del_irq_chip(max14577->irq, max14577->irq_data_pmic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	i2c_unregister_device(max14577->i2c_pmic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static int max14577_i2c_probe(struct i2c_client *i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 			      const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	struct max14577 *max14577;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	struct max14577_platform_data *pdata = dev_get_platdata(&i2c->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	struct device_node *np = i2c->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	const struct regmap_irq_chip *irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	const struct mfd_cell *mfd_devs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	unsigned int mfd_devs_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	int irq_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	if (np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 		pdata = devm_kzalloc(&i2c->dev, sizeof(*pdata), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 		if (!pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 			return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 		i2c->dev.platform_data = pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	if (!pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 		dev_err(&i2c->dev, "No platform data found.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	max14577 = devm_kzalloc(&i2c->dev, sizeof(*max14577), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	if (!max14577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	i2c_set_clientdata(i2c, max14577);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	max14577->dev = &i2c->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	max14577->i2c = i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	max14577->irq = i2c->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	max14577->regmap = devm_regmap_init_i2c(i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 			&max14577_muic_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	if (IS_ERR(max14577->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 		ret = PTR_ERR(max14577->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 		dev_err(max14577->dev, "Failed to allocate register map: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 				ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	if (np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 		const struct of_device_id *of_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 		of_id = of_match_device(max14577_dt_match, &i2c->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 		if (of_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 			max14577->dev_type =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 				(enum maxim_device_type)of_id->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 		max14577->dev_type = id->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	max14577_print_dev_type(max14577);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 	switch (max14577->dev_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 	case MAXIM_DEVICE_TYPE_MAX77836:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 		irq_chip = &max77836_muic_irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 		mfd_devs = max77836_devs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 		mfd_devs_size = ARRAY_SIZE(max77836_devs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 		irq_flags = IRQF_TRIGGER_FALLING | IRQF_ONESHOT | IRQF_SHARED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 	case MAXIM_DEVICE_TYPE_MAX14577:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 		irq_chip = &max14577_irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 		mfd_devs = max14577_devs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 		mfd_devs_size = ARRAY_SIZE(max14577_devs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 		irq_flags = IRQF_TRIGGER_FALLING | IRQF_ONESHOT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 	ret = regmap_add_irq_chip(max14577->regmap, max14577->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 				  irq_flags, 0, irq_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 				  &max14577->irq_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 	if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 		dev_err(&i2c->dev, "Failed to request IRQ %d: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 				max14577->irq, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 	/* Max77836 specific initialization code (additional regmap) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 	if (max14577->dev_type == MAXIM_DEVICE_TYPE_MAX77836) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 		ret = max77836_init(max14577);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 			goto err_max77836;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 	ret = mfd_add_devices(max14577->dev, -1, mfd_devs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 			mfd_devs_size, NULL, 0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 		goto err_mfd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 	device_init_wakeup(max14577->dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) err_mfd:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 	if (max14577->dev_type == MAXIM_DEVICE_TYPE_MAX77836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 		max77836_remove(max14577);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) err_max77836:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 	regmap_del_irq_chip(max14577->irq, max14577->irq_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) static int max14577_i2c_remove(struct i2c_client *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 	struct max14577 *max14577 = i2c_get_clientdata(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 	mfd_remove_devices(max14577->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 	regmap_del_irq_chip(max14577->irq, max14577->irq_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 	if (max14577->dev_type == MAXIM_DEVICE_TYPE_MAX77836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 		max77836_remove(max14577);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) static const struct i2c_device_id max14577_i2c_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 	{ "max14577", MAXIM_DEVICE_TYPE_MAX14577, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 	{ "max77836", MAXIM_DEVICE_TYPE_MAX77836, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) MODULE_DEVICE_TABLE(i2c, max14577_i2c_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) static int max14577_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 	struct i2c_client *i2c = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) 	struct max14577 *max14577 = i2c_get_clientdata(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 	if (device_may_wakeup(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 		enable_irq_wake(max14577->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) 	 * MUIC IRQ must be disabled during suspend because if it happens
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) 	 * while suspended it will be handled before resuming I2C.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) 	 * When device is woken up from suspend (e.g. by ADC change),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) 	 * an interrupt occurs before resuming I2C bus controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) 	 * Interrupt handler tries to read registers but this read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) 	 * will fail because I2C is still suspended.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) 	disable_irq(max14577->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) static int max14577_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) 	struct i2c_client *i2c = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) 	struct max14577 *max14577 = i2c_get_clientdata(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) 	if (device_may_wakeup(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) 		disable_irq_wake(max14577->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) 	enable_irq(max14577->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) #endif /* CONFIG_PM_SLEEP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) static SIMPLE_DEV_PM_OPS(max14577_pm, max14577_suspend, max14577_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) static struct i2c_driver max14577_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) 		.name = "max14577",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) 		.pm = &max14577_pm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) 		.of_match_table = max14577_dt_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) 	.probe = max14577_i2c_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) 	.remove = max14577_i2c_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) 	.id_table = max14577_i2c_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) static int __init max14577_i2c_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) 	BUILD_BUG_ON(ARRAY_SIZE(max14577_i2c_id) != MAXIM_DEVICE_TYPE_NUM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) 	BUILD_BUG_ON(ARRAY_SIZE(max14577_dt_match) != MAXIM_DEVICE_TYPE_NUM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) 	/* Valid charger current values must be provided for each chipset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) 	BUILD_BUG_ON(ARRAY_SIZE(maxim_charger_currents) != MAXIM_DEVICE_TYPE_NUM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) 	/* Check for valid values for charger */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) 	BUILD_BUG_ON(MAX14577_CHARGER_CURRENT_LIMIT_HIGH_START +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) 			MAX14577_CHARGER_CURRENT_LIMIT_HIGH_STEP * 0xf !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) 			MAX14577_CHARGER_CURRENT_LIMIT_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) 	BUILD_BUG_ON(MAX14577_CHARGER_CURRENT_LIMIT_HIGH_STEP == 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) 	BUILD_BUG_ON(MAX77836_CHARGER_CURRENT_LIMIT_HIGH_START +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) 			MAX77836_CHARGER_CURRENT_LIMIT_HIGH_STEP * 0xf !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) 			MAX77836_CHARGER_CURRENT_LIMIT_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) 	BUILD_BUG_ON(MAX77836_CHARGER_CURRENT_LIMIT_HIGH_STEP == 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) 	return i2c_add_driver(&max14577_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) module_init(max14577_i2c_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) static void __exit max14577_i2c_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) 	i2c_del_driver(&max14577_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) module_exit(max14577_i2c_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) MODULE_AUTHOR("Chanwoo Choi <cw00.choi@samsung.com>, Krzysztof Kozlowski <krzk@kernel.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) MODULE_DESCRIPTION("Maxim 14577/77836 multi-function core driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) MODULE_LICENSE("GPL");