^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * lpc_sch.c - LPC interface for Intel Poulsbo SCH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * LPC bridge function of the Intel SCH contains many other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * functional units, such as Interrupt controllers, Timers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Power Management, System Management, GPIO, RTC, and LPC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Configuration Registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Copyright (c) 2010 CompuLab Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Copyright (c) 2014 Intel Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Author: Denis Turischev <denis@compulab.co.il>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/mfd/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SMBASE 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SMBUS_IO_SIZE 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define GPIO_BASE 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define GPIO_IO_SIZE 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define GPIO_IO_SIZE_CENTERTON 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define WDTBASE 0x84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define WDT_IO_SIZE 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) enum sch_chipsets {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) LPC_SCH = 0, /* Intel Poulsbo SCH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) LPC_ITC, /* Intel Tunnel Creek */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) LPC_CENTERTON, /* Intel Centerton */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) LPC_QUARK_X1000, /* Intel Quark X1000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct lpc_sch_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) unsigned int io_size_smbus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) unsigned int io_size_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) unsigned int io_size_wdt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static struct lpc_sch_info sch_chipset_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) [LPC_SCH] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) .io_size_smbus = SMBUS_IO_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) .io_size_gpio = GPIO_IO_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) [LPC_ITC] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .io_size_smbus = SMBUS_IO_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) .io_size_gpio = GPIO_IO_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) .io_size_wdt = WDT_IO_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) [LPC_CENTERTON] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) .io_size_smbus = SMBUS_IO_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .io_size_gpio = GPIO_IO_SIZE_CENTERTON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .io_size_wdt = WDT_IO_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) [LPC_QUARK_X1000] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .io_size_gpio = GPIO_IO_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .io_size_wdt = WDT_IO_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static const struct pci_device_id lpc_sch_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SCH_LPC), LPC_SCH },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ITC_LPC), LPC_ITC },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CENTERTON_ILB), LPC_CENTERTON },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_QUARK_X1000_ILB), LPC_QUARK_X1000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) { 0, }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) MODULE_DEVICE_TABLE(pci, lpc_sch_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define LPC_NO_RESOURCE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define LPC_SKIP_RESOURCE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static int lpc_sch_get_io(struct pci_dev *pdev, int where, const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct resource *res, int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) unsigned int base_addr_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) unsigned short base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) if (size == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) return LPC_NO_RESOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) pci_read_config_dword(pdev, where, &base_addr_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) base_addr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) if (!(base_addr_cfg & (1 << 31)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) dev_warn(&pdev->dev, "Decode of the %s I/O range disabled\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) base_addr = (unsigned short)base_addr_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) if (base_addr == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) dev_warn(&pdev->dev, "I/O space for %s uninitialized\n", name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) return LPC_SKIP_RESOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) res->start = base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) res->end = base_addr + size - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) res->flags = IORESOURCE_IO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static int lpc_sch_populate_cell(struct pci_dev *pdev, int where,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) const char *name, int size, int id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct mfd_cell *cell)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) res = devm_kzalloc(&pdev->dev, sizeof(*res), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) if (!res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) ret = lpc_sch_get_io(pdev, where, name, res, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) memset(cell, 0, sizeof(*cell));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) cell->name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) cell->resources = res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) cell->num_resources = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) cell->ignore_resource_conflicts = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) cell->id = id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static int lpc_sch_probe(struct pci_dev *dev, const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct mfd_cell lpc_sch_cells[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct lpc_sch_info *info = &sch_chipset_info[id->driver_data];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) unsigned int cells = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) ret = lpc_sch_populate_cell(dev, SMBASE, "isch_smbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) info->io_size_smbus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) id->device, &lpc_sch_cells[cells]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) cells++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) ret = lpc_sch_populate_cell(dev, GPIO_BASE, "sch_gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) info->io_size_gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) id->device, &lpc_sch_cells[cells]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) cells++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) ret = lpc_sch_populate_cell(dev, WDTBASE, "ie6xx_wdt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) info->io_size_wdt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) id->device, &lpc_sch_cells[cells]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) cells++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) if (cells == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) dev_err(&dev->dev, "All decode registers disabled.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) return mfd_add_devices(&dev->dev, 0, lpc_sch_cells, cells, NULL, 0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static void lpc_sch_remove(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) mfd_remove_devices(&dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static struct pci_driver lpc_sch_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .name = "lpc_sch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .id_table = lpc_sch_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .probe = lpc_sch_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .remove = lpc_sch_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) module_pci_driver(lpc_sch_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) MODULE_AUTHOR("Denis Turischev <denis@compulab.co.il>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) MODULE_DESCRIPTION("LPC interface for Intel Poulsbo SCH");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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