^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * lpc_ich.c - LPC interface for Intel ICH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * LPC bridge function of the Intel ICH contains many other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * functional units, such as Interrupt controllers, Timers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Power Management, System Management, GPIO, RTC, and LPC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Configuration Registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * This driver is derived from lpc_sch.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Copyright (c) 2011 Extreme Engineering Solution, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Author: Aaron Sierra <asierra@xes-inc.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * This driver supports the following I/O Controller hubs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * (See the intel documentation on http://developer.intel.com.)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * document number 290655-003, 290677-014: 82801AA (ICH), 82801AB (ICHO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * document number 290687-002, 298242-027: 82801BA (ICH2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * document number 290733-003, 290739-013: 82801CA (ICH3-S)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * document number 290716-001, 290718-007: 82801CAM (ICH3-M)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * document number 290744-001, 290745-025: 82801DB (ICH4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * document number 252337-001, 252663-008: 82801DBM (ICH4-M)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * document number 273599-001, 273645-002: 82801E (C-ICH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * document number 252516-001, 252517-028: 82801EB (ICH5), 82801ER (ICH5R)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * document number 300641-004, 300884-013: 6300ESB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * document number 301473-002, 301474-026: 82801F (ICH6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * document number 313082-001, 313075-006: 631xESB, 632xESB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * document number 307013-003, 307014-024: 82801G (ICH7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * document number 322896-001, 322897-001: NM10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * document number 313056-003, 313057-017: 82801H (ICH8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * document number 316972-004, 316973-012: 82801I (ICH9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * document number 319973-002, 319974-002: 82801J (ICH10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * document number 322169-001, 322170-003: 5 Series, 3400 Series (PCH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * document number 320066-003, 320257-008: EP80597 (IICH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * document number 324645-001, 324646-001: Cougar Point (CPT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include <linux/mfd/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #include <linux/mfd/lpc_ich.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #include <linux/platform_data/itco_wdt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define ACPIBASE 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define ACPIBASE_GPE_OFF 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define ACPIBASE_GPE_END 0x2f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define ACPIBASE_SMI_OFF 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define ACPIBASE_SMI_END 0x33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define ACPIBASE_PMC_OFF 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define ACPIBASE_PMC_END 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define ACPIBASE_TCO_OFF 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define ACPIBASE_TCO_END 0x7f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define ACPICTRL_PMCBASE 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define ACPIBASE_GCS_OFF 0x3410
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define ACPIBASE_GCS_END 0x3414
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SPIBASE_BYT 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SPIBASE_BYT_SZ 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SPIBASE_BYT_EN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SPIBASE_LPT 0x3800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SPIBASE_LPT_SZ 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define BCR 0xdc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define BCR_WPD BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SPIBASE_APL_SZ 4096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define GPIOBASE_ICH0 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define GPIOCTRL_ICH0 0x5C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define GPIOBASE_ICH6 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define GPIOCTRL_ICH6 0x4C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define RCBABASE 0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define wdt_io_res(i) wdt_res(0, i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define wdt_mem_res(i) wdt_res(ICH_RES_MEM_OFF, i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define wdt_res(b, i) (&wdt_ich_res[(b) + (i)])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct lpc_ich_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) int chipset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) int abase; /* ACPI base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) int actrl_pbase; /* ACPI control or PMC base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) int gbase; /* GPIO base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) int gctrl; /* GPIO control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) int abase_save; /* Cached ACPI base value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) int actrl_pbase_save; /* Cached ACPI control or PMC base value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) int gctrl_save; /* Cached GPIO control value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static struct resource wdt_ich_res[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* ACPI - TCO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .flags = IORESOURCE_IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* ACPI - SMI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .flags = IORESOURCE_IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* GCS or PMC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static struct resource gpio_ich_res[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* GPIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .flags = IORESOURCE_IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* ACPI - GPE0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .flags = IORESOURCE_IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static struct resource intel_spi_res[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static struct mfd_cell lpc_ich_wdt_cell = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .name = "iTCO_wdt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .num_resources = ARRAY_SIZE(wdt_ich_res),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .resources = wdt_ich_res,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .ignore_resource_conflicts = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static struct mfd_cell lpc_ich_gpio_cell = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .name = "gpio_ich",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .num_resources = ARRAY_SIZE(gpio_ich_res),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .resources = gpio_ich_res,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .ignore_resource_conflicts = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static struct mfd_cell lpc_ich_spi_cell = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .name = "intel-spi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .num_resources = ARRAY_SIZE(intel_spi_res),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .resources = intel_spi_res,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .ignore_resource_conflicts = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* chipset related info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) enum lpc_chipsets {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) LPC_ICH = 0, /* ICH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) LPC_ICH0, /* ICH0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) LPC_ICH2, /* ICH2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) LPC_ICH2M, /* ICH2-M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) LPC_ICH3, /* ICH3-S */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) LPC_ICH3M, /* ICH3-M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) LPC_ICH4, /* ICH4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) LPC_ICH4M, /* ICH4-M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) LPC_CICH, /* C-ICH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) LPC_ICH5, /* ICH5 & ICH5R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) LPC_6300ESB, /* 6300ESB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) LPC_ICH6, /* ICH6 & ICH6R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) LPC_ICH6M, /* ICH6-M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) LPC_ICH6W, /* ICH6W & ICH6RW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) LPC_631XESB, /* 631xESB/632xESB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) LPC_ICH7, /* ICH7 & ICH7R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) LPC_ICH7DH, /* ICH7DH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) LPC_ICH7M, /* ICH7-M & ICH7-U */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) LPC_ICH7MDH, /* ICH7-M DH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) LPC_NM10, /* NM10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) LPC_ICH8, /* ICH8 & ICH8R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) LPC_ICH8DH, /* ICH8DH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) LPC_ICH8DO, /* ICH8DO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) LPC_ICH8M, /* ICH8M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) LPC_ICH8ME, /* ICH8M-E */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) LPC_ICH9, /* ICH9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) LPC_ICH9R, /* ICH9R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) LPC_ICH9DH, /* ICH9DH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) LPC_ICH9DO, /* ICH9DO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) LPC_ICH9M, /* ICH9M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) LPC_ICH9ME, /* ICH9M-E */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) LPC_ICH10, /* ICH10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) LPC_ICH10R, /* ICH10R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) LPC_ICH10D, /* ICH10D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) LPC_ICH10DO, /* ICH10DO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) LPC_PCH, /* PCH Desktop Full Featured */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) LPC_PCHM, /* PCH Mobile Full Featured */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) LPC_P55, /* P55 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) LPC_PM55, /* PM55 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) LPC_H55, /* H55 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) LPC_QM57, /* QM57 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) LPC_H57, /* H57 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) LPC_HM55, /* HM55 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) LPC_Q57, /* Q57 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) LPC_HM57, /* HM57 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) LPC_PCHMSFF, /* PCH Mobile SFF Full Featured */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) LPC_QS57, /* QS57 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) LPC_3400, /* 3400 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) LPC_3420, /* 3420 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) LPC_3450, /* 3450 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) LPC_EP80579, /* EP80579 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) LPC_CPT, /* Cougar Point */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) LPC_CPTD, /* Cougar Point Desktop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) LPC_CPTM, /* Cougar Point Mobile */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) LPC_PBG, /* Patsburg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) LPC_DH89XXCC, /* DH89xxCC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) LPC_PPT, /* Panther Point */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) LPC_LPT, /* Lynx Point */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) LPC_LPT_LP, /* Lynx Point-LP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) LPC_WBG, /* Wellsburg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) LPC_AVN, /* Avoton SoC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) LPC_BAYTRAIL, /* Bay Trail SoC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) LPC_COLETO, /* Coleto Creek */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) LPC_WPT_LP, /* Wildcat Point-LP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) LPC_BRASWELL, /* Braswell SoC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) LPC_LEWISBURG, /* Lewisburg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) LPC_9S, /* 9 Series */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) LPC_APL, /* Apollo Lake SoC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) LPC_GLK, /* Gemini Lake SoC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) LPC_COUGARMOUNTAIN,/* Cougar Mountain SoC*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static struct lpc_ich_info lpc_chipset_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) [LPC_ICH] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) .name = "ICH",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .iTCO_version = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) [LPC_ICH0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .name = "ICH0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .iTCO_version = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) [LPC_ICH2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .name = "ICH2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .iTCO_version = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) [LPC_ICH2M] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .name = "ICH2-M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .iTCO_version = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) [LPC_ICH3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .name = "ICH3-S",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .iTCO_version = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) [LPC_ICH3M] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .name = "ICH3-M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .iTCO_version = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) [LPC_ICH4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .name = "ICH4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .iTCO_version = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) [LPC_ICH4M] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .name = "ICH4-M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .iTCO_version = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) [LPC_CICH] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .name = "C-ICH",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .iTCO_version = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) [LPC_ICH5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .name = "ICH5 or ICH5R",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .iTCO_version = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) [LPC_6300ESB] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .name = "6300ESB",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .iTCO_version = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) [LPC_ICH6] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .name = "ICH6 or ICH6R",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .iTCO_version = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .gpio_version = ICH_V6_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) [LPC_ICH6M] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .name = "ICH6-M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .iTCO_version = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .gpio_version = ICH_V6_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) [LPC_ICH6W] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) .name = "ICH6W or ICH6RW",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .iTCO_version = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .gpio_version = ICH_V6_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) [LPC_631XESB] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .name = "631xESB/632xESB",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .iTCO_version = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .gpio_version = ICH_V6_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) [LPC_ICH7] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .name = "ICH7 or ICH7R",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .iTCO_version = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .gpio_version = ICH_V7_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) [LPC_ICH7DH] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .name = "ICH7DH",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .iTCO_version = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .gpio_version = ICH_V7_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) [LPC_ICH7M] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .name = "ICH7-M or ICH7-U",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .iTCO_version = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .gpio_version = ICH_V7_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) [LPC_ICH7MDH] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .name = "ICH7-M DH",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .iTCO_version = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .gpio_version = ICH_V7_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) [LPC_NM10] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) .name = "NM10",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .iTCO_version = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .gpio_version = ICH_V7_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) [LPC_ICH8] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) .name = "ICH8 or ICH8R",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .iTCO_version = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) .gpio_version = ICH_V7_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) [LPC_ICH8DH] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .name = "ICH8DH",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .iTCO_version = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .gpio_version = ICH_V7_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) [LPC_ICH8DO] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .name = "ICH8DO",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .iTCO_version = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .gpio_version = ICH_V7_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) [LPC_ICH8M] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .name = "ICH8M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .iTCO_version = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .gpio_version = ICH_V7_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) [LPC_ICH8ME] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .name = "ICH8M-E",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .iTCO_version = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) .gpio_version = ICH_V7_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) [LPC_ICH9] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .name = "ICH9",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .iTCO_version = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) .gpio_version = ICH_V9_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) [LPC_ICH9R] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) .name = "ICH9R",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) .iTCO_version = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) .gpio_version = ICH_V9_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) [LPC_ICH9DH] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) .name = "ICH9DH",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) .iTCO_version = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) .gpio_version = ICH_V9_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) [LPC_ICH9DO] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .name = "ICH9DO",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .iTCO_version = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .gpio_version = ICH_V9_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) [LPC_ICH9M] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) .name = "ICH9M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) .iTCO_version = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .gpio_version = ICH_V9_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) [LPC_ICH9ME] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .name = "ICH9M-E",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .iTCO_version = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .gpio_version = ICH_V9_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) [LPC_ICH10] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .name = "ICH10",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .iTCO_version = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .gpio_version = ICH_V10CONS_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) [LPC_ICH10R] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .name = "ICH10R",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .iTCO_version = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .gpio_version = ICH_V10CONS_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) [LPC_ICH10D] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .name = "ICH10D",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .iTCO_version = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .gpio_version = ICH_V10CORP_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) [LPC_ICH10DO] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .name = "ICH10DO",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .iTCO_version = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .gpio_version = ICH_V10CORP_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) [LPC_PCH] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) .name = "PCH Desktop Full Featured",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) .iTCO_version = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .gpio_version = ICH_V5_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) [LPC_PCHM] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .name = "PCH Mobile Full Featured",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .iTCO_version = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .gpio_version = ICH_V5_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) [LPC_P55] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .name = "P55",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .iTCO_version = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .gpio_version = ICH_V5_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) [LPC_PM55] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) .name = "PM55",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) .iTCO_version = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) .gpio_version = ICH_V5_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) [LPC_H55] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) .name = "H55",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) .iTCO_version = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) .gpio_version = ICH_V5_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) [LPC_QM57] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) .name = "QM57",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) .iTCO_version = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) .gpio_version = ICH_V5_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) [LPC_H57] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) .name = "H57",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) .iTCO_version = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .gpio_version = ICH_V5_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) [LPC_HM55] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) .name = "HM55",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) .iTCO_version = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .gpio_version = ICH_V5_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) [LPC_Q57] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) .name = "Q57",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) .iTCO_version = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .gpio_version = ICH_V5_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) [LPC_HM57] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .name = "HM57",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) .iTCO_version = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) .gpio_version = ICH_V5_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) [LPC_PCHMSFF] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) .name = "PCH Mobile SFF Full Featured",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) .iTCO_version = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) .gpio_version = ICH_V5_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) [LPC_QS57] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) .name = "QS57",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) .iTCO_version = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) .gpio_version = ICH_V5_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) [LPC_3400] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) .name = "3400",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) .iTCO_version = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) .gpio_version = ICH_V5_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) [LPC_3420] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) .name = "3420",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) .iTCO_version = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) .gpio_version = ICH_V5_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) [LPC_3450] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) .name = "3450",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) .iTCO_version = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) .gpio_version = ICH_V5_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) [LPC_EP80579] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) .name = "EP80579",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) .iTCO_version = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) [LPC_CPT] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) .name = "Cougar Point",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) .iTCO_version = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) .gpio_version = ICH_V5_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) [LPC_CPTD] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) .name = "Cougar Point Desktop",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) .iTCO_version = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) .gpio_version = ICH_V5_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) [LPC_CPTM] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) .name = "Cougar Point Mobile",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) .iTCO_version = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) .gpio_version = ICH_V5_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) [LPC_PBG] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) .name = "Patsburg",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) .iTCO_version = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) [LPC_DH89XXCC] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) .name = "DH89xxCC",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) .iTCO_version = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) [LPC_PPT] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) .name = "Panther Point",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) .iTCO_version = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) .gpio_version = ICH_V5_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) [LPC_LPT] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) .name = "Lynx Point",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) .iTCO_version = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) .gpio_version = ICH_V5_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) .spi_type = INTEL_SPI_LPT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) [LPC_LPT_LP] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) .name = "Lynx Point_LP",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) .iTCO_version = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) .spi_type = INTEL_SPI_LPT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) [LPC_WBG] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) .name = "Wellsburg",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) .iTCO_version = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) [LPC_AVN] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) .name = "Avoton SoC",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) .iTCO_version = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) .gpio_version = AVOTON_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) .spi_type = INTEL_SPI_BYT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) [LPC_BAYTRAIL] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) .name = "Bay Trail SoC",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) .iTCO_version = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) .spi_type = INTEL_SPI_BYT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) [LPC_COLETO] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) .name = "Coleto Creek",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) .iTCO_version = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) [LPC_WPT_LP] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) .name = "Wildcat Point_LP",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) .iTCO_version = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) .spi_type = INTEL_SPI_LPT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) [LPC_BRASWELL] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) .name = "Braswell SoC",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) .iTCO_version = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) .spi_type = INTEL_SPI_BYT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) [LPC_LEWISBURG] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) .name = "Lewisburg",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) .iTCO_version = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) [LPC_9S] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) .name = "9 Series",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) .iTCO_version = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) .gpio_version = ICH_V5_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) [LPC_APL] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) .name = "Apollo Lake SoC",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) .iTCO_version = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) .spi_type = INTEL_SPI_BXT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) [LPC_GLK] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) .name = "Gemini Lake SoC",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) .spi_type = INTEL_SPI_BXT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) [LPC_COUGARMOUNTAIN] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) .name = "Cougar Mountain SoC",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) .iTCO_version = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) * This data only exists for exporting the supported PCI ids
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) * via MODULE_DEVICE_TABLE. We do not actually register a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) * pci_driver, because the I/O Controller Hub has also other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) * functions that probably will be registered by other drivers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) static const struct pci_device_id lpc_ich_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) { PCI_VDEVICE(INTEL, 0x0f1c), LPC_BAYTRAIL},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) { PCI_VDEVICE(INTEL, 0x1c41), LPC_CPT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) { PCI_VDEVICE(INTEL, 0x1c42), LPC_CPTD},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) { PCI_VDEVICE(INTEL, 0x1c43), LPC_CPTM},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) { PCI_VDEVICE(INTEL, 0x1c44), LPC_CPT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) { PCI_VDEVICE(INTEL, 0x1c45), LPC_CPT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) { PCI_VDEVICE(INTEL, 0x1c46), LPC_CPT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) { PCI_VDEVICE(INTEL, 0x1c47), LPC_CPT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) { PCI_VDEVICE(INTEL, 0x1c48), LPC_CPT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) { PCI_VDEVICE(INTEL, 0x1c49), LPC_CPT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) { PCI_VDEVICE(INTEL, 0x1c4a), LPC_CPT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) { PCI_VDEVICE(INTEL, 0x1c4b), LPC_CPT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) { PCI_VDEVICE(INTEL, 0x1c4c), LPC_CPT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) { PCI_VDEVICE(INTEL, 0x1c4d), LPC_CPT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) { PCI_VDEVICE(INTEL, 0x1c4e), LPC_CPT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) { PCI_VDEVICE(INTEL, 0x1c4f), LPC_CPT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) { PCI_VDEVICE(INTEL, 0x1c50), LPC_CPT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) { PCI_VDEVICE(INTEL, 0x1c51), LPC_CPT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) { PCI_VDEVICE(INTEL, 0x1c52), LPC_CPT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) { PCI_VDEVICE(INTEL, 0x1c53), LPC_CPT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) { PCI_VDEVICE(INTEL, 0x1c54), LPC_CPT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) { PCI_VDEVICE(INTEL, 0x1c55), LPC_CPT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) { PCI_VDEVICE(INTEL, 0x1c56), LPC_CPT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) { PCI_VDEVICE(INTEL, 0x1c57), LPC_CPT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) { PCI_VDEVICE(INTEL, 0x1c58), LPC_CPT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) { PCI_VDEVICE(INTEL, 0x1c59), LPC_CPT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) { PCI_VDEVICE(INTEL, 0x1c5a), LPC_CPT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) { PCI_VDEVICE(INTEL, 0x1c5b), LPC_CPT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) { PCI_VDEVICE(INTEL, 0x1c5c), LPC_CPT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) { PCI_VDEVICE(INTEL, 0x1c5d), LPC_CPT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) { PCI_VDEVICE(INTEL, 0x1c5e), LPC_CPT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) { PCI_VDEVICE(INTEL, 0x1c5f), LPC_CPT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) { PCI_VDEVICE(INTEL, 0x1d40), LPC_PBG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) { PCI_VDEVICE(INTEL, 0x1d41), LPC_PBG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) { PCI_VDEVICE(INTEL, 0x1e40), LPC_PPT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) { PCI_VDEVICE(INTEL, 0x1e41), LPC_PPT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) { PCI_VDEVICE(INTEL, 0x1e42), LPC_PPT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) { PCI_VDEVICE(INTEL, 0x1e43), LPC_PPT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) { PCI_VDEVICE(INTEL, 0x1e44), LPC_PPT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) { PCI_VDEVICE(INTEL, 0x1e45), LPC_PPT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) { PCI_VDEVICE(INTEL, 0x1e46), LPC_PPT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) { PCI_VDEVICE(INTEL, 0x1e47), LPC_PPT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) { PCI_VDEVICE(INTEL, 0x1e48), LPC_PPT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) { PCI_VDEVICE(INTEL, 0x1e49), LPC_PPT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) { PCI_VDEVICE(INTEL, 0x1e4a), LPC_PPT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) { PCI_VDEVICE(INTEL, 0x1e4b), LPC_PPT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) { PCI_VDEVICE(INTEL, 0x1e4c), LPC_PPT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) { PCI_VDEVICE(INTEL, 0x1e4d), LPC_PPT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) { PCI_VDEVICE(INTEL, 0x1e4e), LPC_PPT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) { PCI_VDEVICE(INTEL, 0x1e4f), LPC_PPT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) { PCI_VDEVICE(INTEL, 0x1e50), LPC_PPT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) { PCI_VDEVICE(INTEL, 0x1e51), LPC_PPT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) { PCI_VDEVICE(INTEL, 0x1e52), LPC_PPT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) { PCI_VDEVICE(INTEL, 0x1e53), LPC_PPT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) { PCI_VDEVICE(INTEL, 0x1e54), LPC_PPT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) { PCI_VDEVICE(INTEL, 0x1e55), LPC_PPT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) { PCI_VDEVICE(INTEL, 0x1e56), LPC_PPT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) { PCI_VDEVICE(INTEL, 0x1e57), LPC_PPT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) { PCI_VDEVICE(INTEL, 0x1e58), LPC_PPT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) { PCI_VDEVICE(INTEL, 0x1e59), LPC_PPT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) { PCI_VDEVICE(INTEL, 0x1e5a), LPC_PPT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) { PCI_VDEVICE(INTEL, 0x1e5b), LPC_PPT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) { PCI_VDEVICE(INTEL, 0x1e5c), LPC_PPT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) { PCI_VDEVICE(INTEL, 0x1e5d), LPC_PPT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) { PCI_VDEVICE(INTEL, 0x1e5e), LPC_PPT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) { PCI_VDEVICE(INTEL, 0x1e5f), LPC_PPT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) { PCI_VDEVICE(INTEL, 0x1f38), LPC_AVN},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) { PCI_VDEVICE(INTEL, 0x1f39), LPC_AVN},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) { PCI_VDEVICE(INTEL, 0x1f3a), LPC_AVN},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) { PCI_VDEVICE(INTEL, 0x1f3b), LPC_AVN},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) { PCI_VDEVICE(INTEL, 0x229c), LPC_BRASWELL},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) { PCI_VDEVICE(INTEL, 0x2310), LPC_DH89XXCC},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) { PCI_VDEVICE(INTEL, 0x2390), LPC_COLETO},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) { PCI_VDEVICE(INTEL, 0x2410), LPC_ICH},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) { PCI_VDEVICE(INTEL, 0x2420), LPC_ICH0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) { PCI_VDEVICE(INTEL, 0x2440), LPC_ICH2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) { PCI_VDEVICE(INTEL, 0x244c), LPC_ICH2M},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) { PCI_VDEVICE(INTEL, 0x2450), LPC_CICH},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) { PCI_VDEVICE(INTEL, 0x2480), LPC_ICH3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) { PCI_VDEVICE(INTEL, 0x248c), LPC_ICH3M},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) { PCI_VDEVICE(INTEL, 0x24c0), LPC_ICH4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) { PCI_VDEVICE(INTEL, 0x24cc), LPC_ICH4M},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) { PCI_VDEVICE(INTEL, 0x24d0), LPC_ICH5},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) { PCI_VDEVICE(INTEL, 0x25a1), LPC_6300ESB},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) { PCI_VDEVICE(INTEL, 0x2640), LPC_ICH6},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) { PCI_VDEVICE(INTEL, 0x2641), LPC_ICH6M},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) { PCI_VDEVICE(INTEL, 0x2642), LPC_ICH6W},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) { PCI_VDEVICE(INTEL, 0x2670), LPC_631XESB},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) { PCI_VDEVICE(INTEL, 0x2671), LPC_631XESB},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) { PCI_VDEVICE(INTEL, 0x2672), LPC_631XESB},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) { PCI_VDEVICE(INTEL, 0x2673), LPC_631XESB},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) { PCI_VDEVICE(INTEL, 0x2674), LPC_631XESB},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) { PCI_VDEVICE(INTEL, 0x2675), LPC_631XESB},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) { PCI_VDEVICE(INTEL, 0x2676), LPC_631XESB},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) { PCI_VDEVICE(INTEL, 0x2677), LPC_631XESB},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) { PCI_VDEVICE(INTEL, 0x2678), LPC_631XESB},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) { PCI_VDEVICE(INTEL, 0x2679), LPC_631XESB},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) { PCI_VDEVICE(INTEL, 0x267a), LPC_631XESB},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) { PCI_VDEVICE(INTEL, 0x267b), LPC_631XESB},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) { PCI_VDEVICE(INTEL, 0x267c), LPC_631XESB},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) { PCI_VDEVICE(INTEL, 0x267d), LPC_631XESB},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) { PCI_VDEVICE(INTEL, 0x267e), LPC_631XESB},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) { PCI_VDEVICE(INTEL, 0x267f), LPC_631XESB},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) { PCI_VDEVICE(INTEL, 0x27b0), LPC_ICH7DH},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) { PCI_VDEVICE(INTEL, 0x27b8), LPC_ICH7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) { PCI_VDEVICE(INTEL, 0x27b9), LPC_ICH7M},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) { PCI_VDEVICE(INTEL, 0x27bc), LPC_NM10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) { PCI_VDEVICE(INTEL, 0x27bd), LPC_ICH7MDH},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) { PCI_VDEVICE(INTEL, 0x2810), LPC_ICH8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) { PCI_VDEVICE(INTEL, 0x2811), LPC_ICH8ME},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) { PCI_VDEVICE(INTEL, 0x2812), LPC_ICH8DH},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) { PCI_VDEVICE(INTEL, 0x2814), LPC_ICH8DO},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) { PCI_VDEVICE(INTEL, 0x2815), LPC_ICH8M},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) { PCI_VDEVICE(INTEL, 0x2912), LPC_ICH9DH},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) { PCI_VDEVICE(INTEL, 0x2914), LPC_ICH9DO},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) { PCI_VDEVICE(INTEL, 0x2916), LPC_ICH9R},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) { PCI_VDEVICE(INTEL, 0x2917), LPC_ICH9ME},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) { PCI_VDEVICE(INTEL, 0x2918), LPC_ICH9},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) { PCI_VDEVICE(INTEL, 0x2919), LPC_ICH9M},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) { PCI_VDEVICE(INTEL, 0x3197), LPC_GLK},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) { PCI_VDEVICE(INTEL, 0x2b9c), LPC_COUGARMOUNTAIN},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) { PCI_VDEVICE(INTEL, 0x3a14), LPC_ICH10DO},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) { PCI_VDEVICE(INTEL, 0x3a16), LPC_ICH10R},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) { PCI_VDEVICE(INTEL, 0x3a18), LPC_ICH10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) { PCI_VDEVICE(INTEL, 0x3a1a), LPC_ICH10D},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) { PCI_VDEVICE(INTEL, 0x3b00), LPC_PCH},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) { PCI_VDEVICE(INTEL, 0x3b01), LPC_PCHM},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) { PCI_VDEVICE(INTEL, 0x3b02), LPC_P55},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) { PCI_VDEVICE(INTEL, 0x3b03), LPC_PM55},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) { PCI_VDEVICE(INTEL, 0x3b06), LPC_H55},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) { PCI_VDEVICE(INTEL, 0x3b07), LPC_QM57},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) { PCI_VDEVICE(INTEL, 0x3b08), LPC_H57},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) { PCI_VDEVICE(INTEL, 0x3b09), LPC_HM55},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) { PCI_VDEVICE(INTEL, 0x3b0a), LPC_Q57},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) { PCI_VDEVICE(INTEL, 0x3b0b), LPC_HM57},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) { PCI_VDEVICE(INTEL, 0x3b0d), LPC_PCHMSFF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) { PCI_VDEVICE(INTEL, 0x3b0f), LPC_QS57},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) { PCI_VDEVICE(INTEL, 0x3b12), LPC_3400},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) { PCI_VDEVICE(INTEL, 0x3b14), LPC_3420},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) { PCI_VDEVICE(INTEL, 0x3b16), LPC_3450},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) { PCI_VDEVICE(INTEL, 0x5031), LPC_EP80579},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) { PCI_VDEVICE(INTEL, 0x5ae8), LPC_APL},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) { PCI_VDEVICE(INTEL, 0x8c40), LPC_LPT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) { PCI_VDEVICE(INTEL, 0x8c41), LPC_LPT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) { PCI_VDEVICE(INTEL, 0x8c42), LPC_LPT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) { PCI_VDEVICE(INTEL, 0x8c43), LPC_LPT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) { PCI_VDEVICE(INTEL, 0x8c44), LPC_LPT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) { PCI_VDEVICE(INTEL, 0x8c45), LPC_LPT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) { PCI_VDEVICE(INTEL, 0x8c46), LPC_LPT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) { PCI_VDEVICE(INTEL, 0x8c47), LPC_LPT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) { PCI_VDEVICE(INTEL, 0x8c48), LPC_LPT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) { PCI_VDEVICE(INTEL, 0x8c49), LPC_LPT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) { PCI_VDEVICE(INTEL, 0x8c4a), LPC_LPT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) { PCI_VDEVICE(INTEL, 0x8c4b), LPC_LPT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) { PCI_VDEVICE(INTEL, 0x8c4c), LPC_LPT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) { PCI_VDEVICE(INTEL, 0x8c4d), LPC_LPT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) { PCI_VDEVICE(INTEL, 0x8c4e), LPC_LPT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) { PCI_VDEVICE(INTEL, 0x8c4f), LPC_LPT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) { PCI_VDEVICE(INTEL, 0x8c50), LPC_LPT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) { PCI_VDEVICE(INTEL, 0x8c51), LPC_LPT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) { PCI_VDEVICE(INTEL, 0x8c52), LPC_LPT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) { PCI_VDEVICE(INTEL, 0x8c53), LPC_LPT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) { PCI_VDEVICE(INTEL, 0x8c54), LPC_LPT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) { PCI_VDEVICE(INTEL, 0x8c55), LPC_LPT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) { PCI_VDEVICE(INTEL, 0x8c56), LPC_LPT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) { PCI_VDEVICE(INTEL, 0x8c57), LPC_LPT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) { PCI_VDEVICE(INTEL, 0x8c58), LPC_LPT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) { PCI_VDEVICE(INTEL, 0x8c59), LPC_LPT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) { PCI_VDEVICE(INTEL, 0x8c5a), LPC_LPT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) { PCI_VDEVICE(INTEL, 0x8c5b), LPC_LPT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) { PCI_VDEVICE(INTEL, 0x8c5c), LPC_LPT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) { PCI_VDEVICE(INTEL, 0x8c5d), LPC_LPT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) { PCI_VDEVICE(INTEL, 0x8c5e), LPC_LPT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) { PCI_VDEVICE(INTEL, 0x8c5f), LPC_LPT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) { PCI_VDEVICE(INTEL, 0x8cc1), LPC_9S},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) { PCI_VDEVICE(INTEL, 0x8cc2), LPC_9S},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) { PCI_VDEVICE(INTEL, 0x8cc3), LPC_9S},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) { PCI_VDEVICE(INTEL, 0x8cc4), LPC_9S},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) { PCI_VDEVICE(INTEL, 0x8cc6), LPC_9S},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) { PCI_VDEVICE(INTEL, 0x8d40), LPC_WBG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) { PCI_VDEVICE(INTEL, 0x8d41), LPC_WBG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) { PCI_VDEVICE(INTEL, 0x8d42), LPC_WBG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) { PCI_VDEVICE(INTEL, 0x8d43), LPC_WBG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) { PCI_VDEVICE(INTEL, 0x8d44), LPC_WBG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) { PCI_VDEVICE(INTEL, 0x8d45), LPC_WBG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) { PCI_VDEVICE(INTEL, 0x8d46), LPC_WBG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) { PCI_VDEVICE(INTEL, 0x8d47), LPC_WBG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) { PCI_VDEVICE(INTEL, 0x8d48), LPC_WBG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) { PCI_VDEVICE(INTEL, 0x8d49), LPC_WBG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) { PCI_VDEVICE(INTEL, 0x8d4a), LPC_WBG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) { PCI_VDEVICE(INTEL, 0x8d4b), LPC_WBG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) { PCI_VDEVICE(INTEL, 0x8d4c), LPC_WBG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) { PCI_VDEVICE(INTEL, 0x8d4d), LPC_WBG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) { PCI_VDEVICE(INTEL, 0x8d4e), LPC_WBG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) { PCI_VDEVICE(INTEL, 0x8d4f), LPC_WBG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) { PCI_VDEVICE(INTEL, 0x8d50), LPC_WBG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) { PCI_VDEVICE(INTEL, 0x8d51), LPC_WBG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) { PCI_VDEVICE(INTEL, 0x8d52), LPC_WBG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) { PCI_VDEVICE(INTEL, 0x8d53), LPC_WBG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) { PCI_VDEVICE(INTEL, 0x8d54), LPC_WBG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) { PCI_VDEVICE(INTEL, 0x8d55), LPC_WBG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) { PCI_VDEVICE(INTEL, 0x8d56), LPC_WBG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) { PCI_VDEVICE(INTEL, 0x8d57), LPC_WBG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) { PCI_VDEVICE(INTEL, 0x8d58), LPC_WBG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) { PCI_VDEVICE(INTEL, 0x8d59), LPC_WBG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) { PCI_VDEVICE(INTEL, 0x8d5a), LPC_WBG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) { PCI_VDEVICE(INTEL, 0x8d5b), LPC_WBG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) { PCI_VDEVICE(INTEL, 0x8d5c), LPC_WBG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) { PCI_VDEVICE(INTEL, 0x8d5d), LPC_WBG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) { PCI_VDEVICE(INTEL, 0x8d5e), LPC_WBG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) { PCI_VDEVICE(INTEL, 0x8d5f), LPC_WBG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) { PCI_VDEVICE(INTEL, 0x9c40), LPC_LPT_LP},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) { PCI_VDEVICE(INTEL, 0x9c41), LPC_LPT_LP},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) { PCI_VDEVICE(INTEL, 0x9c42), LPC_LPT_LP},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) { PCI_VDEVICE(INTEL, 0x9c43), LPC_LPT_LP},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) { PCI_VDEVICE(INTEL, 0x9c44), LPC_LPT_LP},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) { PCI_VDEVICE(INTEL, 0x9c45), LPC_LPT_LP},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) { PCI_VDEVICE(INTEL, 0x9c46), LPC_LPT_LP},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) { PCI_VDEVICE(INTEL, 0x9c47), LPC_LPT_LP},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) { PCI_VDEVICE(INTEL, 0x9cc1), LPC_WPT_LP},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) { PCI_VDEVICE(INTEL, 0x9cc2), LPC_WPT_LP},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) { PCI_VDEVICE(INTEL, 0x9cc3), LPC_WPT_LP},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) { PCI_VDEVICE(INTEL, 0x9cc5), LPC_WPT_LP},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) { PCI_VDEVICE(INTEL, 0x9cc6), LPC_WPT_LP},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) { PCI_VDEVICE(INTEL, 0x9cc7), LPC_WPT_LP},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) { PCI_VDEVICE(INTEL, 0x9cc9), LPC_WPT_LP},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) { PCI_VDEVICE(INTEL, 0xa1c1), LPC_LEWISBURG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) { PCI_VDEVICE(INTEL, 0xa1c2), LPC_LEWISBURG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) { PCI_VDEVICE(INTEL, 0xa1c3), LPC_LEWISBURG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) { PCI_VDEVICE(INTEL, 0xa1c4), LPC_LEWISBURG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) { PCI_VDEVICE(INTEL, 0xa1c5), LPC_LEWISBURG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) { PCI_VDEVICE(INTEL, 0xa1c6), LPC_LEWISBURG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) { PCI_VDEVICE(INTEL, 0xa1c7), LPC_LEWISBURG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) { PCI_VDEVICE(INTEL, 0xa242), LPC_LEWISBURG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) { PCI_VDEVICE(INTEL, 0xa243), LPC_LEWISBURG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) { 0, }, /* End of list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) MODULE_DEVICE_TABLE(pci, lpc_ich_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) static void lpc_ich_restore_config_space(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) struct lpc_ich_priv *priv = pci_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) if (priv->abase_save >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) pci_write_config_byte(dev, priv->abase, priv->abase_save);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) priv->abase_save = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) if (priv->actrl_pbase_save >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) pci_write_config_byte(dev, priv->actrl_pbase,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) priv->actrl_pbase_save);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) priv->actrl_pbase_save = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) if (priv->gctrl_save >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) pci_write_config_byte(dev, priv->gctrl, priv->gctrl_save);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) priv->gctrl_save = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) static void lpc_ich_enable_acpi_space(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) struct lpc_ich_priv *priv = pci_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) u8 reg_save;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) switch (lpc_chipset_info[priv->chipset].iTCO_version) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) * Some chipsets (eg Avoton) enable the ACPI space in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) * ACPI BASE register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) pci_read_config_byte(dev, priv->abase, ®_save);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) pci_write_config_byte(dev, priv->abase, reg_save | 0x2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) priv->abase_save = reg_save;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) * Most chipsets enable the ACPI space in the ACPI control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) * register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) pci_read_config_byte(dev, priv->actrl_pbase, ®_save);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) pci_write_config_byte(dev, priv->actrl_pbase, reg_save | 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) priv->actrl_pbase_save = reg_save;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) static void lpc_ich_enable_gpio_space(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) struct lpc_ich_priv *priv = pci_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) u8 reg_save;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) pci_read_config_byte(dev, priv->gctrl, ®_save);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) pci_write_config_byte(dev, priv->gctrl, reg_save | 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) priv->gctrl_save = reg_save;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) static void lpc_ich_enable_pmc_space(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) struct lpc_ich_priv *priv = pci_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) u8 reg_save;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) pci_read_config_byte(dev, priv->actrl_pbase, ®_save);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) pci_write_config_byte(dev, priv->actrl_pbase, reg_save | 0x2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) priv->actrl_pbase_save = reg_save;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) static int lpc_ich_finalize_wdt_cell(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) struct itco_wdt_platform_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) struct lpc_ich_priv *priv = pci_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) struct lpc_ich_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) struct mfd_cell *cell = &lpc_ich_wdt_cell;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) pdata = devm_kzalloc(&dev->dev, sizeof(*pdata), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) if (!pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) info = &lpc_chipset_info[priv->chipset];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) pdata->version = info->iTCO_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) strlcpy(pdata->name, info->name, sizeof(pdata->name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) cell->platform_data = pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) cell->pdata_size = sizeof(*pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) static void lpc_ich_finalize_gpio_cell(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) struct lpc_ich_priv *priv = pci_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) struct mfd_cell *cell = &lpc_ich_gpio_cell;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) cell->platform_data = &lpc_chipset_info[priv->chipset];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) cell->pdata_size = sizeof(struct lpc_ich_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) * We don't check for resource conflict globally. There are 2 or 3 independent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) * GPIO groups and it's enough to have access to one of these to instantiate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) * the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) static int lpc_ich_check_conflict_gpio(struct resource *res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) u8 use_gpio = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) if (resource_size(res) >= 0x50 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) !acpi_check_region(res->start + 0x40, 0x10, "LPC ICH GPIO3"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) use_gpio |= 1 << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) if (!acpi_check_region(res->start + 0x30, 0x10, "LPC ICH GPIO2"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) use_gpio |= 1 << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) ret = acpi_check_region(res->start + 0x00, 0x30, "LPC ICH GPIO1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) use_gpio |= 1 << 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) return use_gpio ? use_gpio : ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) static int lpc_ich_init_gpio(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) struct lpc_ich_priv *priv = pci_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) u32 base_addr_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) u32 base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) bool acpi_conflict = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) /* Setup power management base register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) pci_read_config_dword(dev, priv->abase, &base_addr_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) base_addr = base_addr_cfg & 0x0000ff80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) if (!base_addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) dev_notice(&dev->dev, "I/O space for ACPI uninitialized\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) lpc_ich_gpio_cell.num_resources--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) goto gpe0_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) res = &gpio_ich_res[ICH_RES_GPE0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) res->start = base_addr + ACPIBASE_GPE_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) res->end = base_addr + ACPIBASE_GPE_END;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) ret = acpi_check_resource_conflict(res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) * This isn't fatal for the GPIO, but we have to make sure that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) * the platform_device subsystem doesn't see this resource
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) * or it will register an invalid region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) lpc_ich_gpio_cell.num_resources--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) acpi_conflict = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) lpc_ich_enable_acpi_space(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) gpe0_done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) /* Setup GPIO base register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) pci_read_config_dword(dev, priv->gbase, &base_addr_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) base_addr = base_addr_cfg & 0x0000ff80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) if (!base_addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) dev_notice(&dev->dev, "I/O space for GPIO uninitialized\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) goto gpio_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) /* Older devices provide fewer GPIO and have a smaller resource size. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) res = &gpio_ich_res[ICH_RES_GPIO];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) res->start = base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) switch (lpc_chipset_info[priv->chipset].gpio_version) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) case ICH_V5_GPIO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) case ICH_V10CORP_GPIO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) res->end = res->start + 128 - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) res->end = res->start + 64 - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) ret = lpc_ich_check_conflict_gpio(res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) /* this isn't necessarily fatal for the GPIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) acpi_conflict = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) goto gpio_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) lpc_chipset_info[priv->chipset].use_gpio = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) lpc_ich_enable_gpio_space(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) lpc_ich_finalize_gpio_cell(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) ret = mfd_add_devices(&dev->dev, PLATFORM_DEVID_AUTO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) &lpc_ich_gpio_cell, 1, NULL, 0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) gpio_done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) if (acpi_conflict)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) pr_warn("Resource conflict(s) found affecting %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) lpc_ich_gpio_cell.name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) static int lpc_ich_init_wdt(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) struct lpc_ich_priv *priv = pci_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) u32 base_addr_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) u32 base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) /* If we have ACPI based watchdog use that instead */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) if (acpi_has_watchdog())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) /* Setup power management base register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) pci_read_config_dword(dev, priv->abase, &base_addr_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) base_addr = base_addr_cfg & 0x0000ff80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) if (!base_addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) dev_notice(&dev->dev, "I/O space for ACPI uninitialized\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) goto wdt_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) res = wdt_io_res(ICH_RES_IO_TCO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) res->start = base_addr + ACPIBASE_TCO_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) res->end = base_addr + ACPIBASE_TCO_END;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) res = wdt_io_res(ICH_RES_IO_SMI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) res->start = base_addr + ACPIBASE_SMI_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) res->end = base_addr + ACPIBASE_SMI_END;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) lpc_ich_enable_acpi_space(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) * iTCO v2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) * Get the Memory-Mapped GCS register. To get access to it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) * we have to read RCBA from PCI Config space 0xf0 and use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) * it as base. GCS = RCBA + ICH6_GCS(0x3410).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) * iTCO v3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) * Get the Power Management Configuration register. To get access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) * to it we have to read the PMC BASE from config space and address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) * the register at offset 0x8.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) if (lpc_chipset_info[priv->chipset].iTCO_version == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) /* Don't register iomem for TCO ver 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) lpc_ich_wdt_cell.num_resources--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) } else if (lpc_chipset_info[priv->chipset].iTCO_version == 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) pci_read_config_dword(dev, RCBABASE, &base_addr_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) base_addr = base_addr_cfg & 0xffffc000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) if (!(base_addr_cfg & 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) dev_notice(&dev->dev, "RCBA is disabled by "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) "hardware/BIOS, device disabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) goto wdt_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) res = wdt_mem_res(ICH_RES_MEM_GCS_PMC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) res->start = base_addr + ACPIBASE_GCS_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) res->end = base_addr + ACPIBASE_GCS_END;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) } else if (lpc_chipset_info[priv->chipset].iTCO_version == 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) lpc_ich_enable_pmc_space(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) pci_read_config_dword(dev, ACPICTRL_PMCBASE, &base_addr_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) base_addr = base_addr_cfg & 0xfffffe00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) res = wdt_mem_res(ICH_RES_MEM_GCS_PMC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) res->start = base_addr + ACPIBASE_PMC_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) res->end = base_addr + ACPIBASE_PMC_END;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) ret = lpc_ich_finalize_wdt_cell(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) goto wdt_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) ret = mfd_add_devices(&dev->dev, PLATFORM_DEVID_AUTO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) &lpc_ich_wdt_cell, 1, NULL, 0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) wdt_done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) static int lpc_ich_init_spi(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) struct lpc_ich_priv *priv = pci_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) struct resource *res = &intel_spi_res[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) struct intel_spi_boardinfo *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) u32 spi_base, rcba, bcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) info = devm_kzalloc(&dev->dev, sizeof(*info), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) if (!info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) info->type = lpc_chipset_info[priv->chipset].spi_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) switch (info->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) case INTEL_SPI_BYT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) pci_read_config_dword(dev, SPIBASE_BYT, &spi_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) if (spi_base & SPIBASE_BYT_EN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) res->start = spi_base & ~(SPIBASE_BYT_SZ - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) res->end = res->start + SPIBASE_BYT_SZ - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) case INTEL_SPI_LPT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) pci_read_config_dword(dev, RCBABASE, &rcba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) if (rcba & 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) spi_base = round_down(rcba, SPIBASE_LPT_SZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) res->start = spi_base + SPIBASE_LPT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) res->end = res->start + SPIBASE_LPT_SZ - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) pci_read_config_dword(dev, BCR, &bcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) info->writeable = !!(bcr & BCR_WPD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) case INTEL_SPI_BXT: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) unsigned int p2sb = PCI_DEVFN(13, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) unsigned int spi = PCI_DEVFN(13, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) struct pci_bus *bus = dev->bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) * The P2SB is hidden by BIOS and we need to unhide it in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) * order to read BAR of the SPI flash device. Once that is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) * done we hide it again.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) pci_bus_write_config_byte(bus, p2sb, 0xe1, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) pci_bus_read_config_dword(bus, spi, PCI_BASE_ADDRESS_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) &spi_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) if (spi_base != ~0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) res->start = spi_base & 0xfffffff0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) res->end = res->start + SPIBASE_APL_SZ - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) pci_bus_read_config_dword(bus, spi, BCR, &bcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) info->writeable = !!(bcr & BCR_WPD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) pci_bus_write_config_byte(bus, p2sb, 0xe1, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) if (!res->start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) lpc_ich_spi_cell.platform_data = info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) lpc_ich_spi_cell.pdata_size = sizeof(*info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) return mfd_add_devices(&dev->dev, PLATFORM_DEVID_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) &lpc_ich_spi_cell, 1, NULL, 0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) static int lpc_ich_probe(struct pci_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) struct lpc_ich_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) bool cell_added = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) priv = devm_kzalloc(&dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) sizeof(struct lpc_ich_priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) priv->chipset = id->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) priv->actrl_pbase_save = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) priv->abase_save = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) priv->abase = ACPIBASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) priv->actrl_pbase = ACPICTRL_PMCBASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) priv->gctrl_save = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) if (priv->chipset <= LPC_ICH5) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) priv->gbase = GPIOBASE_ICH0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) priv->gctrl = GPIOCTRL_ICH0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) priv->gbase = GPIOBASE_ICH6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) priv->gctrl = GPIOCTRL_ICH6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) pci_set_drvdata(dev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) if (lpc_chipset_info[priv->chipset].iTCO_version) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) ret = lpc_ich_init_wdt(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) cell_added = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) if (lpc_chipset_info[priv->chipset].gpio_version) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) ret = lpc_ich_init_gpio(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) cell_added = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) if (lpc_chipset_info[priv->chipset].spi_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) ret = lpc_ich_init_spi(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) cell_added = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) * We only care if at least one or none of the cells registered
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) * successfully.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) if (!cell_added) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) dev_warn(&dev->dev, "No MFD cells added\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) lpc_ich_restore_config_space(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) static void lpc_ich_remove(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) mfd_remove_devices(&dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) lpc_ich_restore_config_space(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) static struct pci_driver lpc_ich_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) .name = "lpc_ich",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) .id_table = lpc_ich_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) .probe = lpc_ich_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) .remove = lpc_ich_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) module_pci_driver(lpc_ich_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) MODULE_AUTHOR("Aaron Sierra <asierra@xes-inc.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) MODULE_DESCRIPTION("LPC interface for Intel ICH");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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