Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Lochnagar I2C bus interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (c) 2012-2018 Cirrus Logic, Inc. and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *                         Cirrus Logic International Semiconductor Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Author: Charles Keepax <ckeepax@opensource.cirrus.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/lockdep.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/mfd/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/mfd/lochnagar.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <linux/mfd/lochnagar1_regs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <linux/mfd/lochnagar2_regs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define LOCHNAGAR_BOOT_RETRIES		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define LOCHNAGAR_BOOT_DELAY_MS		350
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define LOCHNAGAR_CONFIG_POLL_US	10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) static bool lochnagar1_readable_register(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	case LOCHNAGAR_SOFTWARE_RESET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	case LOCHNAGAR_FIRMWARE_ID1...LOCHNAGAR_FIRMWARE_ID2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	case LOCHNAGAR1_CDC_AIF1_SEL...LOCHNAGAR1_CDC_AIF3_SEL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	case LOCHNAGAR1_CDC_MCLK1_SEL...LOCHNAGAR1_CDC_MCLK2_SEL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	case LOCHNAGAR1_CDC_AIF_CTRL1...LOCHNAGAR1_CDC_AIF_CTRL2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	case LOCHNAGAR1_EXT_AIF_CTRL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	case LOCHNAGAR1_DSP_AIF1_SEL...LOCHNAGAR1_DSP_AIF2_SEL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	case LOCHNAGAR1_DSP_CLKIN_SEL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	case LOCHNAGAR1_DSP_AIF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	case LOCHNAGAR1_GF_AIF1...LOCHNAGAR1_GF_AIF2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	case LOCHNAGAR1_PSIA_AIF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	case LOCHNAGAR1_PSIA1_SEL...LOCHNAGAR1_PSIA2_SEL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	case LOCHNAGAR1_SPDIF_AIF_SEL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	case LOCHNAGAR1_GF_AIF3_SEL...LOCHNAGAR1_GF_AIF4_SEL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	case LOCHNAGAR1_GF_CLKOUT1_SEL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	case LOCHNAGAR1_GF_AIF1_SEL...LOCHNAGAR1_GF_AIF2_SEL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	case LOCHNAGAR1_GF_GPIO2...LOCHNAGAR1_GF_GPIO7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	case LOCHNAGAR1_RST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	case LOCHNAGAR1_LED1...LOCHNAGAR1_LED2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	case LOCHNAGAR1_I2C_CTRL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 		return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 		return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) static const struct regmap_config lochnagar1_i2c_regmap = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	.reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	.val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	.reg_format_endian = REGMAP_ENDIAN_BIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	.val_format_endian = REGMAP_ENDIAN_BIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	.max_register = 0x50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	.readable_reg = lochnagar1_readable_register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	.use_single_read = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	.use_single_write = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	.cache_type = REGCACHE_RBTREE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) static const struct reg_sequence lochnagar1_patch[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	{ 0x40, 0x0083 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	{ 0x47, 0x0018 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	{ 0x50, 0x0000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) static bool lochnagar2_readable_register(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	case LOCHNAGAR_SOFTWARE_RESET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	case LOCHNAGAR_FIRMWARE_ID1...LOCHNAGAR_FIRMWARE_ID2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	case LOCHNAGAR2_CDC_AIF1_CTRL...LOCHNAGAR2_CDC_AIF3_CTRL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	case LOCHNAGAR2_DSP_AIF1_CTRL...LOCHNAGAR2_DSP_AIF2_CTRL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	case LOCHNAGAR2_PSIA1_CTRL...LOCHNAGAR2_PSIA2_CTRL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	case LOCHNAGAR2_GF_AIF3_CTRL...LOCHNAGAR2_GF_AIF4_CTRL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	case LOCHNAGAR2_GF_AIF1_CTRL...LOCHNAGAR2_GF_AIF2_CTRL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	case LOCHNAGAR2_SPDIF_AIF_CTRL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	case LOCHNAGAR2_USB_AIF1_CTRL...LOCHNAGAR2_USB_AIF2_CTRL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	case LOCHNAGAR2_ADAT_AIF_CTRL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	case LOCHNAGAR2_CDC_MCLK1_CTRL...LOCHNAGAR2_CDC_MCLK2_CTRL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	case LOCHNAGAR2_DSP_CLKIN_CTRL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	case LOCHNAGAR2_PSIA1_MCLK_CTRL...LOCHNAGAR2_PSIA2_MCLK_CTRL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	case LOCHNAGAR2_SPDIF_MCLK_CTRL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	case LOCHNAGAR2_GF_CLKOUT1_CTRL...LOCHNAGAR2_GF_CLKOUT2_CTRL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	case LOCHNAGAR2_ADAT_MCLK_CTRL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	case LOCHNAGAR2_SOUNDCARD_MCLK_CTRL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	case LOCHNAGAR2_GPIO_FPGA_GPIO1...LOCHNAGAR2_GPIO_FPGA_GPIO6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	case LOCHNAGAR2_GPIO_CDC_GPIO1...LOCHNAGAR2_GPIO_CDC_GPIO8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	case LOCHNAGAR2_GPIO_DSP_GPIO1...LOCHNAGAR2_GPIO_DSP_GPIO6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	case LOCHNAGAR2_GPIO_GF_GPIO2...LOCHNAGAR2_GPIO_GF_GPIO7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	case LOCHNAGAR2_GPIO_CDC_AIF1_BCLK...LOCHNAGAR2_GPIO_CDC_AIF3_TXDAT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	case LOCHNAGAR2_GPIO_DSP_AIF1_BCLK...LOCHNAGAR2_GPIO_DSP_AIF2_TXDAT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	case LOCHNAGAR2_GPIO_PSIA1_BCLK...LOCHNAGAR2_GPIO_PSIA2_TXDAT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	case LOCHNAGAR2_GPIO_GF_AIF3_BCLK...LOCHNAGAR2_GPIO_GF_AIF4_TXDAT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	case LOCHNAGAR2_GPIO_GF_AIF1_BCLK...LOCHNAGAR2_GPIO_GF_AIF2_TXDAT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	case LOCHNAGAR2_GPIO_DSP_UART1_RX...LOCHNAGAR2_GPIO_DSP_UART2_TX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	case LOCHNAGAR2_GPIO_GF_UART2_RX...LOCHNAGAR2_GPIO_GF_UART2_TX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	case LOCHNAGAR2_GPIO_USB_UART_RX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	case LOCHNAGAR2_GPIO_CDC_PDMCLK1...LOCHNAGAR2_GPIO_CDC_PDMDAT2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	case LOCHNAGAR2_GPIO_CDC_DMICCLK1...LOCHNAGAR2_GPIO_CDC_DMICDAT4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	case LOCHNAGAR2_GPIO_DSP_DMICCLK1...LOCHNAGAR2_GPIO_DSP_DMICDAT2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	case LOCHNAGAR2_GPIO_I2C2_SCL...LOCHNAGAR2_GPIO_I2C4_SDA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	case LOCHNAGAR2_GPIO_DSP_STANDBY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	case LOCHNAGAR2_GPIO_CDC_MCLK1...LOCHNAGAR2_GPIO_CDC_MCLK2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	case LOCHNAGAR2_GPIO_DSP_CLKIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	case LOCHNAGAR2_GPIO_PSIA1_MCLK...LOCHNAGAR2_GPIO_PSIA2_MCLK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	case LOCHNAGAR2_GPIO_GF_GPIO1...LOCHNAGAR2_GPIO_GF_GPIO5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	case LOCHNAGAR2_GPIO_DSP_GPIO20:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	case LOCHNAGAR2_GPIO_CHANNEL1...LOCHNAGAR2_GPIO_CHANNEL16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	case LOCHNAGAR2_MINICARD_RESETS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	case LOCHNAGAR2_ANALOGUE_PATH_CTRL1...LOCHNAGAR2_ANALOGUE_PATH_CTRL2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	case LOCHNAGAR2_COMMS_CTRL4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	case LOCHNAGAR2_SPDIF_CTRL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	case LOCHNAGAR2_IMON_CTRL1...LOCHNAGAR2_IMON_CTRL4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	case LOCHNAGAR2_IMON_DATA1...LOCHNAGAR2_IMON_DATA2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	case LOCHNAGAR2_POWER_CTRL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	case LOCHNAGAR2_MICVDD_CTRL1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	case LOCHNAGAR2_MICVDD_CTRL2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	case LOCHNAGAR2_VDDCORE_CDC_CTRL1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	case LOCHNAGAR2_VDDCORE_CDC_CTRL2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	case LOCHNAGAR2_SOUNDCARD_AIF_CTRL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static bool lochnagar2_volatile_register(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	case LOCHNAGAR2_GPIO_CHANNEL1...LOCHNAGAR2_GPIO_CHANNEL16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	case LOCHNAGAR2_ANALOGUE_PATH_CTRL1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	case LOCHNAGAR2_IMON_CTRL3...LOCHNAGAR2_IMON_CTRL4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	case LOCHNAGAR2_IMON_DATA1...LOCHNAGAR2_IMON_DATA2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static const struct regmap_config lochnagar2_i2c_regmap = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	.reg_bits = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	.val_bits = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	.reg_format_endian = REGMAP_ENDIAN_BIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	.val_format_endian = REGMAP_ENDIAN_BIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	.max_register = 0x1F1F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	.readable_reg = lochnagar2_readable_register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	.volatile_reg = lochnagar2_volatile_register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	.cache_type = REGCACHE_RBTREE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static const struct reg_sequence lochnagar2_patch[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	{ 0x00EE, 0x0000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) struct lochnagar_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	const char * const name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	enum lochnagar_type type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	const struct regmap_config *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	const struct reg_sequence *patch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	int npatch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static struct lochnagar_config lochnagar_configs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		.id = 0x50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		.name = "lochnagar1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		.type = LOCHNAGAR1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		.regmap = &lochnagar1_i2c_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		.patch = lochnagar1_patch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		.npatch = ARRAY_SIZE(lochnagar1_patch),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		.id = 0xCB58,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		.name = "lochnagar2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		.type = LOCHNAGAR2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		.regmap = &lochnagar2_i2c_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		.patch = lochnagar2_patch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		.npatch = ARRAY_SIZE(lochnagar2_patch),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static const struct of_device_id lochnagar_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	{ .compatible = "cirrus,lochnagar1", .data = &lochnagar_configs[0] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	{ .compatible = "cirrus,lochnagar2", .data = &lochnagar_configs[1] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static int lochnagar_wait_for_boot(struct regmap *regmap, unsigned int *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	for (i = 0; i < LOCHNAGAR_BOOT_RETRIES; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		msleep(LOCHNAGAR_BOOT_DELAY_MS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		/* The reset register will return the device ID when read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		ret = regmap_read(regmap, LOCHNAGAR_SOFTWARE_RESET, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)  * lochnagar_update_config - Synchronise the boards analogue configuration to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)  *                           the hardware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)  * @lochnagar: A pointer to the primary core data structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)  * Return: Zero on success or an appropriate negative error code on failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) int lochnagar_update_config(struct lochnagar *lochnagar)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	struct regmap *regmap = lochnagar->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	unsigned int done = LOCHNAGAR2_ANALOGUE_PATH_UPDATE_STS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	int timeout_ms = LOCHNAGAR_BOOT_DELAY_MS * LOCHNAGAR_BOOT_RETRIES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	unsigned int val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	lockdep_assert_held(&lochnagar->analogue_config_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	if (lochnagar->type != LOCHNAGAR2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	 * Toggle the ANALOGUE_PATH_UPDATE bit and wait for the device to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	 * acknowledge that any outstanding changes to the analogue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	 * configuration have been applied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	ret = regmap_write(regmap, LOCHNAGAR2_ANALOGUE_PATH_CTRL1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	ret = regmap_write(regmap, LOCHNAGAR2_ANALOGUE_PATH_CTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 			   LOCHNAGAR2_ANALOGUE_PATH_UPDATE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	ret = regmap_read_poll_timeout(regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 				       LOCHNAGAR2_ANALOGUE_PATH_CTRL1, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 				       (val & done), LOCHNAGAR_CONFIG_POLL_US,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 				       timeout_ms * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) EXPORT_SYMBOL_GPL(lochnagar_update_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static int lochnagar_i2c_probe(struct i2c_client *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	struct device *dev = &i2c->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	const struct lochnagar_config *config = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	const struct of_device_id *of_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	struct lochnagar *lochnagar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	struct gpio_desc *reset, *present;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	unsigned int firmwareid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	unsigned int devid, rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	lochnagar = devm_kzalloc(dev, sizeof(*lochnagar), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	if (!lochnagar)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	of_id = of_match_device(lochnagar_of_match, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	if (!of_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	config = of_id->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	lochnagar->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	mutex_init(&lochnagar->analogue_config_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	dev_set_drvdata(dev, lochnagar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	if (IS_ERR(reset)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 		ret = PTR_ERR(reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 		dev_err(dev, "Failed to get reset GPIO: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	present = devm_gpiod_get_optional(dev, "present", GPIOD_OUT_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	if (IS_ERR(present)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 		ret = PTR_ERR(present);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 		dev_err(dev, "Failed to get present GPIO: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	/* Leave the Lochnagar in reset for a reasonable amount of time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	/* Bring Lochnagar out of reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	gpiod_set_value_cansleep(reset, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	/* Identify Lochnagar */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	lochnagar->type = config->type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	lochnagar->regmap = devm_regmap_init_i2c(i2c, config->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	if (IS_ERR(lochnagar->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 		ret = PTR_ERR(lochnagar->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 		dev_err(dev, "Failed to allocate register map: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	/* Wait for Lochnagar to boot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	ret = lochnagar_wait_for_boot(lochnagar->regmap, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 		dev_err(dev, "Failed to read device ID: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	devid = val & LOCHNAGAR_DEVICE_ID_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	rev = val & LOCHNAGAR_REV_ID_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	if (devid != config->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 		dev_err(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 			"ID does not match %s (expected 0x%x got 0x%x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 			config->name, config->id, devid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	/* Identify firmware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	ret = regmap_read(lochnagar->regmap, LOCHNAGAR_FIRMWARE_ID1, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 		dev_err(dev, "Failed to read firmware id 1: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	firmwareid = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	ret = regmap_read(lochnagar->regmap, LOCHNAGAR_FIRMWARE_ID2, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 		dev_err(dev, "Failed to read firmware id 2: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	firmwareid |= (val << config->regmap->val_bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	dev_info(dev, "Found %s (0x%x) revision %u firmware 0x%.6x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 		 config->name, devid, rev + 1, firmwareid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	ret = regmap_register_patch(lochnagar->regmap, config->patch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 				    config->npatch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 		dev_err(dev, "Failed to register patch: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	ret = devm_of_platform_populate(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 		dev_err(dev, "Failed to populate child nodes: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) static struct i2c_driver lochnagar_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 		.name = "lochnagar",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 		.of_match_table = of_match_ptr(lochnagar_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 		.suppress_bind_attrs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	.probe_new = lochnagar_i2c_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) static int __init lochnagar_i2c_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	ret = i2c_add_driver(&lochnagar_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 		pr_err("Failed to register Lochnagar driver: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) subsys_initcall(lochnagar_i2c_init);